source: rtems/bsps/powerpc/mvme5500/start/start.S @ fbcd7c8f

Last change on this file since fbcd7c8f was fbcd7c8f, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 20, 2018 at 8:19:28 AM

bsps: Move start files to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*
2 *  start.S :     RTEMS entry point
3 *
4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
5 *
6 *  S. Kate Feng <feng1@bnl.gov>, April 2004
7 *  Mapped the 2nd 256MB of RAM to support the MVME5500/MVME6100 boards
8 *     
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 *
13 */
14
15#include <rtems/asm.h>
16#include <rtems/score/cpu.h>
17#include <rtems/powerpc/powerpc.h>
18
19#include <libcpu/io.h>
20#include <libcpu/bat.h>
21#include <bspopts.h>
22
23#define SYNC \
24        sync; \
25        isync
26
27#define KERNELBASE      0x0
28#define MEM256MB        0x10000000
29
30#define MONITOR_ENTER                   \
31        mfmsr   r10             ;       \
32        ori     r10,r10,MSR_IP  ;       \
33        mtmsr   r10             ;       \
34        li      r10,0x63        ;       \
35        sc
36
37        .text
38        .globl  __rtems_entry_point
39        .type   __rtems_entry_point,@function
40__rtems_entry_point:
41#ifdef DEBUG_EARLY_START
42        MONITOR_ENTER
43#endif
44
45/*
46 * PREP
47 * This is jumped to on prep systems right after the kernel is relocated
48 * to its proper place in memory by the boot loader.  The expected layout
49 * of the regs is:
50 *   r3: ptr to residual data
51 *   r4: initrd_start or if no initrd then 0
52 *   r5: initrd_end - unused if r4 is 0
53 *   r6: Start of command line string
54 *   r7: End of command line string
55 *
56 *   The Prep boot loader insure that the MMU is currently off...
57 *
58 */
59
60        mr      r31,r3                  /* save parameters */
61        mr      r30,r4
62        mr      r29,r5
63        mr      r28,r6
64        mr      r27,r7
65
66#ifdef __ALTIVEC__
67        /* enable altivec; gcc may use it! */
68        mfmsr r0
69        oris  r0, r0, (1<<(31-16-6))
70        mtmsr r0
71        isync
72        /*
73         * set vscr and vrsave to known values
74         */
75        li    r0, 0
76        mtvrsave r0
77        vxor   0,0,0
78        mtvscr 0
79#endif
80
81        /*
82         * Make sure we have nothing in BATS and TLB
83         */
84        bl      CPU_clear_bats_early
85        bl      flush_tlbs
86/*
87 * Use the first pair of BAT registers to map the 1st 256MB
88 * of RAM to KERNELBASE.
89 */
90        lis     r11,KERNELBASE@h
91/* set up BAT registers for 604 */
92        ori     r11,r11,0x1ffe
93        li      r8,2                    /* R/W access */
94        isync
95        mtspr   DBAT0L,r8               /* N.B. 6xx (not 601) have valid */
96        mtspr   DBAT0U,r11              /* bit in upper BAT register */
97        mtspr   IBAT0L,r8
98        mtspr   IBAT0U,r11
99        isync
100/*
101 * <skf> Use the 2nd pair of BAT registers to map the 2nd 256MB
102 * of RAM to 0x10000000.
103 */
104        lis     r11,MEM256MB@h
105        ori     r11,r11,0x1ffe          /* set up BAT1 registers for 604+ */
106        lis     r8,MEM256MB@h
107        ori     r8,r8,2
108        isync
109        mtspr   DBAT1L,r8               /* N.B. 6xx (not 601) have valid */
110        mtspr   DBAT1U,r11              /* bit in upper BAT register */
111        mtspr   IBAT1L,r8
112        mtspr   IBAT1U,r11
113        isync
114
115/*
116 * we now have the two 256M of ram mapped with the bats. We are still
117 * running on the bootloader stack and cannot switch to an RTEMS allocated
118 * init stack before copying the residual data that may have been set just
119 * after rtems_end address. This bug has been experienced on MVME2304. Thank
120 * to Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and
121 * suggesting the appropriate code.
122 */
123
124enter_C_code:
125        bl      MMUon
126        bl      __eabi  /* setup EABI and SYSV environment */
127        bl      zero_bss
128        /*
129         * restore prep boot params
130         */
131        mr      r3,r31
132        mr      r4,r30
133        mr      r5,r29
134        mr      r6,r28
135        mr      r7,r27
136        bl      save_boot_params
137        /*
138         * stack = &__rtems_end + 4096
139         */
140        addis   r9,r0, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@ha
141        addi    r9,r9, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@l
142        /*
143         * align initial stack
144         * (we hope that the bootloader stack was 16-byte aligned
145         * or we haven't used altivec yet...)
146         */
147        li   r0, (CPU_STACK_ALIGNMENT-1)
148        andc r1, r9, r0
149        /*
150         * NULL ptr to back chain
151         */
152        li   r0, 0
153        stw  r0, 0(r1)
154
155        /*
156         * We are now in a environment that is totally independent from
157         * bootloader setup.
158         */
159    /* pass result of 'save_boot_params' to 'boot_card' in R3 */
160        bl      boot_card
161        bl      _return_to_ppcbug
162
163        .globl  MMUon
164        .type   MMUon,@function
165MMUon:
166        mfmsr   r0
167        ori     r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
168#if (PPC_HAS_FPU == 0)
169        xori    r0, r0, MSR_EE | MSR_IP | MSR_FP
170#else
171        xori    r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1
172#endif
173        mflr    r11
174        mtsrr0  r11
175        mtsrr1  r0
176        SYNC
177        rfi
178
179        .globl  MMUoff
180        .type   MMUoff,@function
181MMUoff:
182        mfmsr   r0
183        ori     r0,r0,MSR_IR| MSR_DR | MSR_IP
184        mflr    r11
185        xori    r0,r0,MSR_IR|MSR_DR
186        mtsrr0  r11
187        mtsrr1  r0
188        SYNC
189        rfi
190
191        .globl  _return_to_ppcbug
192        .type   _return_to_ppcbug,@function
193
194_return_to_ppcbug:
195        mflr    r30
196        bl      MMUoff
197        MONITOR_ENTER
198        bl      MMUon
199        mtctr   r30
200        bctr
201
202flush_tlbs:
203        lis     r20, 0x1000
2041:      addic.  r20, r20, -0x1000
205        tlbie   r20
206        bgt     1b
207        sync
208        blr
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