source: rtems/bsps/powerpc/mvme5500/start/start.S @ 84e59b7c

Last change on this file since 84e59b7c was 84e59b7c, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 15, 2018 at 7:47:22 PM

bsps/powerpc: Use interrupt stack for init stack

Move start.o to separate file.

Update #3459.

  • Property mode set to 100644
File size: 4.0 KB
Line 
1/*
2 *  start.S :     RTEMS entry point
3 *
4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
5 *
6 *  S. Kate Feng <feng1@bnl.gov>, April 2004
7 *  Mapped the 2nd 256MB of RAM to support the MVME5500/MVME6100 boards
8 *     
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 *
13 */
14
15#include <rtems/asm.h>
16#include <libcpu/powerpc-utility.h>
17
18#include <libcpu/io.h>
19#include <libcpu/bat.h>
20#include <bspopts.h>
21
22#define SYNC \
23        sync; \
24        isync
25
26#define KERNELBASE      0x0
27#define MEM256MB        0x10000000
28
29#define MONITOR_ENTER                   \
30        mfmsr   r10             ;       \
31        ori     r10,r10,MSR_IP  ;       \
32        mtmsr   r10             ;       \
33        li      r10,0x63        ;       \
34        sc
35
36        .text
37        .globl  __rtems_entry_point
38        .type   __rtems_entry_point,@function
39__rtems_entry_point:
40#ifdef DEBUG_EARLY_START
41        MONITOR_ENTER
42#endif
43
44/*
45 * PREP
46 * This is jumped to on prep systems right after the kernel is relocated
47 * to its proper place in memory by the boot loader.  The expected layout
48 * of the regs is:
49 *   r3: ptr to residual data
50 *   r4: initrd_start or if no initrd then 0
51 *   r5: initrd_end - unused if r4 is 0
52 *   r6: Start of command line string
53 *   r7: End of command line string
54 *
55 *   The Prep boot loader insure that the MMU is currently off...
56 *
57 */
58
59        mr      r31,r3                  /* save parameters */
60        mr      r30,r4
61        mr      r29,r5
62        mr      r28,r6
63        mr      r27,r7
64
65#ifdef __ALTIVEC__
66        /* enable altivec; gcc may use it! */
67        mfmsr r0
68        oris  r0, r0, (1<<(31-16-6))
69        mtmsr r0
70        isync
71        /*
72         * set vscr and vrsave to known values
73         */
74        li    r0, 0
75        mtvrsave r0
76        vxor   0,0,0
77        mtvscr 0
78#endif
79
80        /*
81         * Make sure we have nothing in BATS and TLB
82         */
83        bl      CPU_clear_bats_early
84        bl      flush_tlbs
85/*
86 * Use the first pair of BAT registers to map the 1st 256MB
87 * of RAM to KERNELBASE.
88 */
89        lis     r11,KERNELBASE@h
90/* set up BAT registers for 604 */
91        ori     r11,r11,0x1ffe
92        li      r8,2                    /* R/W access */
93        isync
94        mtspr   DBAT0L,r8               /* N.B. 6xx (not 601) have valid */
95        mtspr   DBAT0U,r11              /* bit in upper BAT register */
96        mtspr   IBAT0L,r8
97        mtspr   IBAT0U,r11
98        isync
99/*
100 * <skf> Use the 2nd pair of BAT registers to map the 2nd 256MB
101 * of RAM to 0x10000000.
102 */
103        lis     r11,MEM256MB@h
104        ori     r11,r11,0x1ffe          /* set up BAT1 registers for 604+ */
105        lis     r8,MEM256MB@h
106        ori     r8,r8,2
107        isync
108        mtspr   DBAT1L,r8               /* N.B. 6xx (not 601) have valid */
109        mtspr   DBAT1U,r11              /* bit in upper BAT register */
110        mtspr   IBAT1L,r8
111        mtspr   IBAT1U,r11
112        isync
113
114/*
115 * we now have the two 256M of ram mapped with the bats. We are still
116 * running on the bootloader stack and cannot switch to an RTEMS allocated
117 * init stack before copying the residual data that may have been set just
118 * after rtems_end address. This bug has been experienced on MVME2304. Thank
119 * to Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and
120 * suggesting the appropriate code.
121 */
122
123enter_C_code:
124        bl      MMUon
125        bl      __eabi  /* setup EABI and SYSV environment */
126        bl      zero_bss
127        /*
128         * restore prep boot params
129         */
130        mr      r3,r31
131        mr      r4,r30
132        mr      r5,r29
133        mr      r6,r28
134        mr      r7,r27
135        bl      save_boot_params
136
137        /*
138         * Initialize start stack.  The stacks are statically allocated and
139         * properly aligned.
140         */
141        LA      r1, _ISR_Stack_area_end
142        subi    r1, r1, PPC_DEFAULT_CACHE_LINE_SIZE
143        li      r0, 0
144        stw     r0, 0(r1)
145
146        /*
147         * We are now in a environment that is totally independent from
148         * bootloader setup.
149         */
150    /* pass result of 'save_boot_params' to 'boot_card' in R3 */
151        bl      boot_card
152        bl      _return_to_ppcbug
153
154        .globl  MMUon
155        .type   MMUon,@function
156MMUon:
157        mfmsr   r0
158        ori     r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
159#if (PPC_HAS_FPU == 0)
160        xori    r0, r0, MSR_EE | MSR_IP | MSR_FP
161#else
162        xori    r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1
163#endif
164        mflr    r11
165        mtsrr0  r11
166        mtsrr1  r0
167        SYNC
168        rfi
169
170        .globl  MMUoff
171        .type   MMUoff,@function
172MMUoff:
173        mfmsr   r0
174        ori     r0,r0,MSR_IR| MSR_DR | MSR_IP
175        mflr    r11
176        xori    r0,r0,MSR_IR|MSR_DR
177        mtsrr0  r11
178        mtsrr1  r0
179        SYNC
180        rfi
181
182        .globl  _return_to_ppcbug
183        .type   _return_to_ppcbug,@function
184
185_return_to_ppcbug:
186        mflr    r30
187        bl      MMUoff
188        MONITOR_ENTER
189        bl      MMUon
190        mtctr   r30
191        bctr
192
193flush_tlbs:
194        lis     r20, 0x1000
1951:      addic.  r20, r20, -0x1000
196        tlbie   r20
197        bgt     1b
198        sync
199        blr
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