[7be6ad9] | 1 | /* |
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| 2 | * start.S : RTEMS entry point |
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| 3 | * |
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| 4 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 5 | * |
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| 6 | * S. Kate Feng <feng1@bnl.gov>, April 2004 |
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[169480b] | 7 | * Mapped the 2nd 256MB of RAM to support the MVME5500/MVME6100 boards |
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| 8 | * |
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[7be6ad9] | 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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[c499856] | 11 | * http://www.rtems.org/license/LICENSE. |
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[7be6ad9] | 12 | * |
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| 13 | */ |
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| 14 | |
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[1768b06] | 15 | #include <rtems/asm.h> |
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[7be6ad9] | 16 | #include <rtems/score/cpu.h> |
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[2195ccf3] | 17 | #include <rtems/powerpc/powerpc.h> |
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[169480b] | 18 | |
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[7be6ad9] | 19 | #include <libcpu/io.h> |
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[ec58ea04] | 20 | #include <libcpu/bat.h> |
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[169480b] | 21 | #include <bspopts.h> |
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[7be6ad9] | 22 | |
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| 23 | #define SYNC \ |
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| 24 | sync; \ |
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| 25 | isync |
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| 26 | |
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| 27 | #define KERNELBASE 0x0 |
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| 28 | #define MEM256MB 0x10000000 |
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[ac7af4a] | 29 | |
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[7be6ad9] | 30 | #define MONITOR_ENTER \ |
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| 31 | mfmsr r10 ; \ |
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| 32 | ori r10,r10,MSR_IP ; \ |
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| 33 | mtmsr r10 ; \ |
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| 34 | li r10,0x63 ; \ |
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| 35 | sc |
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| 36 | |
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| 37 | .text |
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| 38 | .globl __rtems_entry_point |
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| 39 | .type __rtems_entry_point,@function |
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| 40 | __rtems_entry_point: |
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| 41 | #ifdef DEBUG_EARLY_START |
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| 42 | MONITOR_ENTER |
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[ac7af4a] | 43 | #endif |
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| 44 | |
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| 45 | /* |
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[7be6ad9] | 46 | * PREP |
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| 47 | * This is jumped to on prep systems right after the kernel is relocated |
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| 48 | * to its proper place in memory by the boot loader. The expected layout |
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[ac7af4a] | 49 | * of the regs is: |
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[7be6ad9] | 50 | * r3: ptr to residual data |
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| 51 | * r4: initrd_start or if no initrd then 0 |
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| 52 | * r5: initrd_end - unused if r4 is 0 |
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| 53 | * r6: Start of command line string |
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| 54 | * r7: End of command line string |
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| 55 | * |
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| 56 | * The Prep boot loader insure that the MMU is currently off... |
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| 57 | * |
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| 58 | */ |
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[ac7af4a] | 59 | |
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[7be6ad9] | 60 | mr r31,r3 /* save parameters */ |
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| 61 | mr r30,r4 |
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| 62 | mr r29,r5 |
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| 63 | mr r28,r6 |
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| 64 | mr r27,r7 |
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[169480b] | 65 | |
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| 66 | #ifdef __ALTIVEC__ |
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| 67 | /* enable altivec; gcc may use it! */ |
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| 68 | mfmsr r0 |
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| 69 | oris r0, r0, (1<<(31-16-6)) |
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| 70 | mtmsr r0 |
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[814bd6e3] | 71 | isync |
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[169480b] | 72 | /* |
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| 73 | * set vscr and vrsave to known values |
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| 74 | */ |
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| 75 | li r0, 0 |
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| 76 | mtvrsave r0 |
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| 77 | vxor 0,0,0 |
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| 78 | mtvscr 0 |
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| 79 | #endif |
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| 80 | |
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[7be6ad9] | 81 | /* |
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| 82 | * Make sure we have nothing in BATS and TLB |
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| 83 | */ |
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[ec58ea04] | 84 | bl CPU_clear_bats_early |
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[7be6ad9] | 85 | bl flush_tlbs |
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| 86 | /* |
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| 87 | * Use the first pair of BAT registers to map the 1st 256MB |
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[ac7af4a] | 88 | * of RAM to KERNELBASE. |
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[7be6ad9] | 89 | */ |
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| 90 | lis r11,KERNELBASE@h |
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[169480b] | 91 | /* set up BAT registers for 604 */ |
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| 92 | ori r11,r11,0x1ffe |
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[7be6ad9] | 93 | li r8,2 /* R/W access */ |
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| 94 | isync |
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| 95 | mtspr DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ |
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| 96 | mtspr DBAT0U,r11 /* bit in upper BAT register */ |
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| 97 | mtspr IBAT0L,r8 |
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| 98 | mtspr IBAT0U,r11 |
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| 99 | isync |
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| 100 | /* |
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[169480b] | 101 | * <skf> Use the 2nd pair of BAT registers to map the 2nd 256MB |
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| 102 | * of RAM to 0x10000000. |
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[7be6ad9] | 103 | */ |
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| 104 | lis r11,MEM256MB@h |
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| 105 | ori r11,r11,0x1ffe /* set up BAT1 registers for 604+ */ |
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| 106 | lis r8,MEM256MB@h |
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| 107 | ori r8,r8,2 |
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| 108 | isync |
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| 109 | mtspr DBAT1L,r8 /* N.B. 6xx (not 601) have valid */ |
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| 110 | mtspr DBAT1U,r11 /* bit in upper BAT register */ |
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| 111 | mtspr IBAT1L,r8 |
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[ac7af4a] | 112 | mtspr IBAT1U,r11 |
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[7be6ad9] | 113 | isync |
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| 114 | |
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| 115 | /* |
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[ac7af4a] | 116 | * we now have the two 256M of ram mapped with the bats. We are still |
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| 117 | * running on the bootloader stack and cannot switch to an RTEMS allocated |
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[7be6ad9] | 118 | * init stack before copying the residual data that may have been set just |
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| 119 | * after rtems_end address. This bug has been experienced on MVME2304. Thank |
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| 120 | * to Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and |
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| 121 | * suggesting the appropriate code. |
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| 122 | */ |
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[ac7af4a] | 123 | |
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[7be6ad9] | 124 | enter_C_code: |
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| 125 | bl MMUon |
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[169480b] | 126 | bl __eabi /* setup EABI and SYSV environment */ |
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[7be6ad9] | 127 | bl zero_bss |
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| 128 | /* |
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| 129 | * restore prep boot params |
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| 130 | */ |
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| 131 | mr r3,r31 |
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| 132 | mr r4,r30 |
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| 133 | mr r5,r29 |
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| 134 | mr r6,r28 |
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[ac7af4a] | 135 | mr r7,r27 |
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[7be6ad9] | 136 | bl save_boot_params |
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| 137 | /* |
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| 138 | * stack = &__rtems_end + 4096 |
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| 139 | */ |
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[72510eb2] | 140 | addis r9,r0, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@ha |
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[169480b] | 141 | addi r9,r9, __stack-PPC_MINIMUM_STACK_FRAME_SIZE@l |
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[7be6ad9] | 142 | /* |
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[169480b] | 143 | * align initial stack |
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| 144 | * (we hope that the bootloader stack was 16-byte aligned |
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| 145 | * or we haven't used altivec yet...) |
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| 146 | */ |
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| 147 | li r0, (CPU_STACK_ALIGNMENT-1) |
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| 148 | andc r1, r9, r0 |
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[6963b2e7] | 149 | /* |
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| 150 | * NULL ptr to back chain |
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| 151 | */ |
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| 152 | li r0, 0 |
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| 153 | stw r0, 0(r1) |
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| 154 | |
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[169480b] | 155 | /* |
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| 156 | * We are now in a environment that is totally independent from |
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| 157 | * bootloader setup. |
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[7be6ad9] | 158 | */ |
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[5eccbac] | 159 | /* pass result of 'save_boot_params' to 'boot_card' in R3 */ |
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[7be6ad9] | 160 | bl boot_card |
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| 161 | bl _return_to_ppcbug |
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[ac7af4a] | 162 | |
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[7be6ad9] | 163 | .globl MMUon |
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| 164 | .type MMUon,@function |
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[ac7af4a] | 165 | MMUon: |
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[7be6ad9] | 166 | mfmsr r0 |
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| 167 | ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP |
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[72510eb2] | 168 | #if (PPC_HAS_FPU == 0) |
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[7be6ad9] | 169 | xori r0, r0, MSR_EE | MSR_IP | MSR_FP |
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| 170 | #else |
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| 171 | xori r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1 |
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| 172 | #endif |
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| 173 | mflr r11 |
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| 174 | mtsrr0 r11 |
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| 175 | mtsrr1 r0 |
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| 176 | SYNC |
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| 177 | rfi |
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[ac7af4a] | 178 | |
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[7be6ad9] | 179 | .globl MMUoff |
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| 180 | .type MMUoff,@function |
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[ac7af4a] | 181 | MMUoff: |
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[7be6ad9] | 182 | mfmsr r0 |
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| 183 | ori r0,r0,MSR_IR| MSR_DR | MSR_IP |
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| 184 | mflr r11 |
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| 185 | xori r0,r0,MSR_IR|MSR_DR |
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| 186 | mtsrr0 r11 |
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| 187 | mtsrr1 r0 |
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| 188 | SYNC |
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| 189 | rfi |
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| 190 | |
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| 191 | .globl _return_to_ppcbug |
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| 192 | .type _return_to_ppcbug,@function |
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| 193 | |
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| 194 | _return_to_ppcbug: |
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| 195 | mflr r30 |
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| 196 | bl MMUoff |
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| 197 | MONITOR_ENTER |
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| 198 | bl MMUon |
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| 199 | mtctr r30 |
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[ac7af4a] | 200 | bctr |
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[7be6ad9] | 201 | |
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| 202 | flush_tlbs: |
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| 203 | lis r20, 0x1000 |
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| 204 | 1: addic. r20, r20, -0x1000 |
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| 205 | tlbie r20 |
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| 206 | bgt 1b |
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| 207 | sync |
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| 208 | blr |
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