1 | /* irq.h |
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2 | * |
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3 | * This include file describe the data structure and the functions implemented |
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4 | * by rtems to write interrupt handlers. |
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5 | * |
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6 | * CopyRight (C) 1999 valette@crf.canon.fr |
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7 | * |
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8 | * This code is heavilly inspired by the public specification of STREAM V2 |
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9 | * that can be found at : |
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10 | * |
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11 | * <http://www.chorus.com/Documentation/index.html> by following |
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12 | * the STREAM API Specification Document link. |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | * |
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18 | * Copyright 2004, 2005 Brookhaven National Laboratory and |
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19 | * Shuchen Kate Feng <feng1@bnl.gov> |
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20 | * |
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21 | * - modified shared/irq/irq.h for Mvme5500 (no ISA devices/PIC) |
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22 | * - Discovery GT64260 interrupt controller instead of 8259. |
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23 | * - Added support for software IRQ priority levels. |
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24 | * - modified to optimize the IRQ latency and handling |
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25 | */ |
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26 | |
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27 | #ifndef LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H |
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28 | #define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H |
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29 | |
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30 | #define BSP_SHARED_HANDLER_SUPPORT 1 |
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31 | #include <rtems/irq.h> |
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32 | |
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33 | #ifndef ASM |
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34 | |
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35 | #define OneTierIrqPrioTbl 1 |
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36 | |
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37 | /* |
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38 | * Symbolic IRQ names and related definitions. |
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39 | */ |
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40 | |
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41 | /* leave the ISA symbols in there, so we can reuse shared/irq.c |
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42 | * Also, we start numbering PCI irqs at 16 because the OPENPIC |
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43 | * driver relies on this when mapping irq number <-> vectors |
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44 | * (OPENPIC_VEC_SOURCE in openpic.h) |
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45 | */ |
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46 | |
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47 | /* See section 25.2 , Table 734 of GT64260 controller |
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48 | * Main Interrupt Cause Low register |
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49 | */ |
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50 | #define BSP_MICL_IRQ_NUMBER (32) |
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51 | #define BSP_MICL_IRQ_LOWEST_OFFSET (0) |
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52 | #define BSP_MICL_IRQ_MAX_OFFSET (BSP_MICL_IRQ_LOWEST_OFFSET + BSP_MICL_IRQ_NUMBER -1) |
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53 | /* |
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54 | * Main Interrupt Cause High register |
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55 | */ |
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56 | #define BSP_MICH_IRQ_NUMBER (32) |
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57 | #define BSP_MICH_IRQ_LOWEST_OFFSET (BSP_MICL_IRQ_MAX_OFFSET+1) |
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58 | #define BSP_MICH_IRQ_MAX_OFFSET (BSP_MICH_IRQ_LOWEST_OFFSET + BSP_MICH_IRQ_NUMBER -1) |
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59 | /* External GPP Interrupt assignements |
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60 | */ |
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61 | #define BSP_GPP_IRQ_NUMBER (32) |
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62 | #define BSP_GPP_IRQ_LOWEST_OFFSET (BSP_MICH_IRQ_MAX_OFFSET+1) |
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63 | #define BSP_GPP_IRQ_MAX_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET + BSP_GPP_IRQ_NUMBER - 1) |
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64 | |
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65 | /* |
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66 | * PowerPc exceptions handled as interrupt where a rtems managed interrupt |
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67 | * handler might be connected |
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68 | */ |
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69 | #define BSP_PROCESSOR_IRQ_NUMBER (1) |
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70 | #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_MAX_OFFSET + 1) |
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71 | #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) |
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72 | |
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73 | /* allow a couple of vectors for VME and counter/timer irq sources etc. |
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74 | * This is probably not needed any more. |
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75 | */ |
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76 | #define BSP_MISC_IRQ_NUMBER (30) |
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77 | #define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) |
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78 | #define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) |
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79 | |
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80 | /* |
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81 | * Summary |
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82 | */ |
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83 | #define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) |
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84 | #define BSP_MAIN_IRQ_NUMBER (64) |
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85 | #define BSP_PIC_IRQ_NUMBER (96) |
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86 | #define BSP_LOWEST_OFFSET (BSP_MICL_IRQ_LOWEST_OFFSET) |
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87 | #define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) |
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88 | |
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89 | /* Main CPU interrupt cause (Low) */ |
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90 | #define BSP_MAIN_TIMER0_1_IRQ (BSP_MICL_IRQ_LOWEST_OFFSET+8) |
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91 | #define BSP_MAIN_PCI0_7_0 (BSP_MICL_IRQ_LOWEST_OFFSET+12) |
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92 | #define BSP_MAIN_PCI0_15_8 (BSP_MICL_IRQ_LOWEST_OFFSET+13) |
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93 | #define BSP_MAIN_PCI0_23_16 (BSP_MICL_IRQ_LOWEST_OFFSET+14) |
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94 | #define BSP_MAIN_PCI0_31_24 (BSP_MICL_IRQ_LOWEST_OFFSET+15) |
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95 | #define BSP_MAIN_PCI1_7_0 (BSP_MICL_IRQ_LOWEST_OFFSET+16) |
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96 | #define BSP_MAIN_PCI1_15_8 (BSP_MICL_IRQ_LOWEST_OFFSET+18) |
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97 | #define BSP_MAIN_PCI1_23_16 (BSP_MICL_IRQ_LOWEST_OFFSET+19) |
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98 | #define BSP_MAIN_PCI1_31_24 (BSP_MICL_IRQ_LOWEST_OFFSET+20) |
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99 | |
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100 | |
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101 | /* Main CPU interrupt cause (High) */ |
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102 | #define BSP_MAIN_ETH0_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET) |
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103 | #define BSP_MAIN_ETH1_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+1) |
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104 | #define BSP_MAIN_ETH2_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+2) |
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105 | #define BSP_MAIN_GPP7_0_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+24) |
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106 | #define BSP_MAIN_GPP15_8_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+25) |
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107 | #define BSP_MAIN_GPP23_16_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+26) |
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108 | #define BSP_MAIN_GPP31_24_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+27) |
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109 | |
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110 | /* on the MVME5500, these are the GT64260B external GPP0 interrupt */ |
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111 | #define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET) |
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112 | #define BSP_UART_COM2_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET) |
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113 | #define BSP_UART_COM1_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET) |
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114 | #define BSP_GPP8_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+8) |
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115 | #define BSP_GPP_PMC1_INTA (BSP_GPP8_IRQ_OFFSET) |
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116 | #define BSP_GPP16_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+16) |
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117 | #define BSP_GPP24_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+24) |
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118 | #define BSP_GPP_VME_VLINT0 (BSP_GPP_IRQ_LOWEST_OFFSET+12) |
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119 | #define BSP_GPP_VME_VLINT1 (BSP_GPP_IRQ_LOWEST_OFFSET+13) |
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120 | #define BSP_GPP_VME_VLINT2 (BSP_GPP_IRQ_LOWEST_OFFSET+14) |
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121 | #define BSP_GPP_VME_VLINT3 (BSP_GPP_IRQ_LOWEST_OFFSET+15) |
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122 | #define BSP_GPP_PMC2_INTA (BSP_GPP_IRQ_LOWEST_OFFSET+16) |
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123 | #define BSP_GPP_82544_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+20) |
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124 | #define BSP_GPP_WDT_NMI_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+24) |
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125 | #define BSP_GPP_WDT_EXP_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+25) |
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126 | |
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127 | /* |
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128 | * Some Processor execption handled as rtems IRQ symbolic name definition |
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129 | */ |
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130 | #define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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131 | |
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132 | extern void BSP_rtems_irq_mng_init(unsigned cpuId); |
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133 | |
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134 | #include <bsp/irq_supp.h> |
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135 | |
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136 | #endif |
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137 | #endif |
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