source: rtems/bsps/powerpc/mvme5500/include/bsp/if_wmreg.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 29.3 KB
Line 
1/*      $NetBSD: if_wmreg.h,v 1.22 2007/04/29 20:35:21 bouyer Exp $     */
2
3/*
4 * Copyright (c) 2001 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 * Some are added by Shuchen Kate Feng <feng1@bnl.gov>,
9 *            NSLS, Brookhaven National Laboratory. All rights reserved.
10 *            under the Deaprtment of Energy contract DE-AC02-98CH10886
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 *    notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 *    notice, this list of conditions and the following disclaimer in the
19 *    documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 *    must display the following acknowledgement:
22 *      This product includes software developed for the NetBSD Project by
23 *      Wasabi Systems, Inc.
24 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
25 *    or promote products derived from this software without specific prior
26 *    written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41/*
42 * Register description for the Intel i82542 (``Wiseman''),
43 * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit
44 * Ethernet chips.
45 */
46
47/*
48 * The wiseman supports 64-bit PCI addressing.  This structure
49 * describes the address in descriptors.
50 */
51typedef struct wiseman_addr {
52        uint32_t        wa_low;         /* low-order 32 bits */
53        uint32_t        wa_high;        /* high-order 32 bits */
54} __attribute__((__packed__)) wiseman_addr_t;
55
56/*
57 * The Wiseman receive descriptor.
58 *
59 * The receive descriptor ring must be aligned to a 4K boundary,
60 * and there must be an even multiple of 8 descriptors in the ring.
61 */
62typedef volatile struct wiseman_rxdesc {
63        wiseman_addr_t  wrx_addr;       /* buffer address */
64
65        uint16_t        wrx_len;        /* buffer length */
66        uint16_t        wrx_cksum;      /* checksum (starting at PCSS) */
67
68        uint8_t         wrx_status;     /* Rx status */
69        uint8_t         wrx_errors;     /* Rx errors */
70        uint16_t        wrx_special;    /* special field (VLAN, etc.) */
71} __attribute__((__packed__)) wiseman_rxdesc_t;
72
73/* wrx_status bits */
74#define WRX_ST_DD       (1U << 0)       /* descriptor done */
75#define WRX_ST_EOP      (1U << 1)       /* end of packet */
76#define WRX_ST_IXSM     (1U << 2)       /* ignore checksum indication */
77#define WRX_ST_VP       (1U << 3)       /* VLAN packet */
78#define WRX_ST_BPDU     (1U << 4)       /* ??? */
79#define WRX_ST_TCPCS    (1U << 5)       /* TCP checksum performed */
80#define WRX_ST_IPCS     (1U << 6)       /* IP checksum performed */
81#define WRX_ST_PIF      (1U << 7)       /* passed in-exact filter */
82
83/* wrx_error bits */
84#define WRX_ER_CE       (1U << 0)       /* CRC error */
85#define WRX_ER_SE       (1U << 1)       /* symbol error */
86#define WRX_ER_SEQ      (1U << 2)       /* sequence error */
87#define WRX_ER_ICE      (1U << 3)       /* ??? */
88#define WRX_ER_CXE      (1U << 4)       /* carrier extension error */
89#define WRX_ER_TCPE     (1U << 5)       /* TCP checksum error */
90#define WRX_ER_IPE      (1U << 6)       /* IP checksum error */
91#define WRX_ER_RXE      (1U << 7)       /* Rx data error */
92
93/* wrx_special field for VLAN packets */
94#define WRX_VLAN_ID(x)  ((x) & 0x0fff)  /* VLAN identifier */
95#define WRX_VLAN_CFI    (1U << 12)      /* Canonical Form Indicator */
96#define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */
97
98/*
99 * The Wiseman transmit descriptor.
100 *
101 * The transmit descriptor ring must be aligned to a 4K boundary,
102 * and there must be an even multiple of 8 descriptors in the ring.
103 */
104typedef struct wiseman_tx_fields {
105        uint8_t wtxu_status;            /* Tx status */
106        uint8_t wtxu_options;           /* options */
107        uint16_t wtxu_vlan;             /* VLAN info */
108} __attribute__((__packed__)) wiseman_txfields_t;
109typedef volatile struct wiseman_txdesc {
110        wiseman_addr_t  wtx_addr;       /* buffer address */
111        uint32_t        wtx_cmdlen;     /* command and length */
112        wiseman_txfields_t wtx_fields;  /* fields; see below */
113} __attribute__((__packed__)) wiseman_txdesc_t;
114
115/* Commands for wtx_cmdlen */
116#define WTX_CMD_EOP     (1U << 24)      /* end of packet */
117#define WTX_CMD_IFCS    (1U << 25)      /* insert FCS */
118#define WTX_CMD_RS      (1U << 27)      /* report status */
119#define WTX_CMD_RPS     (1U << 28)      /* report packet sent */
120#define WTX_CMD_DEXT    (1U << 29)      /* descriptor extension */
121#define WTX_CMD_VLE     (1U << 30)      /* VLAN enable */
122#define WTX_CMD_IDE     (1U << 31)      /* interrupt delay enable */
123
124/* Descriptor types (if DEXT is set) */
125#define WTX_DTYP_C      (0U << 20)      /* context */
126#define WTX_DTYP_D      (1U << 20)      /* data */
127
128/* wtx_fields status bits */
129#define WTX_ST_DD       (1U << 0)       /* descriptor done */
130#define WTX_ST_EC       (1U << 1)       /* excessive collisions */
131#define WTX_ST_LC       (1U << 2)       /* late collision */
132#define WTX_ST_TU       (1U << 3)       /* transmit underrun */
133
134/* wtx_fields option bits for IP/TCP/UDP checksum offload */
135#define WTX_IXSM        (1U << 0)       /* IP checksum offload */
136#define WTX_TXSM        (1U << 1)       /* TCP/UDP checksum offload */
137
138/* Maximum payload per Tx descriptor */
139#define WTX_MAX_LEN     4096
140
141/*
142 * The Livengood TCP/IP context descriptor.
143 */
144struct livengood_tcpip_ctxdesc {
145        uint32_t        tcpip_ipcs;     /* IP checksum context */
146        uint32_t        tcpip_tucs;     /* TCP/UDP checksum context */
147        uint32_t        tcpip_cmdlen;
148        uint32_t        tcpip_seg;      /* TCP segmentation context */
149};
150
151/* commands for context descriptors */
152#define WTX_TCPIP_CMD_TCP       (1U << 24)      /* 1 = TCP, 0 = UDP */
153#define WTX_TCPIP_CMD_IP        (1U << 25)      /* 1 = IPv4, 0 = IPv6 */
154#define WTX_TCPIP_CMD_TSE       (1U << 26)      /* segmentation context valid */
155
156#define WTX_TCPIP_IPCSS(x)      ((x) << 0)      /* checksum start */
157#define WTX_TCPIP_IPCSO(x)      ((x) << 8)      /* checksum value offset */
158#define WTX_TCPIP_IPCSE(x)      ((x) << 16)     /* checksum end */
159
160#define WTX_TCPIP_TUCSS(x)      ((x) << 0)      /* checksum start */
161#define WTX_TCPIP_TUCSO(x)      ((x) << 8)      /* checksum value offset */
162#define WTX_TCPIP_TUCSE(x)      ((x) << 16)     /* checksum end */
163
164#define WTX_TCPIP_SEG_STATUS(x) ((x) << 0)
165#define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8)
166#define WTX_TCPIP_SEG_MSS(x)    ((x) << 16)
167
168/*
169 * PCI config registers used by the Wiseman.
170 */
171#define WM_PCI_MMBA     PCI_MAPREG_START
172/* registers for FLASH access on ICH8 */
173#define WM_ICH8_FLASH   0x0014
174
175/*
176 * Wiseman Control/Status Registers.
177 */
178#define WMREG_CTRL      0x0000  /* Device Control Register */
179#define CTRL_FD         (1U << 0)       /* full duplex */
180#define CTRL_BEM        (1U << 1)       /* big-endian mode */
181#define CTRL_PRIOR      (1U << 2)       /* 0 = receive, 1 = fair */
182#define CTRL_LRST       (1U << 3)       /* link reset */
183#define CTRL_ASDE       (1U << 5)       /* auto speed detect enable */
184#define CTRL_SLU        (1U << 6)       /* set link up */
185#define CTRL_ILOS       (1U << 7)       /* invert loss of signal */
186#define CTRL_SPEED(x)   ((x) << 8)      /* speed (Livengood) */
187#define CTRL_SPEED_10   CTRL_SPEED(0)
188#define CTRL_SPEED_100  CTRL_SPEED(1)
189#define CTRL_SPEED_1000 CTRL_SPEED(2)
190#define CTRL_SPEED_MASK CTRL_SPEED(3)
191#define CTRL_FRCSPD     (1U << 11)      /* force speed (Livengood) */
192#define CTRL_FRCFDX     (1U << 12)      /* force full-duplex (Livengood) */
193#define CTRL_D_UD_EN    (1U << 13)      /* Dock/Undock enable */
194#define CTRL_D_UD_POL   (1U << 14)      /* Defined polarity of Dock/Undock indication in SDP[0] */
195#define CTRL_F_PHY_R    (1U << 15)      /* Reset both PHY ports, through PHYRST_N pin */
196#define CTRL_EXT_LINK_EN (1U << 16)     /* enable link status from external LINK_0 and LINK_1 pins */
197#define CTRL_SWDPINS_SHIFT      18
198#define CTRL_SWDPINS_MASK       0x0f
199#define CTRL_SWDPIN(x)          (1U << (CTRL_SWDPINS_SHIFT + (x)))
200#define CTRL_SWDPIO_SHIFT       22
201#define CTRL_SWDPIO_MASK        0x0f
202#define CTRL_SWDPIO(x)          (1U << (CTRL_SWDPIO_SHIFT + (x)))
203#define CTRL_RST        (1U << 26)      /* device reset */
204#define CTRL_RFCE       (1U << 27)      /* Rx flow control enable */
205#define CTRL_TFCE       (1U << 28)      /* Tx flow control enable */
206#define CTRL_VME        (1U << 30)      /* VLAN Mode Enable */
207#define CTRL_PHY_RESET  (1U << 31)      /* PHY reset (Cordova) */
208
209#define WMREG_CTRL_SHADOW 0x0004        /* Device Control Register (shadow) */
210
211#define WMREG_STATUS    0x0008  /* Device Status Register */
212#define STATUS_FD       (1U << 0)       /* full duplex */
213#define STATUS_LU       (1U << 1)       /* link up */
214#define STATUS_TCKOK    (1U << 2)       /* Tx clock running */
215#define STATUS_RBCOK    (1U << 3)       /* Rx clock running */
216#define STATUS_FUNCID_SHIFT 2           /* 82546 function ID */
217#define STATUS_FUNCID_MASK  3           /* ... */
218#define STATUS_TXOFF    (1U << 4)       /* Tx paused */
219#define STATUS_TBIMODE  (1U << 5)       /* fiber mode (Livengood) */
220#define STATUS_SPEED(x) ((x) << 6)      /* speed indication */
221#define STATUS_SPEED_10   STATUS_SPEED(0)
222#define STATUS_SPEED_100  STATUS_SPEED(1)
223#define STATUS_SPEED_1000 STATUS_SPEED(2)
224#define STATUS_ASDV(x)  ((x) << 8)      /* auto speed det. val. (Livengood) */
225#define STATUS_MTXCKOK  (1U << 10)      /* MTXD clock running */
226#define STATUS_PCI66    (1U << 11)      /* 66MHz bus (Livengood) */
227#define STATUS_BUS64    (1U << 12)      /* 64-bit bus (Livengood) */
228#define STATUS_PCIX_MODE (1U << 13)     /* PCIX mode (Cordova) */
229#define STATUS_PCIXSPD(x) ((x) << 14)   /* PCIX speed indication (Cordova) */
230#define STATUS_PCIXSPD_50_66   STATUS_PCIXSPD(0)
231#define STATUS_PCIXSPD_66_100  STATUS_PCIXSPD(1)
232#define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2)
233#define STATUS_PCIXSPD_MASK    STATUS_PCIXSPD(3)
234
235#define WMREG_EECD      0x0010  /* EEPROM Control Register */
236#define EECD_SK         (1U << 0)       /* clock */
237#define EECD_CS         (1U << 1)       /* chip select */
238#define EECD_DI         (1U << 2)       /* data in */
239#define EECD_DO         (1U << 3)       /* data out */
240#define EECD_FWE(x)     ((x) << 4)      /* flash write enable control */
241#define EECD_FWE_DISABLED EECD_FWE(1)
242#define EECD_FWE_ENABLED  EECD_FWE(2)
243#define EECD_EE_REQ     (1U << 6)       /* (shared) EEPROM request */
244#define EECD_EE_GNT     (1U << 7)       /* (shared) EEPROM grant */
245#define EECD_EE_PRES    (1U << 8)       /* EEPROM present */
246#define EECD_EE_SIZE    (1U << 9)       /* EEPROM size
247                                           (0 = 64 word, 1 = 256 word) */
248#define EECD_EE_AUTORD  (1U << 9)       /* auto read done */
249#define EECD_EE_ABITS   (1U << 10)      /* EEPROM address bits
250                                           (based on type) */
251#define EECD_EE_TYPE    (1U << 13)      /* EEPROM type
252                                           (0 = Microwire, 1 = SPI) */
253#define EECD_SEC1VAL    (1U << 22)      /* Sector One Valid */
254
255#define UWIRE_OPC_ERASE 0x04            /* MicroWire "erase" opcode */
256#define UWIRE_OPC_WRITE 0x05            /* MicroWire "write" opcode */
257#define UWIRE_OPC_READ  0x06            /* MicroWire "read" opcode */
258
259#define SPI_OPC_WRITE   0x02            /* SPI "write" opcode */
260#define SPI_OPC_READ    0x03            /* SPI "read" opcode */
261#define SPI_OPC_A8      0x08            /* opcode bit 3 == address bit 8 */
262#define SPI_OPC_WREN    0x06            /* SPI "set write enable" opcode */
263#define SPI_OPC_WRDI    0x04            /* SPI "clear write enable" opcode */
264#define SPI_OPC_RDSR    0x05            /* SPI "read status" opcode */
265#define SPI_OPC_WRSR    0x01            /* SPI "write status" opcode */
266#define SPI_MAX_RETRIES 5000            /* max wait of 5ms for RDY signal */
267
268#define SPI_SR_RDY      0x01
269#define SPI_SR_WEN      0x02
270#define SPI_SR_BP0      0x04
271#define SPI_SR_BP1      0x08
272#define SPI_SR_WPEN     0x80
273
274#define EEPROM_OFF_MACADDR      0x00    /* MAC address offset */
275#define EEPROM_OFF_CFG1         0x0a    /* config word 1 */
276#define EEPROM_OFF_CFG2         0x0f    /* config word 2 */
277#define EEPROM_OFF_SWDPIN       0x20    /* SWD Pins (Cordova) */
278
279#define EEPROM_CFG1_LVDID       (1U << 0)
280#define EEPROM_CFG1_LSSID       (1U << 1)
281#define EEPROM_CFG1_PME_CLOCK   (1U << 2)
282#define EEPROM_CFG1_PM          (1U << 3)
283#define EEPROM_CFG1_ILOS        (1U << 4)
284#define EEPROM_CFG1_SWDPIO_SHIFT 5
285#define EEPROM_CFG1_SWDPIO_MASK (0xf << EEPROM_CFG1_SWDPIO_SHIFT)
286#define EEPROM_CFG1_IPS1        (1U << 8)
287#define EEPROM_CFG1_LRST        (1U << 9)
288#define EEPROM_CFG1_FD          (1U << 10)
289#define EEPROM_CFG1_FRCSPD      (1U << 11)
290#define EEPROM_CFG1_IPS0        (1U << 12)
291#define EEPROM_CFG1_64_32_BAR   (1U << 13)
292
293#define EEPROM_CFG2_CSR_RD_SPLIT (1U << 1)
294#define EEPROM_CFG2_APM_EN      (1U << 2)
295#define EEPROM_CFG2_64_BIT      (1U << 3)
296#define EEPROM_CFG2_MAX_READ    (1U << 4)
297#define EEPROM_CFG2_DMCR_MAP    (1U << 5)
298#define EEPROM_CFG2_133_CAP     (1U << 6)
299#define EEPROM_CFG2_MSI_DIS     (1U << 7)
300#define EEPROM_CFG2_FLASH_DIS   (1U << 8)
301#define EEPROM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9)
302#define EEPROM_CFG2_ANE         (1U << 11)
303#define EEPROM_CFG2_PAUSE(x)    (((x) & 3) >> 12)
304#define EEPROM_CFG2_ASDE        (1U << 14)
305#define EEPROM_CFG2_APM_PME     (1U << 15)
306#define EEPROM_CFG2_SWDPIO_SHIFT 4
307#define EEPROM_CFG2_SWDPIO_MASK (0xf << EEPROM_CFG2_SWDPIO_SHIFT)
308
309#define EEPROM_SWDPIN_MASK      0xdf
310#define EEPROM_SWDPIN_SWDPIN_SHIFT 0
311#define EEPROM_SWDPIN_SWDPIO_SHIFT 8
312
313#define WMREG_EERD      0x0014  /* EEPROM read */
314#define EERD_DONE       0x02    /* done bit */
315#define EERD_START      0x01    /* First bit for telling part to start operation */
316#define EERD_ADDR_SHIFT 2       /* Shift to the address bits */
317#define EERD_DATA_SHIFT 16      /* Offset to data in EEPROM read/write registers */
318
319#define WMREG_CTRL_EXT  0x0018  /* Extended Device Control Register */
320#define CTRL_EXT_GPI_EN(x)      (1U << (x)) /* gpin interrupt enable */
321#define CTRL_EXT_SWDPINS_SHIFT  4
322#define CTRL_EXT_SWDPINS_MASK   0x0d
323#define CTRL_EXT_SWDPIN(x)      (1U << (CTRL_EXT_SWDPINS_SHIFT + (x) - 4))
324#define CTRL_EXT_SWDPIO_SHIFT   8
325#define CTRL_EXT_SWDPIO_MASK    0x0d
326#define CTRL_EXT_SWDPIO(x)      (1U << (CTRL_EXT_SWDPIO_SHIFT + (x) - 4))
327#define CTRL_EXT_ASDCHK         (1U << 12) /* ASD check */
328#define CTRL_EXT_EE_RST         (1U << 13) /* EEPROM reset */
329#define CTRL_EXT_IPS            (1U << 14) /* invert power state bit 0 */
330#define CTRL_EXT_SPD_BYPS       (1U << 15) /* speed select bypass */
331#define CTRL_EXT_IPS1           (1U << 16) /* invert power state bit 1 */
332#define CTRL_EXT_RO_DIS         (1U << 17) /* relaxed ordering disabled */
333#define CTRL_EXT_LINK_MODE_MASK 0x00C00000
334#define CTRL_EXT_LINK_MODE_GMII 0x00000000
335#define CTRL_EXT_LINK_MODE_TBI  0x00C00000
336#define CTRL_EXT_LINK_MODE_KMRN 0x00000000
337#define CTRL_EXT_LINK_MODE_SERDES 0x00C00000
338
339
340#define WMREG_MDIC      0x0020  /* MDI Control Register */
341#define MDIC_DATA(x)    ((x) & 0xffff)
342#define MDIC_REGADD(x)  ((x) << 16)
343#define MDIC_PHYADD(x)  ((x) << 21)
344#define MDIC_OP_WRITE   (1U << 26)
345#define MDIC_OP_READ    (2U << 26)
346#define MDIC_READY      (1U << 28)
347#define MDIC_I          (1U << 29)      /* interrupt on MDI complete */
348#define MDIC_E          (1U << 30)      /* MDI error */
349
350#define WMREG_FCAL      0x0028  /* Flow Control Address Low */
351#define FCAL_CONST      0x00c28001      /* Flow Control MAC addr low */
352
353#define WMREG_FCAH      0x002c  /* Flow Control Address High */
354#define FCAH_CONST      0x00000100      /* Flow Control MAC addr high */
355
356#define WMREG_FCT       0x0030  /* Flow Control Type */
357
358#define WMREG_VET       0x0038  /* VLAN Ethertype */
359
360#define WMREG_RAL_BASE  0x0040  /* Receive Address List */
361#define WMREG_CORDOVA_RAL_BASE 0x5400
362#define WMREG_RAL_LO(b, x) ((b) + ((x) << 3))
363#define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4)
364        /*
365         * Receive Address List: The LO part is the low-order 32-bits
366         * of the MAC address.  The HI part is the high-order 16-bits
367         * along with a few control bits.
368         */
369#define RAL_AS(x)       ((x) << 16)     /* address select */
370#define RAL_AS_DEST     RAL_AS(0)       /* (cordova?) */
371#define RAL_AS_SOURCE   RAL_AS(1)       /* (cordova?) */
372#define RAL_RDR1        (1U << 30)      /* put packet in alt. rx ring */
373#define RAL_AV          (1U << 31)      /* entry is valid */
374
375#define WM_RAL_TABSIZE  16
376#define WM_ICH8_RAL_TABSIZE 7
377
378#define WMREG_ICR       0x00c0  /* Interrupt Cause Register */
379#define ICR_TXDW        (1U << 0)       /* Tx desc written back */
380#define ICR_TXQE        (1U << 1)       /* Tx queue empty */
381#define ICR_LSC         (1U << 2)       /* link status change */
382#define ICR_RXSEQ       (1U << 3)       /* receive sequence error */
383#define ICR_RXDMT0      (1U << 4)       /* Rx ring 0 nearly empty */
384#define ICR_RXO         (1U << 6)       /* Rx overrun */
385#define ICR_RXT0        (1U << 7)       /* Rx ring 0 timer */
386#define ICR_MDAC        (1U << 9)       /* MDIO access complete */
387#define ICR_RXCFG       (1U << 10)      /* Receiving /C/ */
388#define ICR_GPI(x)      (1U << (x))     /* general purpose interrupts */
389#define ICR_INT         (1U << 31)      /* device generated an interrupt */
390
391#define WMREG_ITR       0x00c4  /* Interrupt Throttling Register */
392#define ITR_IVAL_MASK   0xffff          /* Interval mask */
393#define ITR_IVAL_SHIFT  0               /* Interval shift */
394
395#define WMREG_ICS       0x00c8  /* Interrupt Cause Set Register */
396        /* See ICR bits. */
397
398#define WMREG_IMS       0x00d0  /* Interrupt Mask Set Register */
399        /* See ICR bits. */
400
401#define WMREG_IMC       0x00d8  /* Interrupt Mask Clear Register */
402        /* See ICR bits. */
403
404#define WMREG_RCTL      0x0100  /* Receive Control */
405#define RCTL_EN         (1U << 1)       /* receiver enable */
406#define RCTL_SBP        (1U << 2)       /* store bad packets */
407#define RCTL_UPE        (1U << 3)       /* unicast promisc. enable */
408#define RCTL_MPE        (1U << 4)       /* multicast promisc. enable */
409#define RCTL_LPE        (1U << 5)       /* large packet enable */
410#define RCTL_LBM(x)     ((x) << 6)      /* loopback mode */
411#define RCTL_LBM_NONE   RCTL_LBM(0)
412#define RCTL_LBM_PHY    RCTL_LBM(3)
413#define RCTL_RDMTS(x)   ((x) << 8)      /* receive desc. min thresh size */
414#define RCTL_RDMTS_1_2  RCTL_RDMTS(0)
415#define RCTL_RDMTS_1_4  RCTL_RDMTS(1)
416#define RCTL_RDMTS_1_8  RCTL_RDMTS(2)
417#define RCTL_RDMTS_MASK RCTL_RDMTS(3)
418#define RCTL_MO(x)      ((x) << 12)     /* multicast offset */
419#define RCTL_BAM        (1U << 15)      /* broadcast accept mode */
420#define RCTL_2k         (0 << 16)       /* 2k Rx buffers */
421#define RCTL_1k         (1 << 16)       /* 1k Rx buffers */
422#define RCTL_512        (2 << 16)       /* 512 byte Rx buffers */
423#define RCTL_256        (3 << 16)       /* 256 byte Rx buffers */
424#define RCTL_BSEX_16k   (1 << 16)       /* 16k Rx buffers (BSEX) */
425#define RCTL_BSEX_8k    (2 << 16)       /* 8k Rx buffers (BSEX) */
426#define RCTL_BSEX_4k    (3 << 16)       /* 4k Rx buffers (BSEX) */
427#define RCTL_DPF        (1U << 22)      /* discard pause frames */
428#define RCTL_PMCF       (1U << 23)      /* pass MAC control frames */
429#define RCTL_BSEX       (1U << 25)      /* buffer size extension (Livengood) */
430#define RCTL_SECRC      (1U << 26)      /* strip Ethernet CRC */
431
432#define WMREG_OLD_RDTR0 0x0108  /* Receive Delay Timer (ring 0) */
433#define WMREG_RDTR      0x2820
434#define RDTR_FPD        (1U << 31)      /* flush partial descriptor */
435
436#define WMREG_RADV      0x282c  /* Receive Interrupt Absolute Delay Timer */
437
438#define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */
439#define WMREG_RDBAL     0x2800
440
441#define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */
442#define WMREG_RDBAH     0x2804
443
444#define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */
445#define WMREG_RDLEN     0x2808
446
447#define WMREG_OLD_RDH0  0x0120  /* Receive Descriptor Head (ring 0) */
448#define WMREG_RDH       0x2810
449
450#define WMREG_OLD_RDT0  0x0128  /* Receive Descriptor Tail (ring 0) */
451#define WMREG_RDT       0x2818
452
453#define WMREG_RXDCTL    0x2828  /* Receive Descriptor Control */
454#define RXDCTL_PTHRESH(x) ((x) << 0)    /* prefetch threshold */
455#define RXDCTL_HTHRESH(x) ((x) << 8)    /* host threshold */
456#define RXDCTL_WTHRESH(x) ((x) << 16)   /* write back threshold */
457#define RXDCTL_GRAN     (1U << 24)      /* 0 = cacheline, 1 = descriptor */
458
459#define WMREG_OLD_RDTR1 0x0130  /* Receive Delay Timer (ring 1) */
460
461#define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */
462
463#define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */
464
465#define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */
466
467#define WMREG_OLD_RDH1  0x0148
468
469#define WMREG_OLD_RDT1  0x0150
470
471#define WMREG_OLD_FCRTH 0x0160  /* Flow Control Rx Threshold Hi (OLD) */
472#define WMREG_FCRTL     0x2160  /* Flow Control Rx Threshold Lo */
473#define FCRTH_DFLT      0x00008000
474
475#define WMREG_OLD_FCRTL 0x0168  /* Flow Control Rx Threshold Lo (OLD) */
476#define WMREG_FCRTH     0x2168  /* Flow Control Rx Threhsold Hi */
477#define FCRTL_DFLT      0x00004000
478#define FCRTL_XONE      0x80000000      /* Enable XON frame transmission */
479
480#define WMREG_FCTTV     0x0170  /* Flow Control Transmit Timer Value */
481#define FCTTV_DFLT      0x00000600
482
483#define WMREG_TXCW      0x0178  /* Transmit Configuration Word (TBI mode) */
484        /* See MII ANAR_X bits. */
485#define TXCW_TxConfig   (1U << 30)      /* Tx Config */
486#define TXCW_ANE        (1U << 31)      /* Autonegotiate */
487
488#define WMREG_RXCW      0x0180  /* Receive Configuration Word (TBI mode) */
489        /* See MII ANLPAR_X bits. */
490#define RXCW_NC         (1U << 26)      /* no carrier */
491#define RXCW_IV         (1U << 27)      /* config invalid */
492#define RXCW_CC         (1U << 28)      /* config change */
493#define RXCW_C          (1U << 29)      /* /C/ reception */
494#define RXCW_SYNCH      (1U << 30)      /* synchronized */
495#define RXCW_ANC        (1U << 31)      /* autonegotiation complete */
496
497#define WMREG_MTA       0x0200  /* Multicast Table Array */
498#define WMREG_CORDOVA_MTA 0x5200
499
500#define WMREG_TCTL      0x0400  /* Transmit Control Register */
501#define TCTL_EN         (1U << 1)       /* transmitter enable */
502#define TCTL_PSP        (1U << 3)       /* pad short packets */
503#define TCTL_CT(x)      (((x) & 0xff) << 4)   /* 4:11 - collision threshold */
504#define TCTL_COLD(x)    (((x) & 0x3ff) << 12) /* 12:21 - collision distance */
505#define TCTL_SWXOFF     (1U << 22)      /* software XOFF */
506#define TCTL_RTLC       (1U << 24)      /* retransmit on late collision */
507#define TCTL_NRTU       (1U << 25)      /* no retransmit on underrun */
508#define TCTL_MULR       (1U << 28)      /* multiple request */
509
510#define TX_COLLISION_THRESHOLD          15
511#define TX_COLLISION_DISTANCE_HDX       512
512#define TX_COLLISION_DISTANCE_FDX       64
513
514#define WMREG_TCTL_EXT  0x0404  /* Transmit Control Register */
515#define TCTL_EXT_BST_MASK       0x000003FF /* Backoff Slot Time */
516#define TCTL_EXT_GCEX_MASK      0x000FFC00 /* Gigabit Carry Extend Padding */
517
518#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
519
520#define WMREG_TQSA_LO   0x0408
521
522#define WMREG_TQSA_HI   0x040c
523
524#define WMREG_TIPG      0x0410  /* Transmit IPG Register */
525#define TIPG_IPGT(x)    (x)             /* IPG transmit time */
526#define TIPG_IPGR1(x)   ((x) << 10)     /* IPG receive time 1 */
527#define TIPG_IPGR2(x)   ((x) << 20)     /* IPG receive time 2 */
528
529#define TIPG_WM_DFLT    (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a))
530#define TIPG_LG_DFLT    (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06))
531#define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06))
532#define TIPG_1000T_80003_DFLT \
533    (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07))
534#define TIPG_10_100_80003_DFLT \
535    (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07))
536
537#define WMREG_TQC       0x0418
538
539#define WMREG_EEWR      0x102c  /* EEPROM write */
540
541#define WMREG_RDFH      0x2410  /* Receive Data FIFO Head */
542
543#define WMREG_RDFT      0x2418  /* Receive Data FIFO Tail */
544
545#define WMREG_RDFHS     0x2420  /* Receive Data FIFO Head Saved */
546
547#define WMREG_RDFTS     0x2428  /* Receive Data FIFO Tail Saved */
548
549#define WMREG_TDFH      0x3410  /* Transmit Data FIFO Head */
550
551#define WMREG_TDFT      0x3418  /* Transmit Data FIFO Tail */
552
553#define WMREG_TDFHS     0x3420  /* Transmit Data FIFO Head Saved */
554
555#define WMREG_TDFTS     0x3428  /* Transmit Data FIFO Tail Saved */
556
557#define WMREG_TDFPC     0x3430  /* Transmit Data FIFO Packet Count */
558
559#define WMREG_OLD_TBDAL 0x0420  /* Transmit Descriptor Base Lo */
560#define WMREG_TBDAL     0x3800
561
562#define WMREG_OLD_TBDAH 0x0424  /* Transmit Descriptor Base Hi */
563#define WMREG_TBDAH     0x3804
564
565#define WMREG_OLD_TDLEN 0x0428  /* Transmit Descriptor Length */
566#define WMREG_TDLEN     0x3808
567
568#define WMREG_OLD_TDH   0x0430  /* Transmit Descriptor Head */
569#define WMREG_TDH       0x3810
570
571#define WMREG_OLD_TDT   0x0438  /* Transmit Descriptor Tail */
572#define WMREG_TDT       0x3818
573
574#define WMREG_OLD_TIDV  0x0440  /* Transmit Delay Interrupt Value */
575#define WMREG_TIDV      0x3820
576
577#define WMREG_TXDCTL    0x3828  /* Trandmit Descriptor Control */
578#define TXDCTL_PTHRESH(x) ((x) << 0)    /* prefetch threshold */
579#define TXDCTL_HTHRESH(x) ((x) << 8)    /* host threshold */
580#define TXDCTL_WTHRESH(x) ((x) << 16)   /* write back threshold */
581
582#define WMREG_TADV      0x382c  /* Transmit Absolute Interrupt Delay Timer */
583
584#define WMREG_AIT       0x0458  /* Adaptive IFS Throttle */
585
586#define WMREG_VFTA      0x0600
587
588#define WM_MC_TABSIZE   128
589#define WM_ICH8_MC_TABSIZE 32
590#define WM_VLAN_TABSIZE 128
591
592#define WMREG_PBA       0x1000  /* Packet Buffer Allocation */
593#define PBA_BYTE_SHIFT  10              /* KB -> bytes */
594#define PBA_ADDR_SHIFT  7               /* KB -> quadwords */
595#define PBA_8K          0x0008
596#define PBA_12K         0x000c
597#define PBA_16K         0x0010          /* 16K, default Tx allocation */
598#define PBA_22K         0x0016
599#define PBA_24K         0x0018
600#define PBA_30K         0x001e
601#define PBA_32K         0x0020
602#define PBA_40K         0x0028
603#define PBA_48K         0x0030          /* 48K, default Rx allocation */
604
605#define WMREG_PBS       0x1000  /* Packet Buffer Size (ICH8 only ?) */
606
607#define WMREG_TXDMAC    0x3000  /* Transfer DMA Control */
608#define TXDMAC_DPP      (1U << 0)       /* disable packet prefetch */
609
610#define WMREG_TSPMT     0x3830  /* TCP Segmentation Pad and Minimum
611                                   Threshold (Cordova) */
612#define TSPMT_TSMT(x)   (x)             /* TCP seg min transfer */
613#define TSPMT_TSPBP(x)  ((x) << 16)     /* TCP seg pkt buf padding */
614
615#define WMREG_RXCSUM    0x5000  /* Receive Checksum register */
616#define RXCSUM_PCSS     0x000000ff      /* Packet Checksum Start */
617#define RXCSUM_IPOFL    (1U << 8)       /* IP checksum offload */
618#define RXCSUM_TUOFL    (1U << 9)       /* TCP/UDP checksum offload */
619#define RXCSUM_IPV6OFL  (1U << 10)      /* IPv6 checksum offload */
620
621#define WMREG_RXERRC    0x400C  /* receive error Count - R/clr */
622#define WMREG_COLC      0x4028  /* collision Count - R/clr */
623#define WMREG_XONRXC    0x4048  /* XON Rx Count - R/clr */
624#define WMREG_XONTXC    0x404c  /* XON Tx Count - R/clr */
625#define WMREG_XOFFRXC   0x4050  /* XOFF Rx Count - R/clr */
626#define WMREG_XOFFTXC   0x4054  /* XOFF Tx Count - R/clr */
627#define WMREG_FCRUC     0x4058  /* Flow Control Rx Unsupported Count - R/clr */
628
629#define WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */
630#define KUMCTRLSTA_MASK                 0x0000FFFF
631#define KUMCTRLSTA_OFFSET               0x001F0000
632#define KUMCTRLSTA_OFFSET_SHIFT         16
633#define KUMCTRLSTA_REN                  0x00200000
634
635#define KUMCTRLSTA_OFFSET_FIFO_CTRL     0x00000000
636#define KUMCTRLSTA_OFFSET_CTRL          0x00000001
637#define KUMCTRLSTA_OFFSET_INB_CTRL      0x00000002
638#define KUMCTRLSTA_OFFSET_DIAG          0x00000003
639#define KUMCTRLSTA_OFFSET_TIMEOUTS      0x00000004
640#define KUMCTRLSTA_OFFSET_INB_PARAM     0x00000009
641#define KUMCTRLSTA_OFFSET_HD_CTRL       0x00000010
642#define KUMCTRLSTA_OFFSET_M2P_SERDES    0x0000001E
643#define KUMCTRLSTA_OFFSET_M2P_MODES     0x0000001F
644
645/* FIFO Control */
646#define KUMCTRLSTA_FIFO_CTRL_RX_BYPASS  0x00000008
647#define KUMCTRLSTA_FIFO_CTRL_TX_BYPASS  0x00000800
648
649/* In-Band Control */
650#define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500
651#define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
652
653/* Half-Duplex Control */
654#define KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
655#define KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
656
657#define WMREG_MDPHYA    0x003C  /* PHY address - RW */
658
659#define WMREG_MANC2H    0x5860  /* Managment Control To Host - RW */
660
661#define WMREG_SWSM      0x5b50  /* SW Semaphore */
662#define SWSM_SMBI       0x00000001      /* Driver Semaphore bit */
663#define SWSM_SWESMBI    0x00000002      /* FW Semaphore bit */
664#define SWSM_WMNG       0x00000004      /* Wake MNG Clock */
665#define SWSM_DRV_LOAD   0x00000008      /* Driver Loaded Bit */
666
667#define WMREG_SW_FW_SYNC 0x5b5c /* software-firmware semaphore */
668#define SWFW_EEP_SM             0x0001 /* eeprom access */
669#define SWFW_PHY0_SM            0x0002 /* first ctrl phy access */
670#define SWFW_PHY1_SM            0x0004 /* second ctrl phy access */
671#define SWFW_MAC_CSR_SM         0x0008
672#define SWFW_SOFT_SHIFT         0       /* software semaphores */
673#define SWFW_FIRM_SHIFT         16      /* firmware semaphores */
674
675#define WMREG_EXTCNFCTR         0x0f00  /* Extended Configuration Control */
676#define EXTCNFCTR_PCIE_WRITE_ENABLE     0x00000001
677#define EXTCNFCTR_PHY_WRITE_ENABLE      0x00000002
678#define EXTCNFCTR_D_UD_ENABLE           0x00000004
679#define EXTCNFCTR_D_UD_LATENCY          0x00000008
680#define EXTCNFCTR_D_UD_OWNER            0x00000010
681#define EXTCNFCTR_MDIO_SW_OWNERSHIP     0x00000020
682#define EXTCNFCTR_MDIO_HW_OWNERSHIP     0x00000040
683#define EXTCNFCTR_EXT_CNF_POINTER       0x0FFF0000
684#define E1000_EXTCNF_CTRL_SWFLAG        EXTCNFCTR_MDIO_SW_OWNERSHIP
685
686/* ich8 flash control */
687#define ICH_FLASH_COMMAND_TIMEOUT            5000    /* 5000 uSecs - adjusted */
688#define ICH_FLASH_ERASE_TIMEOUT              3000000 /* Up to 3 seconds - worst case */
689#define ICH_FLASH_CYCLE_REPEAT_COUNT         10      /* 10 cycles */
690#define ICH_FLASH_SEG_SIZE_256               256
691#define ICH_FLASH_SEG_SIZE_4K                4096
692#define ICH_FLASH_SEG_SIZE_64K               65536
693
694#define ICH_CYCLE_READ                       0x0
695#define ICH_CYCLE_RESERVED                   0x1
696#define ICH_CYCLE_WRITE                      0x2
697#define ICH_CYCLE_ERASE                      0x3
698
699#define ICH_FLASH_GFPREG   0x0000
700#define ICH_FLASH_HSFSTS   0x0004 /* Flash Status Register */
701#define HSFSTS_DONE             0x0001 /* Flash Cycle Done */
702#define HSFSTS_ERR              0x0002 /* Flash Cycle Error */
703#define HSFSTS_DAEL             0x0004 /* Direct Access error Log */
704#define HSFSTS_ERSZ_MASK        0x0018 /* Block/Sector Erase Size */
705#define HSFSTS_ERSZ_SHIFT       3
706#define HSFSTS_FLINPRO          0x0020 /* flash SPI cycle in Progress */
707#define HSFSTS_FLDVAL           0x4000 /* Flash Descriptor Valid */
708#define HSFSTS_FLLK             0x8000 /* Flash Configuration Lock-Down */
709#define ICH_FLASH_HSFCTL   0x0006 /* Flash control Register */
710#define HSFCTL_GO               0x0001 /* Flash Cycle Go */
711#define HSFCTL_CYCLE_MASK       0x0006 /* Flash Cycle */
712#define HSFCTL_CYCLE_SHIFT      1
713#define HSFCTL_BCOUNT_MASK      0x0300 /* Data Byte Count */
714#define HSFCTL_BCOUNT_SHIFT     8
715#define ICH_FLASH_FADDR    0x0008
716#define ICH_FLASH_FDATA0   0x0010
717#define ICH_FLASH_FRACC    0x0050
718#define ICH_FLASH_FREG0    0x0054
719#define ICH_FLASH_FREG1    0x0058
720#define ICH_FLASH_FREG2    0x005C
721#define ICH_FLASH_FREG3    0x0060
722#define ICH_FLASH_FPR0     0x0074
723#define ICH_FLASH_FPR1     0x0078
724#define ICH_FLASH_SSFSTS   0x0090
725#define ICH_FLASH_SSFCTL   0x0092
726#define ICH_FLASH_PREOP    0x0094
727#define ICH_FLASH_OPTYPE   0x0096
728#define ICH_FLASH_OPMENU   0x0098
729
730#define ICH_FLASH_REG_MAPSIZE      0x00A0
731#define ICH_FLASH_SECTOR_SIZE      4096
732#define ICH_GFPREG_BASE_MASK       0x1FFF
733#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
734
735/* start of Kate Feng added */
736#define WMREG_GPTC      0x4080  /* Good packets transmitted count */
737#define WMREG_GPRC      0x4074  /* Good packets received count */
738#define WMREG_CRCERRS   0x4000  /* CRC Error Count */
739#define WMREG_RLEC      0x4040  /* Receive Length Error Count */
740/* end of Kate Feng added */
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