[7be6ad9] | 1 | /* |
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| 2 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 3 | * |
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| 4 | * The license and distribution terms for this file may be |
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[0c875c6a] | 5 | * found in the file LICENSE in this distribution or at |
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[c499856] | 6 | * http://www.rtems.org/license/LICENSE. |
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[7be6ad9] | 7 | * |
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[72510eb2] | 8 | * (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. |
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[7be6ad9] | 9 | */ |
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| 10 | |
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[9cff822a] | 11 | #ifndef LIBBSP_POWERPC_MVME5500_BSP_H |
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| 12 | #define LIBBSP_POWERPC_MVME5500_BSP_H |
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[7be6ad9] | 13 | |
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[0659b5de] | 14 | #ifndef ASM |
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| 15 | |
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[7be6ad9] | 16 | #include <bspopts.h> |
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[a052181] | 17 | #include <bsp/default-initial-extension.h> |
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[7be6ad9] | 18 | |
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| 19 | #include <rtems.h> |
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| 20 | #include <libcpu/io.h> |
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| 21 | #include <bsp/vectors.h> |
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| 22 | |
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[72510eb2] | 23 | /* Board type */ |
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| 24 | typedef enum { |
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[0659b5de] | 25 | undefined = 0, |
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| 26 | MVME5500, |
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| 27 | MVME6100 |
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[72510eb2] | 28 | } BSP_BoardTypes; |
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| 29 | |
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[0659b5de] | 30 | BSP_BoardTypes BSP_getBoardType(void); |
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[72510eb2] | 31 | |
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| 32 | /* Board type */ |
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| 33 | typedef enum { |
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[0659b5de] | 34 | Undefined, |
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| 35 | UNIVERSE2, |
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| 36 | TSI148, |
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[72510eb2] | 37 | } BSP_VMEchipTypes; |
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| 38 | |
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[0659b5de] | 39 | BSP_VMEchipTypes BSP_getVMEchipType(void); |
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[72510eb2] | 40 | |
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| 41 | /* The version of Discovery system controller */ |
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| 42 | |
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| 43 | typedef enum { |
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[0659b5de] | 44 | notdefined, |
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| 45 | GT64260A, |
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| 46 | GT64260B, |
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| 47 | MV64360, |
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[72510eb2] | 48 | } DiscoveryChipVersion; |
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| 49 | |
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[0659b5de] | 50 | DiscoveryChipVersion BSP_getDiscoveryChipVersion(void); |
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[72510eb2] | 51 | |
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| 52 | #define _256M 0x10000000 |
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| 53 | #define _512M 0x20000000 |
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| 54 | |
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[0659b5de] | 55 | #define GT64x60_REG_BASE 0xf1000000 /* Base of GT64260 Reg Space */ |
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| 56 | #define GT64x60_REG_SPACE_SIZE 0x10000 /* 64Kb Internal Reg Space */ |
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[72510eb2] | 57 | |
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| 58 | #define GT64x60_DEV1_BASE 0xf1100000 /* Device bank1(chip select 1) base |
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| 59 | */ |
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[0659b5de] | 60 | #define GT64260_DEV1_SIZE 0x00100000 /* Device bank size */ |
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[7be6ad9] | 61 | |
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| 62 | /* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */ |
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[72510eb2] | 63 | #define _IO_BASE GT64x60_REG_BASE |
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| 64 | |
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| 65 | #define BSP_NVRAM_BASE_ADDR 0xf1110000 |
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| 66 | |
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| 67 | #define BSP_RTC_INTA_REG 0x7ff0 |
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[0659b5de] | 68 | #define BSP_RTC_SECOND 0x7ff2 |
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| 69 | #define BSP_RTC_MINUTE 0x7ff3 |
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| 70 | #define BSP_RTC_HOUR 0x7ff4 |
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| 71 | #define BSP_RTC_DATE 0x7ff5 |
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[72510eb2] | 72 | #define BSP_RTC_INTERRUPTS 0x7ff6 |
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| 73 | #define BSP_RTC_WATCHDOG 0x7ff7 |
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[7be6ad9] | 74 | |
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| 75 | /* PCI0 Domain I/O space */ |
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| 76 | #define PCI0_IO_BASE 0xf0000000 |
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| 77 | #define PCI1_IO_BASE 0xf0800000 |
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| 78 | |
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| 79 | /* PCI 0 memory space as seen from the CPU */ |
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[0659b5de] | 80 | #define PCI0_MEM_BASE 0x80000000 |
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| 81 | #define PCI_MEM_BASE 0 /* glue for vmeUniverse */ |
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[4406c2f] | 82 | #define PCI_MEM_BASE_ADJUSTMENT 0 |
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[7be6ad9] | 83 | |
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| 84 | /* address of our ram on the PCI bus */ |
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[0659b5de] | 85 | #define PCI_DRAM_OFFSET 0 |
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[7be6ad9] | 86 | |
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| 87 | /* PCI 1 memory space as seen from the CPU */ |
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[0659b5de] | 88 | #define PCI1_MEM_BASE 0xe0000000 |
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[7be6ad9] | 89 | #define PCI1_MEM_SIZE 0x10000000 |
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| 90 | |
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[54cb48f] | 91 | /* Needed for hot adding via PMCspan on the PCI0 local bus. |
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| 92 | * This is board dependent, only because mvme5500 |
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| 93 | * supports hot adding and has more than one local PCI |
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| 94 | * bus. |
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| 95 | */ |
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| 96 | #define BSP_MAX_PCI_BUS_ON_PCI0 8 |
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| 97 | #define BSP_MAX_PCI_BUS_ON_PCI1 2 |
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| 98 | #define BSP_MAX_PCI_BUS (BSP_MAX_PCI_BUS_ON_PCI0+BSP_MAX_PCI_BUS_ON_PCI1) |
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| 99 | |
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| 100 | |
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[ee732739] | 101 | /* The glues to Till's vmeUniverse, although the name does not |
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| 102 | * actually reflect the relevant architect of the MVME5500. |
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| 103 | */ |
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[7be6ad9] | 104 | #define BSP_PCI_IRQ0 BSP_GPP_IRQ_LOWEST_OFFSET |
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| 105 | |
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| 106 | /* |
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| 107 | * confdefs.h overrides for this BSP: |
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| 108 | * - Interrupt stack space is not minimum if defined. |
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| 109 | */ |
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[72510eb2] | 110 | #define BSP_INTERRUPT_STACK_SIZE (16 * 1024) /* <skf> 2/09 wants it to be adjustable by BSP */ |
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| 111 | |
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[7be6ad9] | 112 | /* uart.c uses out_8 instead of outb */ |
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[0659b5de] | 113 | #define BSP_UART_IOBASE_COM1 GT64x60_DEV1_BASE + 0x20000 |
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| 114 | #define BSP_UART_IOBASE_COM2 GT64x60_DEV1_BASE + 0x21000 |
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[7be6ad9] | 115 | |
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[0659b5de] | 116 | #define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ |
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| 117 | #define BSP_UART_BAUD_BASE 115200 |
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[7be6ad9] | 118 | |
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| 119 | /* |
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| 120 | * Total memory using RESIDUAL DATA |
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| 121 | */ |
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| 122 | extern unsigned int BSP_mem_size; |
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| 123 | /* |
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| 124 | * PCI Bus Frequency |
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| 125 | */ |
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| 126 | extern unsigned int BSP_bus_frequency; |
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| 127 | /* |
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| 128 | * processor clock frequency |
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| 129 | */ |
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| 130 | extern unsigned int BSP_processor_frequency; |
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| 131 | /* |
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| 132 | * Time base divisior (how many tick for 1 second). |
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| 133 | */ |
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| 134 | extern unsigned int BSP_time_base_divisor; |
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| 135 | |
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| 136 | #define BSP_Convert_decrementer( _value ) \ |
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| 137 | ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) |
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| 138 | |
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[72510eb2] | 139 | extern void bsp_reset(void); |
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[7be6ad9] | 140 | /* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ |
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[0659b5de] | 141 | extern int BSP_disconnect_clock_handler(void); |
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| 142 | extern int BSP_connect_clock_handler(void); |
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[7be6ad9] | 143 | |
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[0659b5de] | 144 | unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); |
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| 145 | |
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| 146 | /* |
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| 147 | * Prototypes for methods called only from .S for dependency tracking |
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| 148 | */ |
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| 149 | char *save_boot_params( |
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| 150 | void *r3, |
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| 151 | void *r4, |
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| 152 | void *r5, |
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| 153 | char *cmdline_start, |
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| 154 | char *cmdline_end |
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| 155 | ); |
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| 156 | void zero_bss(void); |
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| 157 | |
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| 158 | /* |
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| 159 | * Prototypes for methods in the BSP that cross file boundaries |
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| 160 | */ |
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| 161 | uint32_t probeMemoryEnd(void); |
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| 162 | void pci_interface(void); |
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| 163 | void BSP_printPicIsrTbl(void); |
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| 164 | int I2Cread_eeprom( |
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| 165 | unsigned char I2cBusAddr, |
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| 166 | uint32_t devA2A1A0, |
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| 167 | uint32_t AddrBytes, |
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| 168 | unsigned char *pBuff, |
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| 169 | uint32_t numBytes |
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| 170 | ); |
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[7be6ad9] | 171 | |
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[ee732739] | 172 | #if 0 |
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[0659b5de] | 173 | #define RTEMS_BSP_NETWORK_DRIVER_NAME "gt1" |
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| 174 | #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_GT64260eth_driver_attach |
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[ee732739] | 175 | #else |
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[0659b5de] | 176 | #define RTEMS_BSP_NETWORK_DRIVER_NAME "wmG1" |
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| 177 | #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_i82544EI_driver_attach |
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[ee732739] | 178 | #endif |
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[7be6ad9] | 179 | |
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[72510eb2] | 180 | extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH(); |
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[7be6ad9] | 181 | |
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[72510eb2] | 182 | #define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER() |
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[ee732739] | 183 | |
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[0659b5de] | 184 | static inline void lwmemBar(void) |
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[72510eb2] | 185 | { |
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[3e6c5a7] | 186 | __asm__ volatile("lwsync":::"memory"); |
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[72510eb2] | 187 | } |
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| 188 | |
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[0659b5de] | 189 | static inline void io_flush(void) |
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[72510eb2] | 190 | { |
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[3e6c5a7] | 191 | __asm__ volatile("isync":::"memory"); |
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[72510eb2] | 192 | } |
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[0659b5de] | 193 | |
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| 194 | static inline void memBar(void) |
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[ee732739] | 195 | { |
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[3e6c5a7] | 196 | __asm__ volatile("sync":::"memory"); |
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[ee732739] | 197 | } |
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[0659b5de] | 198 | |
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| 199 | static inline void ioBar(void) |
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[ee732739] | 200 | { |
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[3e6c5a7] | 201 | __asm__ volatile("eieio":::"memory"); |
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[ee732739] | 202 | } |
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[7be6ad9] | 203 | |
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[ac7af4a] | 204 | #endif |
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[0659b5de] | 205 | |
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| 206 | #endif /* !ASM */ |
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