1 | /* |
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2 | * start.S : RTEMS entry point |
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3 | * |
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4 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.org/license/LICENSE. |
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9 | * |
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10 | * Modified for mvme3100 by T. Straumann, 2007. |
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11 | * |
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12 | */ |
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13 | |
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14 | #include <rtems/asm.h> |
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15 | #include <rtems/score/cpu.h> |
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16 | #include <rtems/powerpc/powerpc.h> |
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17 | |
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18 | #include <bspopts.h> |
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19 | |
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20 | #define SYNC \ |
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21 | sync; \ |
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22 | isync |
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23 | |
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24 | #define KERNELBASE 0x0 |
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25 | |
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26 | /* cannot include <bsp.h> from assembly :-( */ |
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27 | #ifndef BSP_8540_CCSR_BASE |
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28 | #define BSP_8540_CCSR_BASE 0xe1000000 |
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29 | #endif |
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30 | |
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31 | #define ERR_DISABLE_REG (BSP_8540_CCSR_BASE + 0x2e44) |
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32 | |
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33 | .text |
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34 | .globl __rtems_entry_point |
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35 | .type __rtems_entry_point,@function |
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36 | __rtems_entry_point: |
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37 | mr r31,r3 |
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38 | mr r30,r4 |
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39 | mr r29,r5 |
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40 | mr r28,r6 |
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41 | mr r27,r7 |
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42 | /* disable checking for memory-select errors; motload has all TLBs |
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43 | * mapping a possible larger area as memory (not-guarded, caching-enabled) |
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44 | * than actual physical memory is available. |
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45 | * In case of speculative loads this may cause 'memory-select' errors |
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46 | * which seem to raise 'core_fault_in' (found no description in |
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47 | * the manual but I experienced this problem). |
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48 | * Such errors (if HID1[RFXE] is clear) may *stall* execution |
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49 | * leading to mysterious 'hangs'. |
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50 | * Note: enabling HID1[RFXE] at this point makes no sense since |
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51 | * exceptions are not configured yet. Therefore we disable |
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52 | * memory-select errors. |
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53 | * Eventually (bspstart.c) we want to delete TLB entries for |
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54 | * which no physical memory is present. |
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55 | */ |
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56 | lis r3, ERR_DISABLE_REG@ha |
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57 | lwz r4, ERR_DISABLE_REG@l(r3) |
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58 | /* disable memory-select errors */ |
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59 | ori r4, r4, 1 |
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60 | stw r4, ERR_DISABLE_REG@l(r3) |
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61 | |
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62 | /* Use MotLoad's TLB setup for now; caches are on already */ |
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63 | bl __eabi /* setup EABI and SYSV environment */ |
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64 | bl zero_bss |
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65 | /* |
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66 | * restore original args |
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67 | */ |
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68 | mr r3,r31 |
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69 | mr r4,r30 |
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70 | mr r5,r29 |
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71 | mr r6,r28 |
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72 | mr r7,r27 |
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73 | bl save_boot_params |
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74 | addis r9,r0, (__stack-PPC_MINIMUM_STACK_FRAME_SIZE)@ha |
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75 | addi r9,r9, (__stack-PPC_MINIMUM_STACK_FRAME_SIZE)@l |
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76 | /* align down to 16-bytes */ |
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77 | li r5, (CPU_STACK_ALIGNMENT - 1) |
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78 | andc r1, r9, r5 |
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79 | |
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80 | /* NULL ptr to back chain */ |
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81 | li r0, 0 |
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82 | stw r0, 0(r1) |
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83 | |
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84 | /* |
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85 | * We are now in a environment that is totally independent from |
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86 | * bootloader setup. |
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87 | */ |
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88 | /* pass result of 'save_boot_params' to 'boot_card' in R3 */ |
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89 | bl boot_card |
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90 | /* point of no return: reset board here ? */ |
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