source: rtems/bsps/powerpc/mvme3100/include/bsp/irq.h @ 45d0659

Last change on this file since 45d0659 was 45d0659, checked in by Sebastian Huber <sebastian.huber@…>, on May 11, 2019 at 12:57:39 PM

bsps: Always build generic interrupt support

This makes it possible to write tests for the generic interrupt
controller support.

Update #3269.

  • Property mode set to 100644
File size: 4.2 KB
RevLine 
[a77c3719]1/**
2 *  @file
3 *
4 *  @ingroup powerpc_irq
5 *
6 *  @brief This include file describe the data structure and the functions
7 *  implemented by RTEMS to write interrupt handlers.
8 */
9
[b599faa]10/* irq.h
11 *
12 *  This include file describe the data structure and the functions implemented
13 *  by RTEMS to write interrupt handlers.
14 *
15 *  Copyright (C) 1999 valette@crf.canon.fr
16 *
17 *  This code is heavilly inspired by the public specification of STREAM V2
18 *  that can be found at :
19 *
20 *      <http://www.chorus.com/Documentation/index.html> by following
21 *  the STREAM API Specification Document link.
22 *
23 *  The license and distribution terms for this file may be
[0c875c6a]24 *  found in the file LICENSE in this distribution or at
[c499856]25 *  http://www.rtems.org/license/LICENSE.
[b599faa]26 *
27 *  Adapted for the mvme3100 BSP by T. Straumann, 2007.
28 */
29
30#ifndef BSP_POWERPC_IRQ_H
31#define BSP_POWERPC_IRQ_H
32
33#define BSP_SHARED_HANDLER_SUPPORT      1
34#include <rtems/irq.h>
35
36#ifndef ASM
37
[45d0659]38#include <bsp/irq-default.h>
39
[b599faa]40#ifdef __cplusplus
41extern "C" {
42#endif
43
[a77c3719]44/**
45 *  @defgroup powerpc_irq Definitions
46 *
[c991eeec]47 *  @ingroup RTEMSBSPsPowerPCMVME3100
[a77c3719]48 *
49 *  @brief rtems_irq_number Definitions
[b599faa]50 */
51
52/* Must pad number of external sources to 16 because
53 * of the layout of vector/priority registers in the
54 * 8540's openpic where there is a gap between
55 * registers corresponding to external and core sources.
56 */
57#define BSP_EXT_IRQ_NUMBER          (16)
58#define BSP_CORE_IRQ_NUMBER                     (32)
59
60/* openpic glue code from shared/irq assigns priorities and configures
61 * initial ISRs for BSP_PCI_IRQ_NUMBER entries (plus ISA stuff on legacy
62 * boards). Hence PCI_IRQ_NUMBER must also cover the internal sources
63 * even though they have nothing to do with PCI.
64 */
65#define BSP_PCI_IRQ_NUMBER                      (BSP_EXT_IRQ_NUMBER + BSP_CORE_IRQ_NUMBER)
66#define BSP_PCI_IRQ_LOWEST_OFFSET       (0)
67#define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
68
69#define BSP_CORE_IRQ_LOWEST_OFFSET  (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_EXT_IRQ_NUMBER)
70#define BSP_CORE_IRQ_MAX_OFFSET         (BSP_CORE_IRQ_LOWEST_OFFSET + BSP_CORE_IRQ_NUMBER - 1)
71
72/*
73 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
74 * handler might be connected
75 */
76#define BSP_PROCESSOR_IRQ_NUMBER        (1)
77#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CORE_IRQ_MAX_OFFSET + 1)
78#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
79/* Misc vectors for OPENPIC irqs (IPI, timers)
80 */
81#define BSP_MISC_IRQ_NUMBER             (8)
82#define BSP_MISC_IRQ_LOWEST_OFFSET      (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
83#define BSP_MISC_IRQ_MAX_OFFSET         (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
84/*
85 * Summary
86 */
87#define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
88#define BSP_LOWEST_OFFSET               (BSP_PCI_IRQ_LOWEST_OFFSET)
89#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
90
91/*
92 * Some PCI IRQ symbolic name definition
93 */
94#define BSP_PCI_IRQ0                    (BSP_PCI_IRQ_LOWEST_OFFSET)
95
96#define BSP_VME0_IRQ                    (BSP_PCI_IRQ_LOWEST_OFFSET  +  0)
97#define BSP_VME1_IRQ                    (BSP_PCI_IRQ_LOWEST_OFFSET  +  1)
98#define BSP_VME2_IRQ                    (BSP_PCI_IRQ_LOWEST_OFFSET  +  2)
99#define BSP_VME3_IRQ                    (BSP_PCI_IRQ_LOWEST_OFFSET  +  3)
100
101#define BSP_ABORT_IRQ                   (BSP_PCI_IRQ_LOWEST_OFFSET  +  8)
102#define BSP_TEMP_IRQ                    (BSP_PCI_IRQ_LOWEST_OFFSET  +  9)
103#define BSP_PHY_IRQ                             (BSP_PCI_IRQ_LOWEST_OFFSET  + 10)
104#define BSP_RTC_IRQ                             (BSP_PCI_IRQ_LOWEST_OFFSET  + 11)
105
106/* Weird - they provide 3 different IRQ lines per ethernet controller
107 * but only one shared line for 2 UARTs ???
108 */
109#define BSP_UART_COM1_IRQ               (BSP_CORE_IRQ_LOWEST_OFFSET + 26)
110#define BSP_UART_COM2_IRQ               (BSP_CORE_IRQ_LOWEST_OFFSET + 26)
111#define BSP_I2C_IRQ                             (BSP_CORE_IRQ_LOWEST_OFFSET + 27)
112
[ac7af4a]113/*
[b599faa]114 * Some internal (CORE) name definitions
115 */
116/* Ethernet (FEC) */
117#define BSP_CORE_IRQ_FEC                (BSP_CORE_IRQ_LOWEST_OFFSET + 25)
118/* i2c controller */
119#define BSP_CORE_IRQ_I2C                (BSP_CORE_IRQ_LOWEST_OFFSET + 27)
120
121/*
122 * Some Processor execption handled as RTEMS IRQ symbolic name definition
123 */
124#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
125
126/*-------------------------------------------------------------------------+
127| Function Prototypes.
128+--------------------------------------------------------------------------*/
129
130extern void BSP_rtems_irq_mng_init(unsigned cpuId);
131
132#include <bsp/irq_supp.h>
133
134#ifdef __cplusplus
135};
136#endif
137
138#endif
139#endif
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