source: rtems/bsps/powerpc/mpc8260ads/start/start.S @ fbcd7c8f

Last change on this file since fbcd7c8f was fbcd7c8f, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 20, 2018 at 8:19:28 AM

bsps: Move start files to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 4.5 KB
RevLine 
[5edbffe]1/*  start.S
2 *
3 *  Modified for the Motorola PQII ADS board by
4 *  Andy Dachs <a.dachs@sstl.co.uk> 23-11-00.
5 *  Surrey Satellite Technology Limited
6 *
7 *  I have a proprietary bootloader programmed into the flash
8 *  on the board which initialises the SDRAM prior to calling
9 *  this function.
10 *
11 *  This file is based on the one by Jay Monkman (jmonkman@fracsa.com)
12 *  which in turn was based on the dlentry.s file for the Papyrus BSP,
13 *  written by:
14 *
15 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
16 *
17 *  COPYRIGHT (c) 1995 by i-cubed ltd.
18 *
19 *  To anyone who acknowledges that this file is provided "AS IS"
20 *  without any express or implied warranty:
21 *      permission to use, copy, modify, and distribute this file
22 *      for any purpose is hereby granted without fee, provided that
23 *      the above copyright notice and this notice appears in all
24 *      copies, and that the name of i-cubed limited not be used in
25 *      advertising or publicity pertaining to distribution of the
26 *      software without specific, written prior permission.
27 *      i-cubed limited makes no representations about the suitability
28 *      of this software for any purpose.
29 *
30 */
31
[40e9b095]32#include <rtems/asm.h>
[5edbffe]33
34/*
35 *  The initial stack is set to run BELOW the code base address.
36 *  (between the vectors and text sections)
37 *
38 *  The entry veneer has to clear the BSS and copy the read only
39 *  version of the data segment to the correct location.
40 */
41
[6128a4a]42        .section ".entry"  /* This might have to be the first thing in the
[5edbffe]43                            * text section. At one time, it had to be
44                            * first, but I don't believe it is true
45                            * any more. */
46        PUBLIC_VAR (start)
47SYM(start):
48        bl      .startup
[6128a4a]49base_addr:
[5edbffe]50
51/*
52 * Parameters from linker
53 */
[6128a4a]54toc_pointer:
[5edbffe]55        .long   s.got
[6128a4a]56bss_length:
[5edbffe]57        .long   bss.size
[6128a4a]58bss_addr:
[5edbffe]59        .long   bss.start
60
61PUBLIC_VAR (data_length )
62data_length:
63        .long   data.size
64PUBLIC_VAR (data_addr )
65data_addr:
66        .long   data.start
67
68PUBLIC_VAR (text_addr)
69text_addr:
70        .long   text.start
71
72PUBLIC_VAR (text_length)
73text_length:
74        .long   text.size
75
76/*
[6128a4a]77 * Initialization code
[5edbffe]78 */
79.startup:
80    /* Get start address */
81        mflr    r1
82
83    /* --------------------------------------------------
84     * Clear MSR[EE] to disable interrupts
85     * Clear MSR[IP] bit to put vectors at 0x00000000
86     * Set MSR[FP] to enable FPU - not on my eval board!
87     * -------------------------------------------------- */
88        mfmsr   r5
89        lis     r13, 0xFFFF
90        ori     r13, r13, 0x7FBF
91        and     r5, r5, r13                     /* Clear EE and IP */
92#if 1
93        ori     r5, r5, 0x2000                  /* Enable FPU */
94#endif
95        mtmsr   r5
96
[6128a4a]97#ifdef ENABLE_CACHE
[5edbffe]98        /* Enable caches */
99        mfspr   r5, 1008
100        ori     r5, r5, 0x8000
101        isync
102        mtspr   1008, r5
[6128a4a]103
[5edbffe]104/*      Leave D-cache disabled for now */
[6128a4a]105#if 0
[5edbffe]106        ori     r5, r5, 0x4000
107        sync
108        mtspr   1008, r5
109#endif
110#endif
111
112        /*--------------------------------------------------
113         * Set up the power management modes
114         * The 8260 has a dynamic power management mode that
115         * is automatically invoked if the unit is idle.
116         * We invoke the NAP mode in the RTEMS idle task.
117         *-------------------------------------------------- */
118
119        lis     r13, 0x0050     /* set nap mode and DPM */
[6128a4a]120        or      r5, r5, r13
[5edbffe]121        mtspr   1008, r5
122
123        /*--------------------------------------------------
124         *
125         *-------------------------------------------------- */
126
127        /* clear the bss section */
128        bl      bssclr
129
130/*
131 * C_setup.
132 */
133
134        /* set toc */
135        lwz r2, toc_pointer-base_addr(r1)
136
137        /* Set up stack pointer = beginning of text section - 56 */
138        addi    r1, r1, -56-4
139
[820d1ab0]140        /* Clear cmdline */
[aa058378]141        xor r3, r3, r3
[6128a4a]142
[5edbffe]143        .extern SYM (boot_card)
144        bl       SYM (boot_card)        /* call the first C routine */
145
146        /* we don't expect to return from boot_card but if we do */
147        /* wait here for watchdog to kick us into hard reset     */
148
149twiddle:
150        b               twiddle
151
152/*
153 * bssclr - zero out bss
154 */
155bssclr:
156        lwz     r4, bss_addr-base_addr(r1)      /* Start of bss */
157        lwz     r5, bss_length-base_addr(r1)    /* Length of bss */
158
159        rlwinm. r5,r5,30,0x3FFFFFFF             /* form length/4 */
160        beqlr                                   /* no bss */
161        mtctr   r5                              /* set ctr reg */
162        xor     r6,r6,r6                        /* r6 = 0 */
163clear_bss:
164        stswi   r6,r4,0x4                       /* store r6 */
165        addi    r4,r4,0x4                       /* update r2 */
166
167        bdnz    clear_bss                       /* dec counter and loop */
168        blr                                     /* return */
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