source: rtems/bsps/powerpc/mpc8260ads/start/mmu.c @ a12dcff8

5
Last change on this file since a12dcff8 was a12dcff8, checked in by Sebastian Huber <sebastian.huber@…>, on Mar 23, 2018 at 3:04:18 PM

bsp/mpc8260: Move libcpu content to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 3.9 KB
Line 
1/*
2 * mmu.c
3 *
4 * This file contains routines for initializing
5 * and manipulating the MMU on the MPC8xx.
6 *
7 * Copyright (c) 1999, National Research Council of Canada
8 *
9 * Trivially modified for mpc8260 21.3.2001
10 * Andy Dachs <a.dachs@sstl.co.uk>
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 * http://www.rtems.org/license/LICENSE.
15 */
16
17#include <rtems.h>
18#include <mpc8260.h>
19#include <mpc8260/mmu.h>
20
21/*
22 * mmu_init
23 *
24 * This routine sets up the virtual memory maps on an MPC8xx.
25 * The MPC8xx does not support block address translation (BATs)
26 * and does not have segment registers. Thus, we must set up page
27 * translation. However, its MMU supports variable size pages
28 * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task.
29 *
30 * The MPC8xx has separate data and instruction 32-entry translation
31 * lookaside buffers (TLB). By mapping all of DRAM as one huge page,
32 * we can preload the TLBs and not have to be concerned with taking
33 * TLB miss exceptions.
34 *
35 * We set up the virtual memory map so that virtual address of a
36 * location is equal to its real address.
37 */
38void mmu_init( void )
39{
40#if 0
41/* so far we leave mmu uninitialised */
42
43  register uint32_t   reg1, i;
44
45  /*
46   * Initialize the TLBs
47   *
48   * Instruction address translation and data address translation
49   * must be disabled during initialization (IR=0, DR=0 in MSR).
50   * We can assume the MSR has already been set this way.
51   */
52
53  /*
54   * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR)
55   *    GPM [0]                 0b0 = PowerPC mode
56   *    PPM [1]                 0b0 = Page resolution of protection
57   *    CIDEF [2]               0b0/0b1 = Default cache-inhibit attribute =
58   *                                                    NO for IMMU, YES for DMMU!
59   *    reserved/WTDEF [3]      0b0 = Default write-through attribute = not
60   *    RSV4x [4]               0b0 = 4 entries not reserved
61   *    reserved/TWAM [5]       0b0/0b1 = 4-Kbyte page hardware assist
62   *    PPCS [6]                0b0 = Ignore user/supervisor state
63   *    reserved [7-18]         0x00
64   *    xTLB_INDX [19-23]       31 = 0x1F
65   *    reserved [24-31]        0x00
66   *
67   * Note: It is important that cache-inhibit be set as the default for the
68   * data cache when the DMMU is disabled in order to prevent internal memory
69   * mapped registers from being cached accidentally when address translation
70   * is turned off at the start of exception processing.
71   */
72  reg1 = M8xx_MI_CTR_ITLB_INDX(31);
73  _mtspr( M8xx_MI_CTR, reg1 );
74  reg1 = M8xx_MD_CTR_CIDEF | M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31);
75  _mtspr( M8xx_MD_CTR, reg1 );
76  _isync;
77
78  /*
79   * Invalidate all TLB entries in both TLBs.
80   * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so
81   *       all 32 entries are invalidated.
82   */
83  __asm__ volatile ("tlbia\n"::);
84  _isync;
85
86  /*
87   * Set Current Address Space ID Register (M_CASID).
88   * Supervisor: CASID = 0
89   */
90  reg1 = 0;
91  _mtspr( M8xx_M_CASID, reg1 );
92
93  /*
94   * Initialize the MMU Access Protection Registers (MI_AP, MD_AP)
95   * We ignore the Access Protection Group (APG) mechanism globally
96   * by setting all of the Mx_AP fields to 0b01 : client access
97   * permission is defined by page protection bits.
98   */
99  reg1 = 0x55555555;
100  _mtspr( M8xx_MI_AP, reg1 );
101  _mtspr( M8xx_MD_AP, reg1 );
102
103  /*
104   * Load both 32-entry TLBs with values from the MMU_TLB_table
105   * which is defined in the BSP.
106   * Note the _TLB_Table must have at most 32 entries. This code
107   * makes no effort to enforce this restriction.
108   */
109  for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) {
110    reg1 = MMU_TLB_table[i].mmu_epn;
111    _mtspr( M8xx_MI_EPN, reg1 );
112    _mtspr( M8xx_MD_EPN, reg1 );
113    reg1 = MMU_TLB_table[i].mmu_twc;
114    _mtspr( M8xx_MI_TWC, reg1 );
115    _mtspr( M8xx_MD_TWC, reg1 );
116    reg1 = MMU_TLB_table[i].mmu_rpn;    /* RPN must be written last! */
117    _mtspr( M8xx_MI_RPN, reg1 );
118    _mtspr( M8xx_MD_RPN, reg1 );
119  }
120
121  /*
122   * Turn on address translation by setting MSR[IR] and MSR[DR].
123   */
124  _CPU_MSR_GET( reg1 );
125  reg1 |= PPC_MSR_IR | PPC_MSR_DR;
126  _CPU_MSR_SET( reg1 );
127
128#endif
129
130}
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