source: rtems/bsps/powerpc/mpc8260ads/start/cpuinit.c @ 9964895

5
Last change on this file since 9964895 was 9964895, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 20, 2018 at 8:35:35 AM

bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 1.1 KB
Line 
1/*
2 *  cpuinit.c - this file contains functions for initializing the CPU
3 *
4 *  Written by Jay Monkman (jmonkman@frasca.com)
5 */
6
7#include <bsp.h>
8
9/* Macros for handling all the MMU SPRs */
10#define PUT_IC_CST(r)   __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r))
11#define GET_IC_CST(r)   __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r))
12#define PUT_DC_CST(r)   __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r))
13#define GET_DC_CST(r)   __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r))
14
15void cpu_init(void)
16{
17  /* BRGCLK is VCO_OUT/4 */
18/*
19  m8260.sccr = 0;
20*/
21
22#if 0
23  register unsigned long t1, t2;
24
25  /* Let's clear MSR[IR] and MSR[DR] */
26  t2 = PPC_MSR_IR | PPC_MSR_DR;
27  __asm__ volatile (
28    "mfmsr    %0\n"
29    "andc     %0, %0, %1\n"
30    "mtmsr    %0\n" :"=r"(t1), "=r"(t2):
31    "1"(t2));
32
33  t1 = M8xx_CACHE_CMD_UNLOCK;
34  /*  PUT_DC_CST(t1); */
35  PUT_IC_CST(t1);
36
37  t1 = M8xx_CACHE_CMD_INVALIDATE;
38  /*  PUT_DC_CST(t1); */
39  PUT_IC_CST(t1);
40
41  t1 = M8xx_CACHE_CMD_ENABLE;
42  PUT_IC_CST(t1);
43
44  t1 = M8xx_CACHE_CMD_SFWT;
45  /*  PUT_DC_CST(t1); */
46  t1 = M8xx_CACHE_CMD_ENABLE;
47  /*  PUT_DC_CST(t1);*/
48#endif
49}
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