1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx_asm |
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5 | * |
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6 | * @brief Boot and system start code. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <bspopts.h> |
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24 | #include <bsp/linker-symbols.h> |
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25 | #include <libcpu/powerpc-utility.h> |
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26 | |
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27 | #if MPC55XX_CHIP_FAMILY != 551 |
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28 | #define HAS_SPE |
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29 | #endif |
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30 | |
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31 | #if MPC55XX_CHIP_FAMILY == 564 |
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32 | #define INIT_REGISTERS_FOR_LSM |
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33 | #endif |
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34 | |
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35 | #ifdef HAS_SPE |
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36 | #define ZERO_GPR(reg) evxor reg, reg, reg |
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37 | #else |
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38 | #define ZERO_GPR(reg) xor reg, reg, reg |
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39 | #endif |
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40 | |
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41 | .extern __eabi |
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42 | .extern boot_card |
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43 | .extern bsp_ram_start |
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44 | .extern mpc55xx_start_config_mmu_early |
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45 | .extern mpc55xx_start_config_mmu_early_count |
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46 | .extern mpc55xx_start_early |
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47 | |
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48 | .globl _start |
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49 | .globl mpc55xx_start_load_section |
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50 | .globl mpc55xx_start_mmu_apply_config |
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51 | |
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52 | #ifdef MPC55XX_BOOTFLAGS |
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53 | .globl mpc55xx_bootflag_0 |
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54 | .globl mpc55xx_bootflag_1 |
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55 | #endif |
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56 | |
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57 | .section ".bsp_start_text", "ax" |
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58 | |
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59 | /* BAM: RCHW */ |
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60 | .int 0x005a0000 |
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61 | |
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62 | /* BAM: Address of start instruction */ |
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63 | .int _start |
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64 | |
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65 | #ifdef MPC55XX_BOOTFLAGS |
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66 | /* |
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67 | * We skip over the next two boot flag words to the next 64-bit |
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68 | * aligned start address. It is 64-bit aligned to play well with |
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69 | * FLASH programming. These boot flags can be set by debuggers |
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70 | * and emulators to customize boot. Currently bit0 of |
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71 | * bootflag_0 means to "skip setting up the MMU", allowing |
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72 | * external MMU setup in a debugger before branching to 0x10. |
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73 | * This can be used e.g., to map FLASH into RAM. |
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74 | */ |
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75 | mpc55xx_bootflag_0: |
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76 | .int 0xffffffff |
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77 | mpc55xx_bootflag_1: |
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78 | .int 0xffffffff |
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79 | #endif |
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80 | |
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81 | _start: |
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82 | |
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83 | #ifdef MPC55XX_ENABLE_START_PROLOGUE |
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84 | bl mpc55xx_start_prologue |
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85 | #endif |
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86 | |
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87 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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88 | |
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89 | /* Enable SPE */ |
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90 | #ifdef HAS_SPE |
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91 | mfmsr r3 |
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92 | oris r3, r3, MSR_SPE >> 16 |
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93 | mtmsr r3 |
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94 | isync |
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95 | #endif |
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96 | |
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97 | /* |
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98 | * Initialization of core registers according to "e200z4 Power |
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99 | * Architecture Core Reference Manual" section 2.6 "Reset Settings" |
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100 | * table 2-16 "Reset Settings of e200 Resources". This is necessary |
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101 | * for lock step mode (LSM). |
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102 | */ |
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103 | ZERO_GPR(r0) |
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104 | #ifdef INIT_REGISTERS_FOR_LSM |
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105 | ZERO_GPR(r1) |
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106 | ZERO_GPR(r2) |
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107 | ZERO_GPR(r4) |
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108 | ZERO_GPR(r5) |
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109 | ZERO_GPR(r6) |
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110 | ZERO_GPR(r7) |
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111 | ZERO_GPR(r8) |
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112 | ZERO_GPR(r9) |
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113 | ZERO_GPR(r10) |
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114 | ZERO_GPR(r11) |
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115 | ZERO_GPR(r12) |
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116 | ZERO_GPR(r13) |
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117 | ZERO_GPR(r14) |
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118 | ZERO_GPR(r15) |
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119 | ZERO_GPR(r16) |
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120 | ZERO_GPR(r17) |
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121 | ZERO_GPR(r18) |
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122 | ZERO_GPR(r19) |
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123 | ZERO_GPR(r20) |
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124 | ZERO_GPR(r21) |
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125 | ZERO_GPR(r22) |
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126 | ZERO_GPR(r23) |
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127 | ZERO_GPR(r24) |
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128 | ZERO_GPR(r25) |
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129 | ZERO_GPR(r26) |
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130 | ZERO_GPR(r27) |
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131 | ZERO_GPR(r28) |
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132 | ZERO_GPR(r29) |
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133 | ZERO_GPR(r30) |
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134 | ZERO_GPR(r31) |
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135 | mtcrf 0xff, r0 |
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136 | mtcsrr0 r0 |
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137 | mtcsrr1 r0 |
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138 | mtctr r0 |
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139 | mtspr FSL_EIS_DBCNT, r0 |
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140 | mtspr DEAR_BOOKE, r0 |
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141 | mtdec r0 |
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142 | mtspr BOOKE_DECAR, r0 |
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143 | mtspr FSL_EIS_DSRR0, r0 |
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144 | mtspr FSL_EIS_DSRR1, r0 |
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145 | mtspr BOOKE_DVC1, r0 |
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146 | mtspr BOOKE_DVC2, r0 |
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147 | mtspr BOOKE_IVPR, r0 |
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148 | mtlr r0 |
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149 | mtspr FSL_EIS_MCAR, r0 |
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150 | mtmcsrr0 r0 |
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151 | mtmcsrr1 r0 |
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152 | mtspr SPRG0, r0 |
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153 | mtspr SPRG1, r0 |
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154 | mtspr SPRG2, r0 |
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155 | mtspr SPRG3, r0 |
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156 | mtspr SPRG4, r0 |
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157 | mtspr SPRG5, r0 |
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158 | mtspr SPRG6, r0 |
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159 | mtspr SPRG7, r0 |
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160 | mtspr FSL_EIS_SPRG8, r0 |
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161 | mtspr FSL_EIS_SPRG9, r0 |
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162 | mtsrr0 r0 |
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163 | mtsrr1 r0 |
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164 | mtspr USPRG0, r0 |
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165 | #ifdef HAS_SPE |
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166 | evmra r0, r0 |
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167 | #endif |
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168 | #endif /* INIT_REGISTERS_FOR_LSM */ |
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169 | mtspr TBWL, r0 |
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170 | mtspr TBWU, r0 |
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171 | |
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172 | /* Enable time base */ |
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173 | mfspr r3, HID0 |
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174 | ori r3, r3, 0x4000 |
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175 | mtspr HID0, r3 |
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176 | |
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177 | /* |
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178 | * Enable branch prediction. |
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179 | * |
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180 | * Errata e4396: e200z7: Erroneous Address Fetch |
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181 | * |
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182 | * The propose workaround does not work. |
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183 | */ |
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184 | #if MPC55XX_CHIP_FAMILY != 567 |
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185 | LWI r3, FSL_EIS_BUCSR_BBFI | FSL_EIS_BUCSR_BALLOC_ALL | FSL_EIS_BUCSR_BPRED_NOT_TAKEN | FSL_EIS_BUCSR_BPEN |
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186 | mtspr FSL_EIS_BUCSR, r3 |
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187 | #endif |
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188 | |
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189 | #endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */ |
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190 | |
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191 | /* MMU early initialization */ |
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192 | LA r3, mpc55xx_start_config_mmu_early |
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193 | LW r4, mpc55xx_start_config_mmu_early_count |
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194 | bl mpc55xx_start_mmu_apply_config |
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195 | |
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196 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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197 | |
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198 | /* Initialize intermediate stack (ECC) */ |
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199 | |
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200 | LA r3, bsp_ram_start |
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201 | addi r4, r3, MPC55XX_EARLY_STACK_SIZE |
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202 | |
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203 | zero_intermediate_stack_loop: |
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204 | |
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205 | #ifdef HAS_SPE |
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206 | evstdd r0, 0(r3) |
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207 | evstdd r0, 8(r3) |
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208 | evstdd r0, 16(r3) |
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209 | evstdd r0, 24(r3) |
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210 | #else |
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211 | stw r0, 0(r3) |
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212 | stw r0, 4(r3) |
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213 | stw r0, 8(r3) |
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214 | stw r0, 12(r3) |
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215 | stw r0, 16(r3) |
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216 | stw r0, 20(r3) |
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217 | stw r0, 24(r3) |
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218 | stw r0, 28(r3) |
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219 | #endif |
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220 | addi r3, r3, 32 |
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221 | cmpw cr7, r3, r4 |
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222 | bne cr7, zero_intermediate_stack_loop |
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223 | subi r1, r3, 16 |
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224 | |
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225 | #endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */ |
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226 | |
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227 | /* Next steps in C */ |
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228 | bl mpc55xx_start_early |
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229 | |
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230 | /* Initialize start stack */ |
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231 | LA r1, _ISR_Stack_area_end |
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232 | subi r1, r1, 16 |
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233 | li r0, 0 |
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234 | stw r0, 0(r1) |
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235 | |
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236 | /* |
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237 | * Load sections. This must be performed after the stack switch |
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238 | * because it may overwrite the initial stack. |
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239 | */ |
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240 | LA r3, bsp_section_fast_text_begin |
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241 | LA r4, bsp_section_fast_text_load_begin |
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242 | LA r5, bsp_section_fast_text_size |
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243 | bl mpc55xx_start_load_section |
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244 | LA r3, bsp_section_fast_data_begin |
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245 | LA r4, bsp_section_fast_data_load_begin |
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246 | LA r5, bsp_section_fast_data_size |
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247 | bl mpc55xx_start_load_section |
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248 | LA r3, bsp_section_data_begin |
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249 | LA r4, bsp_section_data_load_begin |
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250 | LA r5, bsp_section_data_size |
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251 | bl mpc55xx_start_load_section |
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252 | |
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253 | /* Set up EABI and SYSV environment */ |
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254 | bl __eabi |
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255 | |
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256 | /* Clear command line */ |
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257 | li r3, 0 |
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258 | |
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259 | /* Start RTEMS */ |
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260 | bl boot_card |
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261 | |
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262 | /* Spin around */ |
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263 | twiddle: |
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264 | |
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265 | b twiddle |
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266 | |
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267 | mpc55xx_start_mmu_apply_config: |
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268 | |
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269 | cmpwi cr7, r4, r0 |
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270 | beqlr cr7 |
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271 | mtctr r4 |
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272 | |
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273 | mmu_init_loop: |
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274 | |
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275 | lwz r4, 0(r3) |
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276 | lwz r5, 4(r3) |
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277 | lwz r6, 8(r3) |
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278 | lwz r7, 12(r3) |
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279 | mtspr FSL_EIS_MAS0, r4 |
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280 | mtspr FSL_EIS_MAS1, r5 |
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281 | mtspr FSL_EIS_MAS2, r6 |
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282 | mtspr FSL_EIS_MAS3, r7 |
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283 | tlbwe |
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284 | addi r3, r3, 16 |
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285 | bdnz mmu_init_loop |
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286 | blr |
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287 | |
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288 | mpc55xx_start_load_section: |
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289 | cmpw cr7, r3, r4 |
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290 | beqlr cr7 |
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291 | b memcpy |
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