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Last change on this file was bcef89f2, checked in by Sebastian Huber <sebastian.huber@…>, on 05/19/23 at 06:18:25

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1	/* SPDX-License-Identifier: BSD-2-Clause */
2
3	/**
4	* @file
5	*
6	* @ingroup mpc55xx_asm
7	*
8	* @brief Boot and system start code.
9	*/
10
11	/*
12	* Copyright (C) 2008, 2012 embedded brains GmbH & Co. KG
13	*
14	* Redistribution and use in source and binary forms, with or without
15	* modification, are permitted provided that the following conditions
16	* are met:
17	* 1. Redistributions of source code must retain the above copyright
18	* notice, this list of conditions and the following disclaimer.
19	* 2. Redistributions in binary form must reproduce the above copyright
20	* notice, this list of conditions and the following disclaimer in the
21	* documentation and/or other materials provided with the distribution.
22	*
23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33	* POSSIBILITY OF SUCH DAMAGE.
34	*/
35
36	#include <bspopts.h>
37	#include <bsp/linker-symbols.h>
38	#include <libcpu/powerpc-utility.h>
39
40	#if MPC55XX_CHIP_FAMILY != 551
41	#define HAS_SPE
42	#endif
43
44	#if MPC55XX_CHIP_FAMILY == 564
45	#define INIT_REGISTERS_FOR_LSM
46	#endif
47
48	#ifdef HAS_SPE
49	#define ZERO_GPR(reg) evxor reg, reg, reg
50	#else
51	#define ZERO_GPR(reg) xor reg, reg, reg
52	#endif
53
54	.extern __eabi
55	.extern boot_card
56	.extern bsp_ram_start
57	.extern mpc55xx_start_config_mmu_early
58	.extern mpc55xx_start_config_mmu_early_count
59	.extern mpc55xx_start_early
60
61	.globl _start
62	.globl mpc55xx_start_load_section
63	.globl mpc55xx_start_mmu_apply_config
64
65	#ifdef MPC55XX_BOOTFLAGS
66	.globl mpc55xx_bootflag_0
67	.globl mpc55xx_bootflag_1
68	#endif
69
70	.section ".bsp_start_text", "ax"
71
72	/* BAM: RCHW */
73	.int 0x005a0000
74
75	/* BAM: Address of start instruction */
76	.int _start
77
78	#ifdef MPC55XX_BOOTFLAGS
79	/*
80	* We skip over the next two boot flag words to the next 64-bit
81	* aligned start address. It is 64-bit aligned to play well with
82	* FLASH programming. These boot flags can be set by debuggers
83	* and emulators to customize boot. Currently bit0 of
84	* bootflag_0 means to "skip setting up the MMU", allowing
85	* external MMU setup in a debugger before branching to 0x10.
86	* This can be used e.g., to map FLASH into RAM.
87	*/
88	mpc55xx_bootflag_0:
89	.int 0xffffffff
90	mpc55xx_bootflag_1:
91	.int 0xffffffff
92	#endif
93
94	_start:
95
96	#ifdef MPC55XX_ENABLE_START_PROLOGUE
97	bl mpc55xx_start_prologue
98	#endif
99
100	#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
101
102	/* Enable SPE */
103	#ifdef HAS_SPE
104	mfmsr r3
105	oris r3, r3, MSR_SPE >> 16
106	mtmsr r3
107	isync
108	#endif
109
110	/*
111	* Initialization of core registers according to "e200z4 Power
112	* Architecture Core Reference Manual" section 2.6 "Reset Settings"
113	* table 2-16 "Reset Settings of e200 Resources". This is necessary
114	* for lock step mode (LSM).
115	*/
116	ZERO_GPR(r0)
117	#ifdef INIT_REGISTERS_FOR_LSM
118	ZERO_GPR(r1)
119	ZERO_GPR(r2)
120	ZERO_GPR(r4)
121	ZERO_GPR(r5)
122	ZERO_GPR(r6)
123	ZERO_GPR(r7)
124	ZERO_GPR(r8)
125	ZERO_GPR(r9)
126	ZERO_GPR(r10)
127	ZERO_GPR(r11)
128	ZERO_GPR(r12)
129	ZERO_GPR(r13)
130	ZERO_GPR(r14)
131	ZERO_GPR(r15)
132	ZERO_GPR(r16)
133	ZERO_GPR(r17)
134	ZERO_GPR(r18)
135	ZERO_GPR(r19)
136	ZERO_GPR(r20)
137	ZERO_GPR(r21)
138	ZERO_GPR(r22)
139	ZERO_GPR(r23)
140	ZERO_GPR(r24)
141	ZERO_GPR(r25)
142	ZERO_GPR(r26)
143	ZERO_GPR(r27)
144	ZERO_GPR(r28)
145	ZERO_GPR(r29)
146	ZERO_GPR(r30)
147	ZERO_GPR(r31)
148	mtcrf 0xff, r0
149	mtcsrr0 r0
150	mtcsrr1 r0
151	mtctr r0
152	mtspr FSL_EIS_DBCNT, r0
153	mtspr DEAR_BOOKE, r0
154	mtdec r0
155	mtspr BOOKE_DECAR, r0
156	mtspr FSL_EIS_DSRR0, r0
157	mtspr FSL_EIS_DSRR1, r0
158	mtspr BOOKE_DVC1, r0
159	mtspr BOOKE_DVC2, r0
160	mtspr BOOKE_IVPR, r0
161	mtlr r0
162	mtspr FSL_EIS_MCAR, r0
163	mtmcsrr0 r0
164	mtmcsrr1 r0
165	mtspr SPRG0, r0
166	mtspr SPRG1, r0
167	mtspr SPRG2, r0
168	mtspr SPRG3, r0
169	mtspr SPRG4, r0
170	mtspr SPRG5, r0
171	mtspr SPRG6, r0
172	mtspr SPRG7, r0
173	mtspr FSL_EIS_SPRG8, r0
174	mtspr FSL_EIS_SPRG9, r0
175	mtsrr0 r0
176	mtsrr1 r0
177	mtspr USPRG0, r0
178	#ifdef HAS_SPE
179	evmra r0, r0
180	#endif
181	#endif /* INIT_REGISTERS_FOR_LSM */
182	mtspr TBWL, r0
183	mtspr TBWU, r0
184
185	/* Enable time base */
186	mfspr r3, HID0
187	ori r3, r3, 0x4000
188	mtspr HID0, r3
189
190	/*
191	* Enable branch prediction.
192	*
193	* Errata e4396: e200z7: Erroneous Address Fetch
194	*
195	* The propose workaround does not work.
196	*/
197	#if MPC55XX_CHIP_FAMILY != 567
198	LWI r3, FSL_EIS_BUCSR_BBFI \| FSL_EIS_BUCSR_BALLOC_ALL \| FSL_EIS_BUCSR_BPRED_NOT_TAKEN \| FSL_EIS_BUCSR_BPEN
199	mtspr FSL_EIS_BUCSR, r3
200	#endif
201
202	#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
203
204	/* MMU early initialization */
205	LA r3, mpc55xx_start_config_mmu_early
206	LW r4, mpc55xx_start_config_mmu_early_count
207	bl mpc55xx_start_mmu_apply_config
208
209	#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
210
211	/* Initialize intermediate stack (ECC) */
212
213	LA r3, bsp_ram_start
214	addi r4, r3, MPC55XX_EARLY_STACK_SIZE
215
216	zero_intermediate_stack_loop:
217
218	#ifdef HAS_SPE
219	evstdd r0, 0(r3)
220	evstdd r0, 8(r3)
221	evstdd r0, 16(r3)
222	evstdd r0, 24(r3)
223	#else
224	stw r0, 0(r3)
225	stw r0, 4(r3)
226	stw r0, 8(r3)
227	stw r0, 12(r3)
228	stw r0, 16(r3)
229	stw r0, 20(r3)
230	stw r0, 24(r3)
231	stw r0, 28(r3)
232	#endif
233	addi r3, r3, 32
234	cmpw cr7, r3, r4
235	bne cr7, zero_intermediate_stack_loop
236	subi r1, r3, 16
237
238	#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
239
240	/* Next steps in C */
241	bl mpc55xx_start_early
242
243	/* Initialize start stack */
244	LA r1, _ISR_Stack_area_end
245	subi r1, r1, 16
246	li r0, 0
247	stw r0, 0(r1)
248
249	/*
250	* Load sections. This must be performed after the stack switch
251	* because it may overwrite the initial stack.
252	*/
253	LA r3, bsp_section_fast_text_begin
254	LA r4, bsp_section_fast_text_load_begin
255	LA r5, bsp_section_fast_text_size
256	bl mpc55xx_start_load_section
257	LA r3, bsp_section_fast_data_begin
258	LA r4, bsp_section_fast_data_load_begin
259	LA r5, bsp_section_fast_data_size
260	bl mpc55xx_start_load_section
261	LA r3, bsp_section_data_begin
262	LA r4, bsp_section_data_load_begin
263	LA r5, bsp_section_data_size
264	bl mpc55xx_start_load_section
265
266	/* Set up EABI and SYSV environment */
267	bl __eabi
268
269	/* Clear command line */
270	li r3, 0
271
272	/* Start RTEMS */
273	bl boot_card
274
275	/* Spin around */
276	twiddle:
277
278	b twiddle
279
280	mpc55xx_start_mmu_apply_config:
281
282	cmpwi cr7, r4, r0
283	beqlr cr7
284	mtctr r4
285
286	mmu_init_loop:
287
288	lwz r4, 0(r3)
289	lwz r5, 4(r3)
290	lwz r6, 8(r3)
291	lwz r7, 12(r3)
292	mtspr FSL_EIS_MAS0, r4
293	mtspr FSL_EIS_MAS1, r5
294	mtspr FSL_EIS_MAS2, r6
295	mtspr FSL_EIS_MAS3, r7
296	tlbwe
297	addi r3, r3, 16
298	bdnz mmu_init_loop
299	blr
300
301	mpc55xx_start_load_section:
302	cmpw cr7, r3, r4
303	beqlr cr7
304	b memcpy

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