1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx_asm |
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5 | * |
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6 | * @brief Flash configuration. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2015 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <libcpu/powerpc-utility.h> |
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24 | #include <mpc55xx/reg-defs.h> |
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25 | |
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26 | .section ".bsp_start_text", "ax" |
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27 | |
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28 | #if MPC55XX_CHIP_FAMILY == 551 |
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29 | |
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30 | /* MPC5510 Microcontroller Family Data Sheet, Rev. 3, Table 16, Num 7 */ |
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31 | .equ FLASH_CLOCK_0, 25000000 |
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32 | .equ FLASH_CLOCK_1, 50000000 |
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33 | .equ FLASH_CLOCK_2, 80000000 |
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34 | .equ FLASH_CLOCK_3, FLASH_CLOCK_2 |
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35 | .equ FLASH_SETTINGS_0, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_0 | FLASH_BUICR_RWSC_0 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_1 | FLASH_BUICR_IPFEN_1 | FLASH_BUICR_PFLIM_2 | FLASH_BUICR_BFEN |
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36 | .equ FLASH_SETTINGS_1, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_1 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_1 | FLASH_BUICR_IPFEN_1 | FLASH_BUICR_PFLIM_2 | FLASH_BUICR_BFEN |
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37 | .equ FLASH_SETTINGS_2, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_2 | FLASH_BUICR_RWSC_2 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_1 | FLASH_BUICR_IPFEN_1 | FLASH_BUICR_PFLIM_2 | FLASH_BUICR_BFEN |
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38 | .equ FLASH_SETTINGS_3, FLASH_SETTINGS_2 |
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39 | |
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40 | #else |
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41 | |
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42 | /* Optimized flash configurations (Table 13-15 [MPC5567 Microcontroller Reference Manual]) */ |
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43 | .equ FLASH_CLOCK_0, 82000000 |
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44 | .equ FLASH_CLOCK_1, 102000000 |
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45 | .equ FLASH_CLOCK_2, 132000000 |
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46 | .equ FLASH_CLOCK_3, 264000000 |
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47 | .equ FLASH_SETTINGS_0, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_1 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN |
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48 | .equ FLASH_SETTINGS_1, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_2 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN |
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49 | .equ FLASH_SETTINGS_2, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_2 | FLASH_BUICR_RWSC_3 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN |
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50 | .equ FLASH_SETTINGS_3, 0x01716B15 |
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51 | |
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52 | #endif |
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53 | |
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54 | /** |
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55 | * @fn void mpc55xx_start_flash() |
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56 | * @brief Optimized flash configuration. |
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57 | * @warning Code will be copied and executed on the stack. |
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58 | */ |
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59 | GLOBAL_FUNCTION mpc55xx_start_flash |
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60 | #if !defined(MPC55XX_NEEDS_LOW_LEVEL_INIT) \ |
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61 | || MPC55XX_CHIP_FAMILY == 564 \ |
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62 | || MPC55XX_CHIP_FAMILY == 566 |
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63 | blr |
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64 | #else |
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65 | .equ stack_size, 20 |
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66 | .equ lr_offset, 28 |
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67 | |
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68 | /* Reserve stack frame */ |
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69 | stwu r1, -stack_size(r1) |
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70 | mflr r0 |
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71 | stw r0, lr_offset(r1) |
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72 | |
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73 | /* Flash settings dependent on system clock */ |
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74 | bl mpc55xx_get_system_clock |
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75 | LWI r4, FLASH_CLOCK_0 |
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76 | cmpw r3, r4 |
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77 | ble clock_0 |
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78 | LWI r4, FLASH_CLOCK_1 |
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79 | cmpw r3, r4 |
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80 | ble clock_1 |
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81 | LWI r4, FLASH_CLOCK_2 |
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82 | cmpw r3, r4 |
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83 | ble clock_2 |
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84 | LWI r4, FLASH_CLOCK_3 |
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85 | cmpw r3, r4 |
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86 | ble clock_3 |
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87 | |
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88 | /* |
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89 | * In case we don't have the right flash settings for the system clock |
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90 | * value, then rely on the BAM settings. |
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91 | */ |
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92 | blr |
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93 | |
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94 | clock_0: |
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95 | LWI r3, FLASH_SETTINGS_0 |
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96 | b settings_done |
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97 | clock_1: |
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98 | LWI r3, FLASH_SETTINGS_1 |
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99 | b settings_done |
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100 | clock_2: |
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101 | LWI r3, FLASH_SETTINGS_2 |
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102 | b settings_done |
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103 | clock_3: |
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104 | LWI r3, FLASH_SETTINGS_3 |
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105 | b settings_done |
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106 | settings_done: |
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107 | |
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108 | /* Copy store code on the stack */ |
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109 | LA r4, store_start |
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110 | lwz r6, 0(r4) |
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111 | lwz r7, 4(r4) |
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112 | lwz r8, 8(r4) |
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113 | stw r6, 8(r1) |
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114 | stw r7, 12(r1) |
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115 | stw r8, 16(r1) |
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116 | |
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117 | /* Execute store code */ |
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118 | LA r4, FLASH_BIUCR |
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119 | addi r5, r1, 8 |
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120 | mtctr r5 |
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121 | bctrl |
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122 | |
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123 | /* Return */ |
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124 | lwz r0, lr_offset(r1) |
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125 | addi r1, r1, stack_size |
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126 | mtlr r0 |
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127 | blr |
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128 | |
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129 | /* |
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130 | * Store flash settings |
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131 | */ |
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132 | |
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133 | store_start: |
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134 | |
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135 | stw r3, 0(r4) |
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136 | isync |
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137 | blr |
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138 | |
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139 | #endif |
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