1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @ingroup RTEMSBSPsPowerPCMPC55XX |
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7 | * |
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8 | * @brief Early initialization code. |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Copyright (C) 2008, 2012 embedded brains GmbH & Co. KG |
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13 | * |
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14 | * Redistribution and use in source and binary forms, with or without |
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15 | * modification, are permitted provided that the following conditions |
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16 | * are met: |
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17 | * 1. Redistributions of source code must retain the above copyright |
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18 | * notice, this list of conditions and the following disclaimer. |
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19 | * 2. Redistributions in binary form must reproduce the above copyright |
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20 | * notice, this list of conditions and the following disclaimer in the |
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21 | * documentation and/or other materials provided with the distribution. |
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22 | * |
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23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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24 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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27 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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28 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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29 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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30 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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31 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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32 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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33 | * POSSIBILITY OF SUCH DAMAGE. |
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34 | */ |
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35 | |
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36 | #include <bsp/mpc55xx-config.h> |
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37 | #include <bsp/linker-symbols.h> |
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38 | |
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39 | /* This function is defined in start.S */ |
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40 | BSP_START_TEXT_SECTION void mpc55xx_start_load_section( |
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41 | void *dst, |
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42 | const void *src, |
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43 | size_t n |
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44 | ); |
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45 | |
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46 | static BSP_START_TEXT_SECTION void mpc55xx_start_mmu(void) |
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47 | { |
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48 | #ifdef MPC55XX_BOOTFLAGS |
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49 | /* If the low bit of bootflag 0 is clear don't change the MMU. */ |
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50 | bool do_mmu_config = (mpc55xx_bootflag_0 [0] & 1) != 0; |
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51 | #else |
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52 | bool do_mmu_config = true; |
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53 | #endif |
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54 | |
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55 | if (do_mmu_config) { |
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56 | mpc55xx_start_mmu_apply_config( |
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57 | &mpc55xx_start_config_mmu [0], |
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58 | mpc55xx_start_config_mmu_count [0] |
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59 | ); |
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60 | } |
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61 | } |
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62 | |
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63 | static BSP_START_TEXT_SECTION void mpc55xx_start_internal_ram(void) |
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64 | { |
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65 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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66 | /* Initialize internal SRAM to zero (ECC) */ |
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67 | bsp_start_zero( |
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68 | (char *) bsp_ram_start + MPC55XX_EARLY_STACK_SIZE, |
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69 | (size_t) bsp_ram_size - MPC55XX_EARLY_STACK_SIZE |
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70 | ); |
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71 | #ifdef MPC55XX_HAS_SECOND_INTERNAL_RAM_AREA |
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72 | bsp_start_zero(&bsp_ram_1_start [0], (size_t) bsp_ram_1_size); |
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73 | #endif |
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74 | #else |
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75 | bsp_start_zero( |
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76 | bsp_section_sbss_begin, |
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77 | (size_t) bsp_section_sbss_size |
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78 | ); |
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79 | bsp_start_zero( |
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80 | bsp_section_bss_begin, |
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81 | (size_t) bsp_section_bss_size |
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82 | ); |
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83 | #endif |
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84 | } |
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85 | |
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86 | static BSP_START_TEXT_SECTION void mpc55xx_start_load_nocache_section(void) |
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87 | { |
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88 | mpc55xx_start_load_section( |
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89 | bsp_section_nocache_begin, |
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90 | bsp_section_nocache_load_begin, |
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91 | (size_t) bsp_section_nocache_size |
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92 | ); |
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93 | rtems_cache_flush_multiple_data_lines( |
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94 | bsp_section_nocache_begin, |
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95 | (size_t) bsp_section_nocache_size |
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96 | ); |
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97 | } |
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98 | |
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99 | static BSP_START_TEXT_SECTION void mpc55xx_start_mode_change(void) |
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100 | { |
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101 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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102 | #ifdef MPC55XX_HAS_MODE_CONTROL |
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103 | uint32_t mctl_key1 = 0x5af0; |
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104 | uint32_t mctl_key2 = 0xa50f; |
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105 | int i = 0; |
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106 | |
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107 | /* Clear any pending RGM status */ |
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108 | RGM.FES.R = 0xffff; |
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109 | RGM.DES.R = 0xffff; |
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110 | |
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111 | /* Make sure XOSC and PLLs are on in RUN0 state */ |
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112 | ME.DRUN_MC.R = 0x001f0074; |
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113 | ME.RUN_MC [0].R = 0x001f0074; |
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114 | |
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115 | /* |
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116 | * Make sure all peripherals are active in DRUN and RUN0 state. |
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117 | * |
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118 | * FIXME: This might be optimized to reduce power consumtion. |
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119 | */ |
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120 | for (i = 0; i < 8; ++i) { |
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121 | ME_RUN_PC_32B_tag run_pc = { .R = ME.RUN_PC [i].R }; |
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122 | |
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123 | run_pc.B.DRUN = 1; |
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124 | run_pc.B.RUN0 = 1; |
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125 | |
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126 | ME.RUN_PC [i].R = run_pc.R; |
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127 | } |
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128 | |
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129 | /* Switch to RUN0 state */ |
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130 | ME.MCTL.R = 0x40000000 | mctl_key1; |
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131 | ME.MCTL.R = 0x40000000 | mctl_key2; |
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132 | |
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133 | while (ME.GS.B.S_MTRANS) { |
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134 | /* Wait for mode switch to be completed */ |
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135 | } |
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136 | #endif |
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137 | #endif |
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138 | } |
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139 | |
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140 | static BSP_START_TEXT_SECTION void mpc55xx_start_siu(void) |
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141 | { |
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142 | size_t i = 0; |
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143 | |
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144 | for (i = 0; i < mpc55xx_start_config_siu_pcr_count [0]; ++i) { |
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145 | const mpc55xx_siu_pcr_config *e = &mpc55xx_start_config_siu_pcr [i]; |
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146 | int j = e->index; |
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147 | int n = j + e->count; |
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148 | uint8_t gpdo = e->output; |
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149 | uint16_t pcr = e->pcr.R; |
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150 | |
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151 | while (j < n) { |
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152 | SIU.GPDO [j].R = gpdo; |
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153 | SIU.PCR [j].R = pcr; |
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154 | ++j; |
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155 | } |
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156 | } |
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157 | } |
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158 | |
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159 | static BSP_START_TEXT_SECTION void mpc55xx_start_ebi_chip_select(void) |
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160 | { |
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161 | #ifdef MPC55XX_HAS_EBI |
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162 | size_t i = 0; |
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163 | |
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164 | for (i = 0; i < mpc55xx_start_config_ebi_cs_count [0]; ++i) { |
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165 | EBI.CS [i] = mpc55xx_start_config_ebi_cs [i]; |
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166 | } |
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167 | |
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168 | for (i = 0; i < mpc55xx_start_config_ebi_cal_cs_count [0]; ++i) { |
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169 | EBI.CAL_CS [i] = mpc55xx_start_config_ebi_cal_cs [i]; |
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170 | } |
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171 | #endif |
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172 | } |
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173 | |
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174 | static BSP_START_TEXT_SECTION void mpc55xx_start_ebi(void) |
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175 | { |
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176 | #ifdef MPC55XX_HAS_EBI |
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177 | size_t i = 0; |
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178 | |
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179 | for (i = 0; i < mpc55xx_start_config_ebi_count [0]; ++i) { |
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180 | SIU.ECCR.B.EBDF = mpc55xx_start_config_ebi [i].siu_eccr_ebdf; |
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181 | EBI.MCR.R = mpc55xx_start_config_ebi [i].ebi_mcr.R; |
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182 | } |
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183 | #endif |
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184 | } |
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185 | |
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186 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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187 | static BSP_START_TEXT_SECTION bool |
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188 | mpc55xx_start_is_in_internal_ram(const void *addr) |
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189 | { |
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190 | return (size_t) addr - (size_t) bsp_ram_start < (size_t) bsp_ram_size; |
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191 | } |
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192 | #endif |
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193 | |
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194 | static BSP_START_TEXT_SECTION void mpc55xx_start_clear_bss(void) |
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195 | { |
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196 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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197 | if (!mpc55xx_start_is_in_internal_ram(bsp_section_sbss_begin)) { |
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198 | bsp_start_zero( |
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199 | bsp_section_sbss_begin, |
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200 | (size_t) bsp_section_sbss_size |
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201 | ); |
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202 | } |
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203 | |
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204 | if (!mpc55xx_start_is_in_internal_ram(bsp_section_bss_begin)) { |
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205 | bsp_start_zero( |
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206 | bsp_section_bss_begin, |
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207 | (size_t) bsp_section_bss_size |
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208 | ); |
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209 | } |
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210 | #endif |
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211 | } |
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212 | |
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213 | BSP_START_TEXT_SECTION void mpc55xx_start_early(void) |
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214 | { |
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215 | mpc55xx_start_watchdog(); |
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216 | mpc55xx_start_clock(); |
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217 | mpc55xx_start_flash(); |
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218 | #if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED) |
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219 | mpc55xx_start_cache(); |
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220 | #endif |
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221 | mpc55xx_start_internal_ram(); |
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222 | mpc55xx_start_load_nocache_section(); |
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223 | mpc55xx_start_mmu(); |
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224 | mpc55xx_start_mode_change(); |
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225 | mpc55xx_start_siu(); |
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226 | mpc55xx_start_ebi_chip_select(); |
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227 | mpc55xx_start_ebi(); |
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228 | mpc55xx_start_clear_bss(); |
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229 | } |
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