source: rtems/bsps/powerpc/mpc55xxevb/start/start-config-clock.c @ e560ee85

Last change on this file since e560ee85 was e560ee85, checked in by Joel Sherrill <joel@…>, on 03/01/22 at 21:38:55

bsps/powerpc/: Scripted embedded brains header file clean up

Updates #4625.

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup RTEMSBSPsPowerPCMPC55XX
5 *
6 * @brief Clock and FMPLL configuration.
7 */
8
9/*
10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 * http://www.rtems.org/license/LICENSE.
15 */
16
17#include <bsp/mpc55xx-config.h>
18
19const mpc55xx_clock_config mpc55xx_start_config_clock [1] = { {
20  #ifdef MPC55XX_HAS_FMPLL
21    .syncr_tmp = {
22      .B = {
23        .PREDIV = MPC55XX_FMPLL_PREDIV - 1,
24        .MFD = MPC55XX_FMPLL_MFD,
25        .RFD = 2,
26        .LOCEN = 1
27      }
28    },
29    .syncr_final = {
30      .B = {
31        .PREDIV = MPC55XX_FMPLL_PREDIV - 1,
32        .MFD = MPC55XX_FMPLL_MFD,
33        .RFD = 0,
34        .LOCEN = 1,
35        .LOLIRQ = 1,
36        .LOCIRQ = 1
37      }
38    }
39  #endif
40  #ifdef MPC55XX_HAS_FMPLL_ENHANCED
41    #define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1)
42    #define EMFD_VAL    (MPC55XX_FMPLL_MFD-16)
43    #define VCO_CLK_REF (MPC55XX_REFERENCE_CLOCK/(EPREDIV_VAL+1))
44    #define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16))
45    #define ERFD_VAL \
46      (((VCO_CLK_OUT + MPC55XX_SYSTEM_CLOCK - 1) / MPC55XX_SYSTEM_CLOCK)-1)
47
48    .esyncr2_tmp = {
49      .B = {
50        .LOCEN = 0,
51        .LOLRE = 0,
52        .LOCRE = 0,
53        .LOLIRQ = 0,
54        .LOCIRQ = 0,
55        .ERATE = 0,
56        .EDEPTH = 0,
57        .ERFD = ERFD_VAL + 2 /* reduce output clock during init */
58      }
59    },
60    .esyncr2_final = {
61      .B = {
62        .LOCEN = 0,
63        .LOLRE = 0,
64        .LOCRE = 0,
65        .LOLIRQ = 0,
66        .LOCIRQ = 0,
67        .ERATE = 0,
68        #if MPC55XX_CHIP_FAMILY  == 567
69          .CLKCFG_DIS = 1,
70        #endif
71        .EDEPTH = 0,
72        .ERFD = ERFD_VAL /* nominal output clock after init */
73      }
74    },
75    .esyncr1_final = {
76      .B = {
77        .CLKCFG = MPC55XX_FMPLL_ESYNCR1_CLKCFG,
78        .EPREDIV = EPREDIV_VAL,
79        .EMFD = EMFD_VAL
80      }
81    }
82  #endif
83  #ifdef MPC55XX_HAS_MODE_CONTROL
84    .fmpll = {
85      {
86        .cr = {
87          #if MPC55XX_REFERENCE_CLOCK == 8000000
88            .B = { .IDF = 0, .ODF = 1, .NDIV = 60, .I_LOCK = 1, .PLL_ON = 1 }
89          #elif MPC55XX_REFERENCE_CLOCK == 40000000
90            .B = { .IDF = 3, .ODF = 1, .NDIV = 48, .I_LOCK = 1, .PLL_ON = 1 }
91          #else
92            #error "unexpected reference clock"
93          #endif
94        }
95      },
96      {
97        .cr = {
98          .B = { .IDF = 3, .ODF = 2, .NDIV = 32, .I_LOCK = 1, .PLL_ON = 1 }
99        }
100      }
101    },
102    .ocds_sc = {
103      .B = { .SELDIV = 2, .SELCTL = 2 }
104    },
105    .auxclk = {
106      [0] = {
107        .AC_SC = { .B = { .SELCTL = 4 } },
108        .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 0 } }
109      },
110      [1] = {
111        .AC_SC = { .B = { .SELCTL = 4 } },
112        .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } }
113      },
114      [2] = {
115        .AC_SC = { .B = { .SELCTL = 4 } },
116        .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } }
117      },
118      [3] = {
119        .AC_SC = { .B = { .SELCTL = 1 } }
120      },
121      [4] = {
122        .AC_SC = { .B = { .SELCTL = 1 } }
123      }
124    }
125  #endif
126} };
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