1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx |
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5 | * |
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6 | * @brief Clock and FMPLL initialization code. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <bsp.h> |
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24 | #include <bsp/fatal.h> |
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25 | #include <bsp/start.h> |
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26 | #include <bsp/bootcard.h> |
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27 | #include <bsp/mpc55xx-config.h> |
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28 | |
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29 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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30 | #if defined(MPC55XX_HAS_FMPLL) || defined(MPC55XX_HAS_FMPLL_ENHANCED) |
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31 | static BSP_START_TEXT_SECTION void fmpll_wait_for_lock(void) |
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32 | { |
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33 | int i = 0; |
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34 | bool lock = false; |
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35 | |
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36 | while (!lock && i < 6000) { |
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37 | lock = FMPLL.SYNSR.B.LOCK != 0; |
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38 | ++i; |
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39 | } |
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40 | |
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41 | if (!lock) { |
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42 | bsp_fatal(MPC55XX_FATAL_FMPLL_LOCK); |
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43 | } |
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44 | } |
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45 | #endif |
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46 | #endif |
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47 | |
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48 | BSP_START_TEXT_SECTION void mpc55xx_start_clock(void) |
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49 | { |
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50 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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51 | const mpc55xx_clock_config *cfg = mpc55xx_start_config_clock; |
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52 | |
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53 | #ifdef MPC55XX_HAS_FMPLL |
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54 | volatile struct FMPLL_tag *fmpll = &FMPLL; |
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55 | |
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56 | fmpll->SYNCR.R = cfg->syncr_tmp.R; |
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57 | fmpll->SYNCR.R; |
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58 | fmpll_wait_for_lock(); |
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59 | |
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60 | fmpll->SYNCR.R = cfg->syncr_final.R; |
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61 | fmpll->SYNCR.R; |
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62 | fmpll_wait_for_lock(); |
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63 | #endif |
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64 | |
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65 | #ifdef MPC55XX_HAS_FMPLL_ENHANCED |
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66 | volatile struct FMPLL_tag *fmpll = &FMPLL; |
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67 | |
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68 | fmpll->ESYNCR2.R = cfg->esyncr2_tmp.R; |
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69 | fmpll->ESYNCR2.R; |
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70 | fmpll->ESYNCR1.R = cfg->esyncr1_final.R; |
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71 | fmpll->ESYNCR1.R; |
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72 | fmpll_wait_for_lock(); |
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73 | |
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74 | fmpll->ESYNCR2.R = cfg->esyncr2_final.R; |
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75 | fmpll->ESYNCR2.R; |
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76 | fmpll_wait_for_lock(); |
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77 | |
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78 | #if MPC55XX_CHIP_FAMILY == 551 || MPC55XX_CHIP_FAMILY == 566 |
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79 | /* System clock supplied by PLL */ |
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80 | SIU.SYSCLK.B.SYSCLKSEL = 2; |
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81 | #endif |
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82 | #endif |
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83 | |
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84 | #ifdef MPC55XX_HAS_MODE_CONTROL |
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85 | volatile CGM_tag *cgm = &CGM; |
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86 | size_t fmpll_count = sizeof(cfg->fmpll) / sizeof(cfg->fmpll [0]); |
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87 | size_t auxclk_count = sizeof(cfg->auxclk) / sizeof(cfg->auxclk [0]); |
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88 | size_t i = 0; |
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89 | |
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90 | for (i = 0; i < auxclk_count; ++i) { |
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91 | cgm->AUXCLK [i].AC_SC.R = cfg->auxclk [i].AC_SC.R; |
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92 | cgm->AUXCLK [i].AC_DC0_3.R = cfg->auxclk [i].AC_DC0_3.R; |
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93 | } |
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94 | |
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95 | for (i = 0; i < fmpll_count; ++i) { |
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96 | cgm->FMPLL [i].CR.R = cfg->fmpll [i].cr.R; |
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97 | cgm->FMPLL [i].MR.R = cfg->fmpll [i].mr.R; |
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98 | } |
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99 | |
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100 | cgm->OC_EN.R = cfg->oc_en.R; |
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101 | cgm->OCDS_SC.R = cfg->ocds_sc.R; |
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102 | #endif |
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103 | #endif |
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104 | } |
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