1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @ingroup mpc55xx_asm |
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7 | * |
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8 | * @brief Cache initialization. |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Copyright (C) 2008, 2012 embedded brains GmbH & Co. KG |
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13 | * |
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14 | * Redistribution and use in source and binary forms, with or without |
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15 | * modification, are permitted provided that the following conditions |
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16 | * are met: |
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17 | * 1. Redistributions of source code must retain the above copyright |
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18 | * notice, this list of conditions and the following disclaimer. |
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19 | * 2. Redistributions in binary form must reproduce the above copyright |
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20 | * notice, this list of conditions and the following disclaimer in the |
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21 | * documentation and/or other materials provided with the distribution. |
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22 | * |
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23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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24 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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27 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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28 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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29 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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30 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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31 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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32 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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33 | * POSSIBILITY OF SUCH DAMAGE. |
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34 | */ |
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35 | |
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36 | #include <libcpu/powerpc-utility.h> |
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37 | |
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38 | #include <mpc55xx/regs.h> |
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39 | |
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40 | .globl mpc55xx_start_cache |
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41 | |
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42 | .section ".bsp_start_text", "ax" |
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43 | |
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44 | mpc55xx_start_cache: |
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45 | |
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46 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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47 | |
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48 | /* Load zero, CINV, and CABT) */ |
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49 | li r0, 0 |
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50 | li r3, 0x2 |
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51 | li r4, 0x4 |
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52 | |
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53 | #if defined(BSP_INSTRUCTION_CACHE_ENABLED) \ |
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54 | && defined(MPC55XX_HAS_INSTRUCTION_CACHE) |
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55 | |
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56 | start_instruction_cache_invalidation: |
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57 | |
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58 | /* Clear instruction cache invalidation abort */ |
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59 | mtspr FSL_EIS_L1CSR1, r0 |
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60 | |
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61 | /* Start instruction cache invalidation */ |
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62 | mtspr FSL_EIS_L1CSR1, r3 |
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63 | |
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64 | get_instruction_cache_invalidation_status: |
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65 | |
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66 | /* Get instruction cache invalidation status */ |
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67 | mfspr r5, FSL_EIS_L1CSR1 |
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68 | |
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69 | /* Check CABT */ |
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70 | and. r6, r5, r4 |
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71 | bne start_instruction_cache_invalidation |
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72 | |
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73 | /* Check CINV */ |
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74 | and. r6, r5, r3 |
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75 | bne get_instruction_cache_invalidation_status |
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76 | |
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77 | /* Save instruction cache settings */ |
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78 | LWI r6, 0x00010001 |
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79 | isync |
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80 | msync |
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81 | mtspr FSL_EIS_L1CSR1, r6 |
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82 | |
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83 | #endif |
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84 | |
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85 | #if (defined(BSP_DATA_CACHE_ENABLED) && defined(MPC55XX_HAS_DATA_CACHE)) \ |
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86 | || ((defined(BSP_DATA_CACHE_ENABLED) \ |
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87 | || defined(BSP_INSTRUCTION_CACHE_ENABLED)) \ |
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88 | && defined(MPC55XX_HAS_UNIFIED_CACHE)) |
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89 | |
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90 | start_data_cache_invalidation: |
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91 | |
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92 | /* Clear data cache invalidation abort */ |
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93 | mtspr FSL_EIS_L1CSR0, r0 |
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94 | |
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95 | /* Start data cache invalidation */ |
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96 | mtspr FSL_EIS_L1CSR0, r3 |
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97 | |
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98 | get_data_cache_invalidation_status: |
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99 | |
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100 | /* Get data cache invalidation status */ |
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101 | mfspr r5, FSL_EIS_L1CSR0 |
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102 | |
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103 | /* Check CABT */ |
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104 | and. r6, r5, r4 |
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105 | bne start_data_cache_invalidation |
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106 | |
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107 | /* Check CINV */ |
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108 | and. r6, r5, r3 |
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109 | bne get_data_cache_invalidation_status |
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110 | |
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111 | /* Save data cache settings */ |
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112 | #if MPC55XX_CHIP_FAMILY != 567 |
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113 | /* FIXME: CORG??? 0x00180011 */ |
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114 | LWI r6, 0x00100001 |
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115 | #else |
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116 | LWI r6, 0x00190001 |
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117 | #endif |
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118 | isync |
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119 | msync |
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120 | mtspr FSL_EIS_L1CSR0, r6 |
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121 | |
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122 | #endif |
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123 | |
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124 | #endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */ |
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125 | |
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126 | /* Return */ |
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127 | blr |
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