source: rtems/bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h @ e560ee85

Last change on this file since e560ee85 was e560ee85, checked in by Joel Sherrill <joel@…>, on 03/01/22 at 21:38:55

bsps/powerpc/: Scripted embedded brains header file clean up

Updates #4625.
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1/**
2 * @file
3 *
4 * @ingroup RTEMSBSPsPowerPCMPC55XX
5 *
6 * @brief SMSC - LAN9218i
7 */
8
9/*
10 * Copyright (c) 2009-2012 embedded brains GmbH.  All rights reserved.
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 * http://www.rtems.org/license/LICENSE.
15 */
16
17#include <bsp.h>
18
19/**
20 * @name Memory Map
21 * @{
22 */
23
24typedef struct {
25  uint32_t rx_fifo_data;
26  uint32_t rx_fifo_data_aliases [7];
27  uint32_t tx_fifo_data;
28  uint32_t tx_fifo_data_aliases [7];
29  uint32_t rx_fifo_status;
30  uint32_t rx_fifo_status_peek;
31  uint32_t tx_fifo_status;
32  uint32_t tx_fifo_status_peek;
33  uint32_t id_rev;
34  uint32_t irq_cfg;
35  uint32_t int_sts;
36  uint32_t int_en;
37  uint32_t reserved_0;
38  uint32_t byte_test;
39  uint32_t fifo_int;
40  uint32_t rx_cfg;
41  uint32_t tx_cfg;
42  uint32_t hw_cfg;
43  uint32_t rx_dp_ctl;
44  uint32_t rx_fifo_inf;
45  uint32_t tx_fifo_inf;
46  uint32_t pmt_ctrl;
47  uint32_t gpio_cfg;
48  uint32_t gpt_cfg;
49  uint32_t gpt_cnt;
50  uint32_t reserved_1;
51  uint32_t word_swap;
52  uint32_t free_run;
53  uint32_t rx_drop;
54  uint32_t mac_csr_cmd;
55  uint32_t mac_csr_data;
56  uint32_t afc_cfg;
57  uint32_t e2p_cmd;
58  uint32_t e2p_data;
59} smsc9218i_registers;
60
61/*
62 * SMSC9218 registers are accessed little-endian (address 0x3fff8000, A22 used
63 * as END_SEL).
64 */
65#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
66  volatile smsc9218i_registers *const smsc9218i =
67    (volatile smsc9218i_registers *) 0x3fff8000;
68  volatile smsc9218i_registers *const smsc9218i_dma =
69    (volatile smsc9218i_registers *) 0x3fff8200;
70#else
71  volatile smsc9218i_registers *const smsc9218i =
72    (volatile smsc9218i_registers *) 0x3fff8000;
73  volatile smsc9218i_registers *const smsc9218i_dma =
74    (volatile smsc9218i_registers *) 0x3fff8000;
75#endif
76
77/** @} */
78
79#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
80  #define SMSC9218I_BIT_POS(pos) (pos)
81#else
82  #define SMSC9218I_BIT_POS(pos) \
83    ((pos) > 15 ? \
84      ((pos) > 23 ? (pos) - 24 : (pos) - 8) \
85        : ((pos) > 7 ? (pos) + 8 : (pos) + 24))
86#endif
87
88#define SMSC9218I_FLAG(pos) \
89  (1U << SMSC9218I_BIT_POS(pos))
90
91#define SMSC9218I_FIELD_8(val, pos) \
92  (((val) & 0xff) << SMSC9218I_BIT_POS(pos))
93
94#define SMSC9218I_GET_FIELD_8(reg, pos) \
95  (((reg) >> SMSC9218I_BIT_POS(pos)) & 0xff)
96
97#define SMSC9218I_FIELD_16(val, pos) \
98  (SMSC9218I_FIELD_8((val) >> 8, (pos) + 8) \
99    | SMSC9218I_FIELD_8((val), pos))
100
101#define SMSC9218I_GET_FIELD_16(reg, pos) \
102  ((SMSC9218I_GET_FIELD_8(reg, (pos) + 8) << 8) \
103    | SMSC9218I_GET_FIELD_8(reg, pos))
104
105#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
106  #define SMSC9218I_SWAP(val) (val)
107#else
108  #define SMSC9218I_SWAP(val) \
109    ((((val) >> 24) & 0xff) \
110      | ((((val) >> 16) & 0xff) << 8) \
111      | ((((val) >> 8) & 0xff) << 16) \
112      | (((val) & 0xff) << 24))
113#endif
114
115/**
116 * @name Receive Status
117 * @{
118 */
119
120#define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30)
121#define SMSC9218I_RX_STS_GET_LENGTH(reg) (SMSC9218I_GET_FIELD_16(reg, 16) & 0x3fff)
122#define SMSC9218I_RX_STS_ERROR SMSC9218I_FLAG(15)
123#define SMSC9218I_RX_STS_BROADCAST SMSC9218I_FLAG(13)
124#define SMSC9218I_RX_STS_ERROR_LENGTH SMSC9218I_FLAG(12)
125#define SMSC9218I_RX_STS_ERROR_RUNT_FRAME SMSC9218I_FLAG(11)
126#define SMSC9218I_RX_STS_MULTICAST SMSC9218I_FLAG(10)
127#define SMSC9218I_RX_STS_ERROR_TOO_LONG SMSC9218I_FLAG(7)
128#define SMSC9218I_RX_STS_ERROR_COLLISION SMSC9218I_FLAG(6)
129#define SMSC9218I_RX_STS_TYPE SMSC9218I_FLAG(5)
130#define SMSC9218I_RX_STS_WATCHDOG SMSC9218I_FLAG(4)
131#define SMSC9218I_RX_STS_ERROR_MII SMSC9218I_FLAG(3)
132#define SMSC9218I_RX_STS_DRIBBLING_BIT SMSC9218I_FLAG(2)
133#define SMSC9218I_RX_STS_ERROR_CRC SMSC9218I_FLAG(1)
134
135/** @} */
136
137/**
138 * @name Transmit Status
139 * @{
140 */
141
142#define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
143#define SMSC9218I_TX_STS_ERROR SMSC9218I_FLAG(15)
144#define SMSC9218I_TX_STS_ERROR_LOSS_OF_CARRIER SMSC9218I_FLAG(11)
145#define SMSC9218I_TX_STS_ERROR_NO_CARRIER SMSC9218I_FLAG(10)
146#define SMSC9218I_TX_STS_ERROR_LATE_COLLISION SMSC9218I_FLAG(9)
147#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_COLLISIONS SMSC9218I_FLAG(8)
148#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_DEFERRAL SMSC9218I_FLAG(2)
149#define SMSC9218I_TX_STS_ERROR_DEFERRED SMSC9218I_FLAG(0)
150
151/** @} */
152
153/**
154 * @name Transmit Command A
155 * @{
156 */
157
158#define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31)
159#define SMSC9218I_TX_A_END_ALIGN_4 0
160#define SMSC9218I_TX_A_END_ALIGN_16 SMSC9218I_FLAG(24)
161#define SMSC9218I_TX_A_END_ALIGN_32 SMSC9218I_FLAG(25)
162#define SMSC9218I_TX_A_DOFF(val) SMSC9218I_FIELD_8(val, 16)
163#define SMSC9218I_TX_A_FIRST SMSC9218I_FLAG(13)
164#define SMSC9218I_TX_A_LAST SMSC9218I_FLAG(12)
165#define SMSC9218I_TX_A_FRAGMENT_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
166
167/** @} */
168
169/**
170 * @name Transmit Command B
171 * @{
172 */
173
174#define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16)
175#define SMSC9218I_TX_B_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
176#define SMSC9218I_TX_B_DISABLE_CRC SMSC9218I_FLAG(13)
177#define SMSC9218I_TX_B_DISABLE_PAD SMSC9218I_FLAG(12)
178#define SMSC9218I_TX_B_FRAME_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
179
180/** @} */
181
182/**
183 * @name Chip ID and Revision
184 * @{
185 */
186
187#define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16)
188#define SMSC9218I_ID_REV_GET_REV(reg) SMSC9218I_GET_FIELD_16(reg, 0)
189#define SMSC9218I_ID_REV_ID_CHIP_118 0x0118U
190#define SMSC9218I_ID_REV_ID_CHIP_218 0x118aU
191
192/** @} */
193
194/**
195 * @name Interrupt Configuration
196 * @{
197 */
198
199#define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24)
200#define SMSC9218I_IRQ_CFG_GET_INT_DEAS(reg) SMSC9218I_GET_FIELD_8(reg, 24)
201#define SMSC9218I_IRQ_CFG_INT_DEAS_CLR SMSC9218I_FLAG(14)
202#define SMSC9218I_IRQ_CFG_INT_DEAS_STS SMSC9218I_FLAG(13)
203#define SMSC9218I_IRQ_CFG_IRQ_INT SMSC9218I_FLAG(12)
204#define SMSC9218I_IRQ_CFG_IRQ_EN SMSC9218I_FLAG(8)
205#define SMSC9218I_IRQ_CFG_IRQ_POL SMSC9218I_FLAG(4)
206#define SMSC9218I_IRQ_CFG_IRQ_TYPE SMSC9218I_FLAG(0)
207
208/** @} */
209
210/**
211 * @name Interrupt Enable and Status
212 * @{
213 */
214
215#define SMSC9218I_INT_SW SMSC9218I_FLAG(31)
216#define SMSC9218I_INT_TXSTOP SMSC9218I_FLAG(25)
217#define SMSC9218I_INT_RXSTOP SMSC9218I_FLAG(24)
218#define SMSC9218I_INT_RXDFH SMSC9218I_FLAG(23)
219#define SMSC9218I_INT_TIOC SMSC9218I_FLAG(21)
220#define SMSC9218I_INT_RXD SMSC9218I_FLAG(20)
221#define SMSC9218I_INT_GPT SMSC9218I_FLAG(19)
222#define SMSC9218I_INT_PHY SMSC9218I_FLAG(18)
223#define SMSC9218I_INT_PME SMSC9218I_FLAG(17)
224#define SMSC9218I_INT_TXSO SMSC9218I_FLAG(16)
225#define SMSC9218I_INT_RWT SMSC9218I_FLAG(15)
226#define SMSC9218I_INT_RXE SMSC9218I_FLAG(14)
227#define SMSC9218I_INT_TXE SMSC9218I_FLAG(13)
228#define SMSC9218I_INT_TDFO SMSC9218I_FLAG(10)
229#define SMSC9218I_INT_TDFA SMSC9218I_FLAG(9)
230#define SMSC9218I_INT_TSFF SMSC9218I_FLAG(8)
231#define SMSC9218I_INT_TSFL SMSC9218I_FLAG(7)
232#define SMSC9218I_INT_RSFF SMSC9218I_FLAG(4)
233#define SMSC9218I_INT_RSFL SMSC9218I_FLAG(3)
234#define SMSC9218I_INT_GPIO2 SMSC9218I_FLAG(2)
235#define SMSC9218I_INT_GPIO1 SMSC9218I_FLAG(1)
236#define SMSC9218I_INT_GPIO0 SMSC9218I_FLAG(0)
237
238/** @} */
239
240/**
241 * @name Byte Order Testing
242 * @{
243 */
244
245#define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U)
246
247/** @} */
248
249/**
250 * @name FIFO Level Interrupts
251 * @{
252 */
253
254#define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24)
255#define SMSC9218I_FIFO_INT_GET_TDAL(reg) SMSC9218I_GET_FIELD_8(reg, 24)
256#define SMSC9218I_FIFO_INT_TSL(val) SMSC9218I_FIELD_8(val, 16)
257#define SMSC9218I_FIFO_INT_GET_TSL(reg) SMSC9218I_GET_FIELD_8(reg, 16)
258#define SMSC9218I_FIFO_INT_RSL(val) SMSC9218I_FIELD_8(val, 0)
259#define SMSC9218I_FIFO_INT_GET_RSL(reg) SMSC9218I_GET_FIELD_8(reg, 0)
260
261/** @} */
262
263/**
264 * @name Receive Configuration
265 * @{
266 */
267
268#define SMSC9218I_RX_CFG_END_ALIGN_4 0
269#define SMSC9218I_RX_CFG_END_ALIGN_16 SMSC9218I_FLAG(30)
270#define SMSC9218I_RX_CFG_END_ALIGN_32 SMSC9218I_FLAG(31)
271#define SMSC9218I_RX_CFG_DMA_CNT(val) SMSC9218I_FIELD_8(val, 24)
272#define SMSC9218I_RX_CFG_GET_DMA_CNT(reg) SMSC9218I_GET_FIELD_8(reg, 24)
273#define SMSC9218I_RX_CFG_DUMP SMSC9218I_FLAG(15)
274#define SMSC9218I_RX_CFG_DOFF(val) SMSC9218I_FIELD_8(val, 8)
275#define SMSC9218I_RX_CFG_GET_DOFF(reg) SMSC9218I_GET_FIELD_8(reg, 8)
276
277/** @} */
278
279/**
280 * @name Transmit Configuration
281 * @{
282 */
283
284#define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15)
285#define SMSC9218I_TX_CFG_DDUMP SMSC9218I_FLAG(14)
286#define SMSC9218I_TX_CFG_SAO SMSC9218I_FLAG(2)
287#define SMSC9218I_TX_CFG_ON SMSC9218I_FLAG(1)
288#define SMSC9218I_TX_CFG_STOP SMSC9218I_FLAG(0)
289
290/** @} */
291
292/**
293 * @name Hardware Configuration
294 * @{
295 */
296
297#define SMSC9218I_HW_CFG_LED_3 SMSC9218I_FLAG(30)
298#define SMSC9218I_HW_CFG_LED_2 SMSC9218I_FLAG(29)
299#define SMSC9218I_HW_CFG_LED_1 SMSC9218I_FLAG(28)
300#define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24)
301#define SMSC9218I_HW_CFG_MBO SMSC9218I_FLAG(20)
302#define SMSC9218I_HW_CFG_TX_FIF_SZ(val) SMSC9218I_FIELD_8(val, 16)
303#define SMSC9218I_HW_CFG_GET_TX_FIF_SZ(reg) SMSC9218I_GET_FIELD_8(reg, 16)
304#define SMSC9218I_HW_CFG_BITMD_32 SMSC9218I_FLAG(2)
305#define SMSC9218I_HW_CFG_SRST_TO SMSC9218I_FLAG(1)
306#define SMSC9218I_HW_CFG_SRST SMSC9218I_FLAG(0)
307
308/** @} */
309
310/**
311 * @name Receive Datapath Control
312 * @{
313 */
314
315#define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31)
316
317/** @} */
318
319/**
320 * @name Receive FIFO Information
321 * @{
322 */
323
324#define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
325#define SMSC9218I_RX_FIFO_INF_GET_DUSED(reg) SMSC9218I_GET_FIELD_16(reg, 0)
326
327/** @} */
328
329/**
330 * @name Transmit FIFO Information
331 * @{
332 */
333
334#define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
335#define SMSC9218I_TX_FIFO_INF_GET_FREE(reg) SMSC9218I_GET_FIELD_16(reg, 0)
336
337/** @} */
338
339/**
340 * @name Power Management Control
341 * @{
342 */
343
344#define SMSC9218I_PMT_CTRL_PM_MODE_D0 0
345#define SMSC9218I_PMT_CTRL_PM_MODE_D1 SMSC9218I_FLAG(12)
346#define SMSC9218I_PMT_CTRL_PM_MODE_D2 SMSC9218I_FLAG(13)
347#define SMSC9218I_PMT_CTRL_PHY_RST SMSC9218I_FLAG(10)
348#define SMSC9218I_PMT_CTRL_WOL_EN SMSC9218I_FLAG(9)
349#define SMSC9218I_PMT_CTRL_ED_EN SMSC9218I_FLAG(8)
350#define SMSC9218I_PMT_CTRL_PME_TYPE_PUPU SMSC9218I_FLAG(6)
351#define SMSC9218I_PMT_CTRL_WUPS_NO 0
352#define SMSC9218I_PMT_CTRL_WUPS_ENERGY SMSC9218I_FLAG(4)
353#define SMSC9218I_PMT_CTRL_WUPS_MAGIC SMSC9218I_FLAG(5)
354#define SMSC9218I_PMT_CTRL_PME_IND SMSC9218I_FLAG(3)
355#define SMSC9218I_PMT_CTRL_PME_POL SMSC9218I_FLAG(2)
356#define SMSC9218I_PMT_CTRL_PME_EN SMSC9218I_FLAG(1)
357#define SMSC9218I_PMT_CTRL_READY SMSC9218I_FLAG(0)
358
359/** @} */
360
361/**
362 * @name General Purpose IO Configuration
363 * @{
364 */
365
366#define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30)
367#define SMSC9218I_GPIO_CFG_LED2 SMSC9218I_FLAG(29)
368#define SMSC9218I_GPIO_CFG_LED1 SMSC9218I_FLAG(28)
369#define SMSC9218I_GPIO_CFG_GPIO2_INT_POL SMSC9218I_FLAG(26)
370#define SMSC9218I_GPIO_CFG_GPIO1_INT_POL SMSC9218I_FLAG(25)
371#define SMSC9218I_GPIO_CFG_GPIO0_INT_POL SMSC9218I_FLAG(24)
372#define SMSC9218I_GPIO_CFG_GPIOBUF2 SMSC9218I_FLAG(18)
373#define SMSC9218I_GPIO_CFG_GPIOBUF1 SMSC9218I_FLAG(17)
374#define SMSC9218I_GPIO_CFG_GPIOBUF0 SMSC9218I_FLAG(16)
375#define SMSC9218I_GPIO_CFG_GPIODIR2 SMSC9218I_FLAG(10)
376#define SMSC9218I_GPIO_CFG_GPIODIR1 SMSC9218I_FLAG(9)
377#define SMSC9218I_GPIO_CFG_GPIODIR0 SMSC9218I_FLAG(8)
378#define SMSC9218I_GPIO_CFG_GPO4 SMSC9218I_FLAG(4)
379#define SMSC9218I_GPIO_CFG_GPO3 SMSC9218I_FLAG(3)
380#define SMSC9218I_GPIO_CFG_GPIO0 SMSC9218I_FLAG(0)
381#define SMSC9218I_GPIO_CFG_GPIO2 SMSC9218I_FLAG(2)
382#define SMSC9218I_GPIO_CFG_GPIO1 SMSC9218I_FLAG(1)
383
384/** @} */
385
386/**
387 * @name General Purpose Timer Configuration
388 * @{
389 */
390
391#define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29)
392#define SMSC9218I_GPT_CFG_LOAD(val) SMSC9218I_FIELD_16(val, 0)
393#define SMSC9218I_GPT_CFG_GET_LOAD(reg) SMSC9218I_GET_FIELD_16(reg, 0)
394
395/** @} */
396
397/**
398 * @name General Purpose Timer Count
399 * @{
400 */
401
402#define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0)
403
404/** @} */
405
406/**
407 * @name Word Swap
408 * @{
409 */
410
411#define SMSC9218I_ENDIAN_BIG 0xffffffffU
412
413/** @} */
414
415/**
416 * @name Free Run Counter
417 * @{
418 */
419
420#define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg)
421
422/** @} */
423
424/**
425 * @name Receiver Dropped Frames Counter
426 * @{
427 */
428
429#define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg)
430
431/** @} */
432
433/**
434 * @name EEPROM Command Register
435 * @{
436 */
437
438#define SMSC9218I_E2P_CMD_EPC_BUSY SMSC9218I_FLAG(31)
439
440/** @} */
441
442/**
443 * @name MAC Control and Status Synchronizer Command
444 * @{
445 */
446
447#define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31)
448#define SMSC9218I_MAC_CSR_CMD_READ SMSC9218I_FLAG(30)
449#define SMSC9218I_MAC_CSR_CMD_ADDR(val) SMSC9218I_FIELD_8(val, 0)
450#define SMSC9218I_MAC_CSR_CMD_GET_ADDR(reg) SMSC9218I_GET_FIELD_8(reg, 0)
451
452/** @} */
453
454/**
455 * @name MAC Control Register
456 * @{
457 */
458
459#define SMSC9218I_MAC_CR 0x00000001U
460#define SMSC9218I_MAC_CR_RXALL 0x80000000U
461#define SMSC9218I_MAC_CR_HBDIS 0x10000000U
462#define SMSC9218I_MAC_CR_RCVOWN 0x00800000U
463#define SMSC9218I_MAC_CR_LOOPBK 0x00200000U
464#define SMSC9218I_MAC_CR_FDPX 0x00100000U
465#define SMSC9218I_MAC_CR_MCPAS 0x00080000U
466#define SMSC9218I_MAC_CR_PRMS 0x00040000U
467#define SMSC9218I_MAC_CR_INVFILT 0x00020000U
468#define SMSC9218I_MAC_CR_PASSBAD 0x00010000U
469#define SMSC9218I_MAC_CR_HFILT 0x00008000U
470#define SMSC9218I_MAC_CR_HPFILT 0x00002000U
471#define SMSC9218I_MAC_CR_LCOLL 0x00001000U
472#define SMSC9218I_MAC_CR_BCAST 0x00000800U
473#define SMSC9218I_MAC_CR_DISRTY 0x00000400U
474#define SMSC9218I_MAC_CR_PADSTR 0x00000100U
475#define SMSC9218I_MAC_CR_BOLMT_MASK 0x000000c0U
476#define SMSC9218I_MAC_CR_BOLMT_10 0x00000000U
477#define SMSC9218I_MAC_CR_BOLMT_8 0x00000040U
478#define SMSC9218I_MAC_CR_BOLMT_4 0x00000080U
479#define SMSC9218I_MAC_CR_BOLMT_1 0x000000c0U
480#define SMSC9218I_MAC_CR_DFCHK 0x00000020U
481#define SMSC9218I_MAC_CR_TXEN 0x00000008U
482#define SMSC9218I_MAC_CR_RXEN 0x00000004U
483
484/** @} */
485
486/**
487 * @name MAC Address High
488 * @{
489 */
490
491#define SMSC9218I_MAC_ADDRH 0x00000002U
492#define SMSC9218I_MAC_ADDRH_MASK 0x0000ffffU
493
494/** @} */
495
496/**
497 * @name MAC Address Low
498 * @{
499 */
500
501#define SMSC9218I_MAC_ADDRL 0x00000003U
502#define SMSC9218I_MAC_ADDRL_MASK 0xffffffffU
503
504/** @} */
505
506/**
507 * @name Multicast Hash Table High
508 * @{
509 */
510
511#define SMSC9218I_MAC_HASHH 0x00000004U
512#define SMSC9218I_MAC_HASHH_MASK 0xffffffffU
513
514/** @} */
515
516/**
517 * @name Multicast Hash Table Low
518 * @{
519 */
520
521#define SMSC9218I_MAC_HASHL 0x00000005U
522#define SMSC9218I_MAC_HASHL_MASK 0xffffffffU
523
524/** @} */
525
526/**
527 * @name MII Access
528 * @{
529 */
530
531#define SMSC9218I_MAC_MII_ACC 0x00000006U
532#define SMSC9218I_MAC_MII_ACC_PHY_DEFAULT (1U << 11)
533#define SMSC9218I_MAC_MII_ACC_WRITE (1U << 1)
534#define SMSC9218I_MAC_MII_ACC_BUSY (1U << 0)
535#define SMSC9218I_MAC_MII_ACC_ADDR(addr) ((addr) << 6)
536
537/** @} */
538
539/**
540 * @name MII Data
541 * @{
542 */
543
544#define SMSC9218I_MAC_MII_DATA 0x00000007U
545
546/** @} */
547
548/**
549 * @name Flow Control
550 * @{
551 */
552
553#define SMSC9218I_MAC_FLOW 0x00000008U
554#define SMSC9218I_MAC_FLOW_FCPT_MASK 0xffff0000U
555#define SMSC9218I_MAC_FLOW_FCPASS 0x00000004U
556#define SMSC9218I_MAC_FLOW_FCEN 0x00000002U
557#define SMSC9218I_MAC_FLOW_FCBSY 0x00000001U
558
559/** @} */
560
561/**
562 * @name VLAN1 Tag
563 * @{
564 */
565
566#define SMSC9218I_MAC_VLAN1 0x00000009U
567
568/** @} */
569
570/**
571 * @name VLAN2 Tag
572 * @{
573 */
574
575#define SMSC9218I_MAC_VLAN2 0x0000000aU
576
577/** @} */
578
579/**
580 * @name Wake-up Frame Filter
581 * @{
582 */
583
584#define SMSC9218I_MAC_WUFF 0x0000000bU
585
586/** @} */
587
588/**
589 * @name Wake-up Control and Status
590 * @{
591 */
592
593#define SMSC9218I_MAC_WUCSR 0x0000000cU
594#define SMSC9218I_MAC_WUCSR_GUE 0x00000200U
595#define SMSC9218I_MAC_WUCSR_WUFR 0x00000040U
596#define SMSC9218I_MAC_WUCSR_MPR 0x00000020U
597#define SMSC9218I_MAC_WUCSR_WUEN 0x00000004U
598#define SMSC9218I_MAC_WUCSR_MPEN 0x00000002U
599
600/** @} */
601
602/**
603 * @name PHY Identifier 1
604 * @{
605 */
606
607#define SMSC9218I_PHY_ID1_LAN9118 0x7
608
609/** @} */
610
611/**
612 * @name PHY Identifier 2
613 * @{
614 */
615
616#define SMSC9218I_PHY_ID2_LAN9218 0xc0c3
617
618/** @} */
619
620/**
621 * @name Mode Control and Status
622 * @{
623 */
624
625#define SMSC9218I_PHY_MCSR 0x00000011U
626#define SMSC9218I_PHY_MCSR_EDPWRDOWN 0x00002000U
627#define SMSC9218I_PHY_MCSR_ENERGYON 0x00000002U
628
629/** @} */
630
631/**
632 * @name Special Modes
633 * @{
634 */
635
636#define SMSC9218I_PHY_SPMODES 0x00000012U
637
638/** @} */
639
640/**
641 * @name Special Control and Status Indications
642 * @{
643 */
644
645#define SMSC9218I_PHY_CSIR 0x0000001bU
646#define SMSC9218I_PHY_CSIR_SQEOFF 0x00000800U
647#define SMSC9218I_PHY_CSIR_FEFIEN 0x00000020U
648#define SMSC9218I_PHY_CSIR_XPOL 0x00000010U
649
650/** @} */
651
652/**
653 * @name Interrupt Source Flag
654 * @{
655 */
656
657#define SMSC9218I_PHY_ISR 0x0000001dU
658#define SMSC9218I_PHY_ISR_INT7 0x00000080U
659#define SMSC9218I_PHY_ISR_INT6 0x00000040U
660#define SMSC9218I_PHY_ISR_INT5 0x00000020U
661#define SMSC9218I_PHY_ISR_INT4 0x00000010U
662#define SMSC9218I_PHY_ISR_INT3 0x00000008U
663#define SMSC9218I_PHY_ISR_INT2 0x00000004U
664#define SMSC9218I_PHY_ISR_INT1 0x00000002U
665
666/** @} */
667
668/**
669 * @name Interrupt Mask
670 * @{
671 */
672
673#define SMSC9218I_PHY_IMR 0x0000001eU
674#define SMSC9218I_PHY_IMR_INT7 0x00000080U
675#define SMSC9218I_PHY_IMR_INT6 0x00000040U
676#define SMSC9218I_PHY_IMR_INT5 0x00000020U
677#define SMSC9218I_PHY_IMR_INT4 0x00000010U
678#define SMSC9218I_PHY_IMR_INT3 0x00000008U
679#define SMSC9218I_PHY_IMR_INT2 0x00000004U
680#define SMSC9218I_PHY_IMR_INT1 0x00000002U
681
682/** @} */
683
684/**
685 * @name PHY Special Control and Status
686 * @{
687 */
688
689#define SMSC9218I_PHY_PHYSCSR 0x0000001fU
690#define SMSC9218I_PHY_PHYSCSR_ANDONE 0x00001000U
691#define SMSC9218I_PHY_PHYSCSR_4B5B_EN 0x00000040U
692#define SMSC9218I_PHY_PHYSCSR_SPEED_MASK 0x0000001cU
693#define SMSC9218I_PHY_PHYSCSR_SPEED_10HD 0x00000004U
694#define SMSC9218I_PHY_PHYSCSR_SPEED_10FD 0x00000014U
695#define SMSC9218I_PHY_PHYSCSR_SPEED_100HD 0x00000008U
696#define SMSC9218I_PHY_PHYSCSR_SPEED_100FD 0x00000018U
697
698/** @} */
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