source: rtems/bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 16.9 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx
5 *
6 * @brief SMSC - LAN9218i
7 */
8
9/*
10 * Copyright (c) 2009-2012 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#include <bsp.h>
24
25/**
26 * @name Memory Map
27 * @{
28 */
29
30typedef struct {
31  uint32_t rx_fifo_data;
32  uint32_t rx_fifo_data_aliases [7];
33  uint32_t tx_fifo_data;
34  uint32_t tx_fifo_data_aliases [7];
35  uint32_t rx_fifo_status;
36  uint32_t rx_fifo_status_peek;
37  uint32_t tx_fifo_status;
38  uint32_t tx_fifo_status_peek;
39  uint32_t id_rev;
40  uint32_t irq_cfg;
41  uint32_t int_sts;
42  uint32_t int_en;
43  uint32_t reserved_0;
44  uint32_t byte_test;
45  uint32_t fifo_int;
46  uint32_t rx_cfg;
47  uint32_t tx_cfg;
48  uint32_t hw_cfg;
49  uint32_t rx_dp_ctl;
50  uint32_t rx_fifo_inf;
51  uint32_t tx_fifo_inf;
52  uint32_t pmt_ctrl;
53  uint32_t gpio_cfg;
54  uint32_t gpt_cfg;
55  uint32_t gpt_cnt;
56  uint32_t reserved_1;
57  uint32_t word_swap;
58  uint32_t free_run;
59  uint32_t rx_drop;
60  uint32_t mac_csr_cmd;
61  uint32_t mac_csr_data;
62  uint32_t afc_cfg;
63  uint32_t e2p_cmd;
64  uint32_t e2p_data;
65} smsc9218i_registers;
66
67/*
68 * SMSC9218 registers are accessed little-endian (address 0x3fff8000, A22 used
69 * as END_SEL).
70 */
71#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
72  volatile smsc9218i_registers *const smsc9218i =
73    (volatile smsc9218i_registers *) 0x3fff8000;
74  volatile smsc9218i_registers *const smsc9218i_dma =
75    (volatile smsc9218i_registers *) 0x3fff8200;
76#else
77  volatile smsc9218i_registers *const smsc9218i =
78    (volatile smsc9218i_registers *) 0x3fff8000;
79  volatile smsc9218i_registers *const smsc9218i_dma =
80    (volatile smsc9218i_registers *) 0x3fff8000;
81#endif
82
83/** @} */
84
85#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
86  #define SMSC9218I_BIT_POS(pos) (pos)
87#else
88  #define SMSC9218I_BIT_POS(pos) \
89    ((pos) > 15 ? \
90      ((pos) > 23 ? (pos) - 24 : (pos) - 8) \
91        : ((pos) > 7 ? (pos) + 8 : (pos) + 24))
92#endif
93
94#define SMSC9218I_FLAG(pos) \
95  (1U << SMSC9218I_BIT_POS(pos))
96
97#define SMSC9218I_FIELD_8(val, pos) \
98  (((val) & 0xff) << SMSC9218I_BIT_POS(pos))
99
100#define SMSC9218I_GET_FIELD_8(reg, pos) \
101  (((reg) >> SMSC9218I_BIT_POS(pos)) & 0xff)
102
103#define SMSC9218I_FIELD_16(val, pos) \
104  (SMSC9218I_FIELD_8((val) >> 8, (pos) + 8) \
105    | SMSC9218I_FIELD_8((val), pos))
106
107#define SMSC9218I_GET_FIELD_16(reg, pos) \
108  ((SMSC9218I_GET_FIELD_8(reg, (pos) + 8) << 8) \
109    | SMSC9218I_GET_FIELD_8(reg, pos))
110
111#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
112  #define SMSC9218I_SWAP(val) (val)
113#else
114  #define SMSC9218I_SWAP(val) \
115    ((((val) >> 24) & 0xff) \
116      | ((((val) >> 16) & 0xff) << 8) \
117      | ((((val) >> 8) & 0xff) << 16) \
118      | (((val) & 0xff) << 24))
119#endif
120
121/**
122 * @name Receive Status
123 * @{
124 */
125
126#define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30)
127#define SMSC9218I_RX_STS_GET_LENGTH(reg) (SMSC9218I_GET_FIELD_16(reg, 16) & 0x3fff)
128#define SMSC9218I_RX_STS_ERROR SMSC9218I_FLAG(15)
129#define SMSC9218I_RX_STS_BROADCAST SMSC9218I_FLAG(13)
130#define SMSC9218I_RX_STS_ERROR_LENGTH SMSC9218I_FLAG(12)
131#define SMSC9218I_RX_STS_ERROR_RUNT_FRAME SMSC9218I_FLAG(11)
132#define SMSC9218I_RX_STS_MULTICAST SMSC9218I_FLAG(10)
133#define SMSC9218I_RX_STS_ERROR_TOO_LONG SMSC9218I_FLAG(7)
134#define SMSC9218I_RX_STS_ERROR_COLLISION SMSC9218I_FLAG(6)
135#define SMSC9218I_RX_STS_TYPE SMSC9218I_FLAG(5)
136#define SMSC9218I_RX_STS_WATCHDOG SMSC9218I_FLAG(4)
137#define SMSC9218I_RX_STS_ERROR_MII SMSC9218I_FLAG(3)
138#define SMSC9218I_RX_STS_DRIBBLING_BIT SMSC9218I_FLAG(2)
139#define SMSC9218I_RX_STS_ERROR_CRC SMSC9218I_FLAG(1)
140
141/** @} */
142
143/**
144 * @name Transmit Status
145 * @{
146 */
147
148#define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
149#define SMSC9218I_TX_STS_ERROR SMSC9218I_FLAG(15)
150#define SMSC9218I_TX_STS_ERROR_LOSS_OF_CARRIER SMSC9218I_FLAG(11)
151#define SMSC9218I_TX_STS_ERROR_NO_CARRIER SMSC9218I_FLAG(10)
152#define SMSC9218I_TX_STS_ERROR_LATE_COLLISION SMSC9218I_FLAG(9)
153#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_COLLISIONS SMSC9218I_FLAG(8)
154#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_DEFERRAL SMSC9218I_FLAG(2)
155#define SMSC9218I_TX_STS_ERROR_DEFERRED SMSC9218I_FLAG(0)
156
157/** @} */
158
159/**
160 * @name Transmit Command A
161 * @{
162 */
163
164#define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31)
165#define SMSC9218I_TX_A_END_ALIGN_4 0
166#define SMSC9218I_TX_A_END_ALIGN_16 SMSC9218I_FLAG(24)
167#define SMSC9218I_TX_A_END_ALIGN_32 SMSC9218I_FLAG(25)
168#define SMSC9218I_TX_A_DOFF(val) SMSC9218I_FIELD_8(val, 16)
169#define SMSC9218I_TX_A_FIRST SMSC9218I_FLAG(13)
170#define SMSC9218I_TX_A_LAST SMSC9218I_FLAG(12)
171#define SMSC9218I_TX_A_FRAGMENT_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
172
173/** @} */
174
175/**
176 * @name Transmit Command B
177 * @{
178 */
179
180#define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16)
181#define SMSC9218I_TX_B_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
182#define SMSC9218I_TX_B_DISABLE_CRC SMSC9218I_FLAG(13)
183#define SMSC9218I_TX_B_DISABLE_PAD SMSC9218I_FLAG(12)
184#define SMSC9218I_TX_B_FRAME_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
185
186/** @} */
187
188/**
189 * @name Chip ID and Revision
190 * @{
191 */
192
193#define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16)
194#define SMSC9218I_ID_REV_GET_REV(reg) SMSC9218I_GET_FIELD_16(reg, 0)
195#define SMSC9218I_ID_REV_ID_CHIP_118 0x0118U
196#define SMSC9218I_ID_REV_ID_CHIP_218 0x118aU
197
198/** @} */
199
200/**
201 * @name Interrupt Configuration
202 * @{
203 */
204
205#define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24)
206#define SMSC9218I_IRQ_CFG_GET_INT_DEAS(reg) SMSC9218I_GET_FIELD_8(reg, 24)
207#define SMSC9218I_IRQ_CFG_INT_DEAS_CLR SMSC9218I_FLAG(14)
208#define SMSC9218I_IRQ_CFG_INT_DEAS_STS SMSC9218I_FLAG(13)
209#define SMSC9218I_IRQ_CFG_IRQ_INT SMSC9218I_FLAG(12)
210#define SMSC9218I_IRQ_CFG_IRQ_EN SMSC9218I_FLAG(8)
211#define SMSC9218I_IRQ_CFG_IRQ_POL SMSC9218I_FLAG(4)
212#define SMSC9218I_IRQ_CFG_IRQ_TYPE SMSC9218I_FLAG(0)
213
214/** @} */
215
216/**
217 * @name Interrupt Enable and Status
218 * @{
219 */
220
221#define SMSC9218I_INT_SW SMSC9218I_FLAG(31)
222#define SMSC9218I_INT_TXSTOP SMSC9218I_FLAG(25)
223#define SMSC9218I_INT_RXSTOP SMSC9218I_FLAG(24)
224#define SMSC9218I_INT_RXDFH SMSC9218I_FLAG(23)
225#define SMSC9218I_INT_TIOC SMSC9218I_FLAG(21)
226#define SMSC9218I_INT_RXD SMSC9218I_FLAG(20)
227#define SMSC9218I_INT_GPT SMSC9218I_FLAG(19)
228#define SMSC9218I_INT_PHY SMSC9218I_FLAG(18)
229#define SMSC9218I_INT_PME SMSC9218I_FLAG(17)
230#define SMSC9218I_INT_TXSO SMSC9218I_FLAG(16)
231#define SMSC9218I_INT_RWT SMSC9218I_FLAG(15)
232#define SMSC9218I_INT_RXE SMSC9218I_FLAG(14)
233#define SMSC9218I_INT_TXE SMSC9218I_FLAG(13)
234#define SMSC9218I_INT_TDFO SMSC9218I_FLAG(10)
235#define SMSC9218I_INT_TDFA SMSC9218I_FLAG(9)
236#define SMSC9218I_INT_TSFF SMSC9218I_FLAG(8)
237#define SMSC9218I_INT_TSFL SMSC9218I_FLAG(7)
238#define SMSC9218I_INT_RSFF SMSC9218I_FLAG(4)
239#define SMSC9218I_INT_RSFL SMSC9218I_FLAG(3)
240#define SMSC9218I_INT_GPIO2 SMSC9218I_FLAG(2)
241#define SMSC9218I_INT_GPIO1 SMSC9218I_FLAG(1)
242#define SMSC9218I_INT_GPIO0 SMSC9218I_FLAG(0)
243
244/** @} */
245
246/**
247 * @name Byte Order Testing
248 * @{
249 */
250
251#define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U)
252
253/** @} */
254
255/**
256 * @name FIFO Level Interrupts
257 * @{
258 */
259
260#define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24)
261#define SMSC9218I_FIFO_INT_GET_TDAL(reg) SMSC9218I_GET_FIELD_8(reg, 24)
262#define SMSC9218I_FIFO_INT_TSL(val) SMSC9218I_FIELD_8(val, 16)
263#define SMSC9218I_FIFO_INT_GET_TSL(reg) SMSC9218I_GET_FIELD_8(reg, 16)
264#define SMSC9218I_FIFO_INT_RSL(val) SMSC9218I_FIELD_8(val, 0)
265#define SMSC9218I_FIFO_INT_GET_RSL(reg) SMSC9218I_GET_FIELD_8(reg, 0)
266
267/** @} */
268
269/**
270 * @name Receive Configuration
271 * @{
272 */
273
274#define SMSC9218I_RX_CFG_END_ALIGN_4 0
275#define SMSC9218I_RX_CFG_END_ALIGN_16 SMSC9218I_FLAG(30)
276#define SMSC9218I_RX_CFG_END_ALIGN_32 SMSC9218I_FLAG(31)
277#define SMSC9218I_RX_CFG_DMA_CNT(val) SMSC9218I_FIELD_8(val, 24)
278#define SMSC9218I_RX_CFG_GET_DMA_CNT(reg) SMSC9218I_GET_FIELD_8(reg, 24)
279#define SMSC9218I_RX_CFG_DUMP SMSC9218I_FLAG(15)
280#define SMSC9218I_RX_CFG_DOFF(val) SMSC9218I_FIELD_8(val, 8)
281#define SMSC9218I_RX_CFG_GET_DOFF(reg) SMSC9218I_GET_FIELD_8(reg, 8)
282
283/** @} */
284
285/**
286 * @name Transmit Configuration
287 * @{
288 */
289
290#define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15)
291#define SMSC9218I_TX_CFG_DDUMP SMSC9218I_FLAG(14)
292#define SMSC9218I_TX_CFG_SAO SMSC9218I_FLAG(2)
293#define SMSC9218I_TX_CFG_ON SMSC9218I_FLAG(1)
294#define SMSC9218I_TX_CFG_STOP SMSC9218I_FLAG(0)
295
296/** @} */
297
298/**
299 * @name Hardware Configuration
300 * @{
301 */
302
303#define SMSC9218I_HW_CFG_LED_3 SMSC9218I_FLAG(30)
304#define SMSC9218I_HW_CFG_LED_2 SMSC9218I_FLAG(29)
305#define SMSC9218I_HW_CFG_LED_1 SMSC9218I_FLAG(28)
306#define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24)
307#define SMSC9218I_HW_CFG_MBO SMSC9218I_FLAG(20)
308#define SMSC9218I_HW_CFG_TX_FIF_SZ(val) SMSC9218I_FIELD_8(val, 16)
309#define SMSC9218I_HW_CFG_GET_TX_FIF_SZ(reg) SMSC9218I_GET_FIELD_8(reg, 16)
310#define SMSC9218I_HW_CFG_BITMD_32 SMSC9218I_FLAG(2)
311#define SMSC9218I_HW_CFG_SRST_TO SMSC9218I_FLAG(1)
312#define SMSC9218I_HW_CFG_SRST SMSC9218I_FLAG(0)
313
314/** @} */
315
316/**
317 * @name Receive Datapath Control
318 * @{
319 */
320
321#define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31)
322
323/** @} */
324
325/**
326 * @name Receive FIFO Information
327 * @{
328 */
329
330#define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
331#define SMSC9218I_RX_FIFO_INF_GET_DUSED(reg) SMSC9218I_GET_FIELD_16(reg, 0)
332
333/** @} */
334
335/**
336 * @name Transmit FIFO Information
337 * @{
338 */
339
340#define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
341#define SMSC9218I_TX_FIFO_INF_GET_FREE(reg) SMSC9218I_GET_FIELD_16(reg, 0)
342
343/** @} */
344
345/**
346 * @name Power Management Control
347 * @{
348 */
349
350#define SMSC9218I_PMT_CTRL_PM_MODE_D0 0
351#define SMSC9218I_PMT_CTRL_PM_MODE_D1 SMSC9218I_FLAG(12)
352#define SMSC9218I_PMT_CTRL_PM_MODE_D2 SMSC9218I_FLAG(13)
353#define SMSC9218I_PMT_CTRL_PHY_RST SMSC9218I_FLAG(10)
354#define SMSC9218I_PMT_CTRL_WOL_EN SMSC9218I_FLAG(9)
355#define SMSC9218I_PMT_CTRL_ED_EN SMSC9218I_FLAG(8)
356#define SMSC9218I_PMT_CTRL_PME_TYPE_PUPU SMSC9218I_FLAG(6)
357#define SMSC9218I_PMT_CTRL_WUPS_NO 0
358#define SMSC9218I_PMT_CTRL_WUPS_ENERGY SMSC9218I_FLAG(4)
359#define SMSC9218I_PMT_CTRL_WUPS_MAGIC SMSC9218I_FLAG(5)
360#define SMSC9218I_PMT_CTRL_PME_IND SMSC9218I_FLAG(3)
361#define SMSC9218I_PMT_CTRL_PME_POL SMSC9218I_FLAG(2)
362#define SMSC9218I_PMT_CTRL_PME_EN SMSC9218I_FLAG(1)
363#define SMSC9218I_PMT_CTRL_READY SMSC9218I_FLAG(0)
364
365/** @} */
366
367/**
368 * @name General Purpose IO Configuration
369 * @{
370 */
371
372#define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30)
373#define SMSC9218I_GPIO_CFG_LED2 SMSC9218I_FLAG(29)
374#define SMSC9218I_GPIO_CFG_LED1 SMSC9218I_FLAG(28)
375#define SMSC9218I_GPIO_CFG_GPIO2_INT_POL SMSC9218I_FLAG(26)
376#define SMSC9218I_GPIO_CFG_GPIO1_INT_POL SMSC9218I_FLAG(25)
377#define SMSC9218I_GPIO_CFG_GPIO0_INT_POL SMSC9218I_FLAG(24)
378#define SMSC9218I_GPIO_CFG_GPIOBUF2 SMSC9218I_FLAG(18)
379#define SMSC9218I_GPIO_CFG_GPIOBUF1 SMSC9218I_FLAG(17)
380#define SMSC9218I_GPIO_CFG_GPIOBUF0 SMSC9218I_FLAG(16)
381#define SMSC9218I_GPIO_CFG_GPIODIR2 SMSC9218I_FLAG(10)
382#define SMSC9218I_GPIO_CFG_GPIODIR1 SMSC9218I_FLAG(9)
383#define SMSC9218I_GPIO_CFG_GPIODIR0 SMSC9218I_FLAG(8)
384#define SMSC9218I_GPIO_CFG_GPO4 SMSC9218I_FLAG(4)
385#define SMSC9218I_GPIO_CFG_GPO3 SMSC9218I_FLAG(3)
386#define SMSC9218I_GPIO_CFG_GPIO0 SMSC9218I_FLAG(0)
387#define SMSC9218I_GPIO_CFG_GPIO2 SMSC9218I_FLAG(2)
388#define SMSC9218I_GPIO_CFG_GPIO1 SMSC9218I_FLAG(1)
389
390/** @} */
391
392/**
393 * @name General Purpose Timer Configuration
394 * @{
395 */
396
397#define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29)
398#define SMSC9218I_GPT_CFG_LOAD(val) SMSC9218I_FIELD_16(val, 0)
399#define SMSC9218I_GPT_CFG_GET_LOAD(reg) SMSC9218I_GET_FIELD_16(reg, 0)
400
401/** @} */
402
403/**
404 * @name General Purpose Timer Count
405 * @{
406 */
407
408#define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0)
409
410/** @} */
411
412/**
413 * @name Word Swap
414 * @{
415 */
416
417#define SMSC9218I_ENDIAN_BIG 0xffffffffU
418
419/** @} */
420
421/**
422 * @name Free Run Counter
423 * @{
424 */
425
426#define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg)
427
428/** @} */
429
430/**
431 * @name Receiver Dropped Frames Counter
432 * @{
433 */
434
435#define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg)
436
437/** @} */
438
439/**
440 * @name EEPROM Command Register
441 * @{
442 */
443
444#define SMSC9218I_E2P_CMD_EPC_BUSY SMSC9218I_FLAG(31)
445
446/** @} */
447
448/**
449 * @name MAC Control and Status Synchronizer Command
450 * @{
451 */
452
453#define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31)
454#define SMSC9218I_MAC_CSR_CMD_READ SMSC9218I_FLAG(30)
455#define SMSC9218I_MAC_CSR_CMD_ADDR(val) SMSC9218I_FIELD_8(val, 0)
456#define SMSC9218I_MAC_CSR_CMD_GET_ADDR(reg) SMSC9218I_GET_FIELD_8(reg, 0)
457
458/** @} */
459
460/**
461 * @name MAC Control Register
462 * @{
463 */
464
465#define SMSC9218I_MAC_CR 0x00000001U
466#define SMSC9218I_MAC_CR_RXALL 0x80000000U
467#define SMSC9218I_MAC_CR_HBDIS 0x10000000U
468#define SMSC9218I_MAC_CR_RCVOWN 0x00800000U
469#define SMSC9218I_MAC_CR_LOOPBK 0x00200000U
470#define SMSC9218I_MAC_CR_FDPX 0x00100000U
471#define SMSC9218I_MAC_CR_MCPAS 0x00080000U
472#define SMSC9218I_MAC_CR_PRMS 0x00040000U
473#define SMSC9218I_MAC_CR_INVFILT 0x00020000U
474#define SMSC9218I_MAC_CR_PASSBAD 0x00010000U
475#define SMSC9218I_MAC_CR_HFILT 0x00008000U
476#define SMSC9218I_MAC_CR_HPFILT 0x00002000U
477#define SMSC9218I_MAC_CR_LCOLL 0x00001000U
478#define SMSC9218I_MAC_CR_BCAST 0x00000800U
479#define SMSC9218I_MAC_CR_DISRTY 0x00000400U
480#define SMSC9218I_MAC_CR_PADSTR 0x00000100U
481#define SMSC9218I_MAC_CR_BOLMT_MASK 0x000000c0U
482#define SMSC9218I_MAC_CR_BOLMT_10 0x00000000U
483#define SMSC9218I_MAC_CR_BOLMT_8 0x00000040U
484#define SMSC9218I_MAC_CR_BOLMT_4 0x00000080U
485#define SMSC9218I_MAC_CR_BOLMT_1 0x000000c0U
486#define SMSC9218I_MAC_CR_DFCHK 0x00000020U
487#define SMSC9218I_MAC_CR_TXEN 0x00000008U
488#define SMSC9218I_MAC_CR_RXEN 0x00000004U
489
490/** @} */
491
492/**
493 * @name MAC Address High
494 * @{
495 */
496
497#define SMSC9218I_MAC_ADDRH 0x00000002U
498#define SMSC9218I_MAC_ADDRH_MASK 0x0000ffffU
499
500/** @} */
501
502/**
503 * @name MAC Address Low
504 * @{
505 */
506
507#define SMSC9218I_MAC_ADDRL 0x00000003U
508#define SMSC9218I_MAC_ADDRL_MASK 0xffffffffU
509
510/** @} */
511
512/**
513 * @name Multicast Hash Table High
514 * @{
515 */
516
517#define SMSC9218I_MAC_HASHH 0x00000004U
518#define SMSC9218I_MAC_HASHH_MASK 0xffffffffU
519
520/** @} */
521
522/**
523 * @name Multicast Hash Table Low
524 * @{
525 */
526
527#define SMSC9218I_MAC_HASHL 0x00000005U
528#define SMSC9218I_MAC_HASHL_MASK 0xffffffffU
529
530/** @} */
531
532/**
533 * @name MII Access
534 * @{
535 */
536
537#define SMSC9218I_MAC_MII_ACC 0x00000006U
538#define SMSC9218I_MAC_MII_ACC_PHY_DEFAULT (1U << 11)
539#define SMSC9218I_MAC_MII_ACC_WRITE (1U << 1)
540#define SMSC9218I_MAC_MII_ACC_BUSY (1U << 0)
541#define SMSC9218I_MAC_MII_ACC_ADDR(addr) ((addr) << 6)
542
543/** @} */
544
545/**
546 * @name MII Data
547 * @{
548 */
549
550#define SMSC9218I_MAC_MII_DATA 0x00000007U
551
552/** @} */
553
554/**
555 * @name Flow Control
556 * @{
557 */
558
559#define SMSC9218I_MAC_FLOW 0x00000008U
560#define SMSC9218I_MAC_FLOW_FCPT_MASK 0xffff0000U
561#define SMSC9218I_MAC_FLOW_FCPASS 0x00000004U
562#define SMSC9218I_MAC_FLOW_FCEN 0x00000002U
563#define SMSC9218I_MAC_FLOW_FCBSY 0x00000001U
564
565/** @} */
566
567/**
568 * @name VLAN1 Tag
569 * @{
570 */
571
572#define SMSC9218I_MAC_VLAN1 0x00000009U
573
574/** @} */
575
576/**
577 * @name VLAN2 Tag
578 * @{
579 */
580
581#define SMSC9218I_MAC_VLAN2 0x0000000aU
582
583/** @} */
584
585/**
586 * @name Wake-up Frame Filter
587 * @{
588 */
589
590#define SMSC9218I_MAC_WUFF 0x0000000bU
591
592/** @} */
593
594/**
595 * @name Wake-up Control and Status
596 * @{
597 */
598
599#define SMSC9218I_MAC_WUCSR 0x0000000cU
600#define SMSC9218I_MAC_WUCSR_GUE 0x00000200U
601#define SMSC9218I_MAC_WUCSR_WUFR 0x00000040U
602#define SMSC9218I_MAC_WUCSR_MPR 0x00000020U
603#define SMSC9218I_MAC_WUCSR_WUEN 0x00000004U
604#define SMSC9218I_MAC_WUCSR_MPEN 0x00000002U
605
606/** @} */
607
608/**
609 * @name PHY Identifier 1
610 * @{
611 */
612
613#define SMSC9218I_PHY_ID1_LAN9118 0x7
614
615/** @} */
616
617/**
618 * @name PHY Identifier 2
619 * @{
620 */
621
622#define SMSC9218I_PHY_ID2_LAN9218 0xc0c3
623
624/** @} */
625
626/**
627 * @name Mode Control and Status
628 * @{
629 */
630
631#define SMSC9218I_PHY_MCSR 0x00000011U
632#define SMSC9218I_PHY_MCSR_EDPWRDOWN 0x00002000U
633#define SMSC9218I_PHY_MCSR_ENERGYON 0x00000002U
634
635/** @} */
636
637/**
638 * @name Special Modes
639 * @{
640 */
641
642#define SMSC9218I_PHY_SPMODES 0x00000012U
643
644/** @} */
645
646/**
647 * @name Special Control and Status Indications
648 * @{
649 */
650
651#define SMSC9218I_PHY_CSIR 0x0000001bU
652#define SMSC9218I_PHY_CSIR_SQEOFF 0x00000800U
653#define SMSC9218I_PHY_CSIR_FEFIEN 0x00000020U
654#define SMSC9218I_PHY_CSIR_XPOL 0x00000010U
655
656/** @} */
657
658/**
659 * @name Interrupt Source Flag
660 * @{
661 */
662
663#define SMSC9218I_PHY_ISR 0x0000001dU
664#define SMSC9218I_PHY_ISR_INT7 0x00000080U
665#define SMSC9218I_PHY_ISR_INT6 0x00000040U
666#define SMSC9218I_PHY_ISR_INT5 0x00000020U
667#define SMSC9218I_PHY_ISR_INT4 0x00000010U
668#define SMSC9218I_PHY_ISR_INT3 0x00000008U
669#define SMSC9218I_PHY_ISR_INT2 0x00000004U
670#define SMSC9218I_PHY_ISR_INT1 0x00000002U
671
672/** @} */
673
674/**
675 * @name Interrupt Mask
676 * @{
677 */
678
679#define SMSC9218I_PHY_IMR 0x0000001eU
680#define SMSC9218I_PHY_IMR_INT7 0x00000080U
681#define SMSC9218I_PHY_IMR_INT6 0x00000040U
682#define SMSC9218I_PHY_IMR_INT5 0x00000020U
683#define SMSC9218I_PHY_IMR_INT4 0x00000010U
684#define SMSC9218I_PHY_IMR_INT3 0x00000008U
685#define SMSC9218I_PHY_IMR_INT2 0x00000004U
686#define SMSC9218I_PHY_IMR_INT1 0x00000002U
687
688/** @} */
689
690/**
691 * @name PHY Special Control and Status
692 * @{
693 */
694
695#define SMSC9218I_PHY_PHYSCSR 0x0000001fU
696#define SMSC9218I_PHY_PHYSCSR_ANDONE 0x00001000U
697#define SMSC9218I_PHY_PHYSCSR_4B5B_EN 0x00000040U
698#define SMSC9218I_PHY_PHYSCSR_SPEED_MASK 0x0000001cU
699#define SMSC9218I_PHY_PHYSCSR_SPEED_10HD 0x00000004U
700#define SMSC9218I_PHY_PHYSCSR_SPEED_10FD 0x00000014U
701#define SMSC9218I_PHY_PHYSCSR_SPEED_100HD 0x00000008U
702#define SMSC9218I_PHY_PHYSCSR_SPEED_100FD 0x00000018U
703
704/** @} */
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