[d374492] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup mpc55xx |
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| 5 | * |
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| 6 | * @brief SMSC - LAN9218i |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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[86c5b1c] | 10 | * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. |
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| 11 | * |
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| 12 | * embedded brains GmbH |
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| 13 | * Obere Lagerstr. 30 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <rtems@embedded-brains.de> |
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[d374492] | 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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[c499856] | 20 | * http://www.rtems.org/license/LICENSE. |
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[d374492] | 21 | */ |
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| 22 | |
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[86c5b1c] | 23 | #include <bsp.h> |
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| 24 | |
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[d374492] | 25 | /** |
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| 26 | * @name Memory Map |
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[ac7af4a] | 27 | * @{ |
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[d374492] | 28 | */ |
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| 29 | |
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| 30 | typedef struct { |
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| 31 | uint32_t rx_fifo_data; |
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| 32 | uint32_t rx_fifo_data_aliases [7]; |
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| 33 | uint32_t tx_fifo_data; |
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| 34 | uint32_t tx_fifo_data_aliases [7]; |
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| 35 | uint32_t rx_fifo_status; |
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| 36 | uint32_t rx_fifo_status_peek; |
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| 37 | uint32_t tx_fifo_status; |
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| 38 | uint32_t tx_fifo_status_peek; |
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| 39 | uint32_t id_rev; |
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| 40 | uint32_t irq_cfg; |
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| 41 | uint32_t int_sts; |
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| 42 | uint32_t int_en; |
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| 43 | uint32_t reserved_0; |
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| 44 | uint32_t byte_test; |
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| 45 | uint32_t fifo_int; |
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| 46 | uint32_t rx_cfg; |
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| 47 | uint32_t tx_cfg; |
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| 48 | uint32_t hw_cfg; |
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| 49 | uint32_t rx_dp_ctl; |
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| 50 | uint32_t rx_fifo_inf; |
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| 51 | uint32_t tx_fifo_inf; |
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| 52 | uint32_t pmt_ctrl; |
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| 53 | uint32_t gpio_cfg; |
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| 54 | uint32_t gpt_cfg; |
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| 55 | uint32_t gpt_cnt; |
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| 56 | uint32_t reserved_1; |
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| 57 | uint32_t word_swap; |
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| 58 | uint32_t free_run; |
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| 59 | uint32_t rx_drop; |
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| 60 | uint32_t mac_csr_cmd; |
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| 61 | uint32_t mac_csr_data; |
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| 62 | uint32_t afc_cfg; |
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| 63 | uint32_t e2p_cmd; |
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| 64 | uint32_t e2p_data; |
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| 65 | } smsc9218i_registers; |
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| 66 | |
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[86c5b1c] | 67 | /* |
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| 68 | * SMSC9218 registers are accessed little-endian (address 0x3fff8000, A22 used |
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| 69 | * as END_SEL). |
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| 70 | */ |
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| 71 | #ifdef SMSC9218I_BIG_ENDIAN_SUPPORT |
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| 72 | volatile smsc9218i_registers *const smsc9218i = |
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[f9fe954] | 73 | (volatile smsc9218i_registers *) 0x3fff8000; |
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| 74 | volatile smsc9218i_registers *const smsc9218i_dma = |
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[86c5b1c] | 75 | (volatile smsc9218i_registers *) 0x3fff8200; |
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| 76 | #else |
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| 77 | volatile smsc9218i_registers *const smsc9218i = |
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| 78 | (volatile smsc9218i_registers *) 0x3fff8000; |
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[f9fe954] | 79 | volatile smsc9218i_registers *const smsc9218i_dma = |
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| 80 | (volatile smsc9218i_registers *) 0x3fff8000; |
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[86c5b1c] | 81 | #endif |
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[d374492] | 82 | |
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| 83 | /** @} */ |
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| 84 | |
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[86c5b1c] | 85 | #ifdef SMSC9218I_BIG_ENDIAN_SUPPORT |
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[f9fe954] | 86 | #define SMSC9218I_BIT_POS(pos) (pos) |
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| 87 | #else |
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[86c5b1c] | 88 | #define SMSC9218I_BIT_POS(pos) \ |
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| 89 | ((pos) > 15 ? \ |
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| 90 | ((pos) > 23 ? (pos) - 24 : (pos) - 8) \ |
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| 91 | : ((pos) > 7 ? (pos) + 8 : (pos) + 24)) |
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| 92 | #endif |
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[d374492] | 93 | |
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| 94 | #define SMSC9218I_FLAG(pos) \ |
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| 95 | (1U << SMSC9218I_BIT_POS(pos)) |
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| 96 | |
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| 97 | #define SMSC9218I_FIELD_8(val, pos) \ |
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| 98 | (((val) & 0xff) << SMSC9218I_BIT_POS(pos)) |
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| 99 | |
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| 100 | #define SMSC9218I_GET_FIELD_8(reg, pos) \ |
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| 101 | (((reg) >> SMSC9218I_BIT_POS(pos)) & 0xff) |
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| 102 | |
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| 103 | #define SMSC9218I_FIELD_16(val, pos) \ |
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| 104 | (SMSC9218I_FIELD_8((val) >> 8, (pos) + 8) \ |
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| 105 | | SMSC9218I_FIELD_8((val), pos)) |
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| 106 | |
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| 107 | #define SMSC9218I_GET_FIELD_16(reg, pos) \ |
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| 108 | ((SMSC9218I_GET_FIELD_8(reg, (pos) + 8) << 8) \ |
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| 109 | | SMSC9218I_GET_FIELD_8(reg, pos)) |
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| 110 | |
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[86c5b1c] | 111 | #ifdef SMSC9218I_BIG_ENDIAN_SUPPORT |
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[f9fe954] | 112 | #define SMSC9218I_SWAP(val) (val) |
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| 113 | #else |
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[86c5b1c] | 114 | #define SMSC9218I_SWAP(val) \ |
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| 115 | ((((val) >> 24) & 0xff) \ |
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| 116 | | ((((val) >> 16) & 0xff) << 8) \ |
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| 117 | | ((((val) >> 8) & 0xff) << 16) \ |
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| 118 | | (((val) & 0xff) << 24)) |
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| 119 | #endif |
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[d374492] | 120 | |
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| 121 | /** |
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| 122 | * @name Receive Status |
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[ac7af4a] | 123 | * @{ |
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[d374492] | 124 | */ |
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| 125 | |
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| 126 | #define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30) |
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| 127 | #define SMSC9218I_RX_STS_GET_LENGTH(reg) (SMSC9218I_GET_FIELD_16(reg, 16) & 0x3fff) |
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| 128 | #define SMSC9218I_RX_STS_ERROR SMSC9218I_FLAG(15) |
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| 129 | #define SMSC9218I_RX_STS_BROADCAST SMSC9218I_FLAG(13) |
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| 130 | #define SMSC9218I_RX_STS_ERROR_LENGTH SMSC9218I_FLAG(12) |
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| 131 | #define SMSC9218I_RX_STS_ERROR_RUNT_FRAME SMSC9218I_FLAG(11) |
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| 132 | #define SMSC9218I_RX_STS_MULTICAST SMSC9218I_FLAG(10) |
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| 133 | #define SMSC9218I_RX_STS_ERROR_TOO_LONG SMSC9218I_FLAG(7) |
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| 134 | #define SMSC9218I_RX_STS_ERROR_COLLISION SMSC9218I_FLAG(6) |
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| 135 | #define SMSC9218I_RX_STS_TYPE SMSC9218I_FLAG(5) |
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| 136 | #define SMSC9218I_RX_STS_WATCHDOG SMSC9218I_FLAG(4) |
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| 137 | #define SMSC9218I_RX_STS_ERROR_MII SMSC9218I_FLAG(3) |
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| 138 | #define SMSC9218I_RX_STS_DRIBBLING_BIT SMSC9218I_FLAG(2) |
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| 139 | #define SMSC9218I_RX_STS_ERROR_CRC SMSC9218I_FLAG(1) |
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| 140 | |
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| 141 | /** @} */ |
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| 142 | |
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| 143 | /** |
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| 144 | * @name Transmit Status |
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[ac7af4a] | 145 | * @{ |
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[d374492] | 146 | */ |
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| 147 | |
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| 148 | #define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16) |
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| 149 | #define SMSC9218I_TX_STS_ERROR SMSC9218I_FLAG(15) |
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| 150 | #define SMSC9218I_TX_STS_ERROR_LOSS_OF_CARRIER SMSC9218I_FLAG(11) |
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| 151 | #define SMSC9218I_TX_STS_ERROR_NO_CARRIER SMSC9218I_FLAG(10) |
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| 152 | #define SMSC9218I_TX_STS_ERROR_LATE_COLLISION SMSC9218I_FLAG(9) |
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| 153 | #define SMSC9218I_TX_STS_ERROR_EXCESSIVE_COLLISIONS SMSC9218I_FLAG(8) |
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| 154 | #define SMSC9218I_TX_STS_ERROR_EXCESSIVE_DEFERRAL SMSC9218I_FLAG(2) |
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| 155 | #define SMSC9218I_TX_STS_ERROR_DEFERRED SMSC9218I_FLAG(0) |
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| 156 | |
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| 157 | /** @} */ |
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| 158 | |
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| 159 | /** |
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| 160 | * @name Transmit Command A |
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[ac7af4a] | 161 | * @{ |
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[d374492] | 162 | */ |
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| 163 | |
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| 164 | #define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31) |
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| 165 | #define SMSC9218I_TX_A_END_ALIGN_4 0 |
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| 166 | #define SMSC9218I_TX_A_END_ALIGN_16 SMSC9218I_FLAG(24) |
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| 167 | #define SMSC9218I_TX_A_END_ALIGN_32 SMSC9218I_FLAG(25) |
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| 168 | #define SMSC9218I_TX_A_DOFF(val) SMSC9218I_FIELD_8(val, 16) |
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| 169 | #define SMSC9218I_TX_A_FIRST SMSC9218I_FLAG(13) |
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| 170 | #define SMSC9218I_TX_A_LAST SMSC9218I_FLAG(12) |
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| 171 | #define SMSC9218I_TX_A_FRAGMENT_LENGTH(val) SMSC9218I_FIELD_16(val, 0) |
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| 172 | |
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| 173 | /** @} */ |
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| 174 | |
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| 175 | /** |
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| 176 | * @name Transmit Command B |
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[ac7af4a] | 177 | * @{ |
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[d374492] | 178 | */ |
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| 179 | |
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| 180 | #define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16) |
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| 181 | #define SMSC9218I_TX_B_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16) |
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| 182 | #define SMSC9218I_TX_B_DISABLE_CRC SMSC9218I_FLAG(13) |
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| 183 | #define SMSC9218I_TX_B_DISABLE_PAD SMSC9218I_FLAG(12) |
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| 184 | #define SMSC9218I_TX_B_FRAME_LENGTH(val) SMSC9218I_FIELD_16(val, 0) |
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| 185 | |
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| 186 | /** @} */ |
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| 187 | |
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| 188 | /** |
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| 189 | * @name Chip ID and Revision |
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[ac7af4a] | 190 | * @{ |
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[d374492] | 191 | */ |
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| 192 | |
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| 193 | #define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16) |
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| 194 | #define SMSC9218I_ID_REV_GET_REV(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
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| 195 | #define SMSC9218I_ID_REV_ID_CHIP_118 0x0118U |
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| 196 | #define SMSC9218I_ID_REV_ID_CHIP_218 0x118aU |
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| 197 | |
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| 198 | /** @} */ |
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| 199 | |
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| 200 | /** |
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| 201 | * @name Interrupt Configuration |
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[ac7af4a] | 202 | * @{ |
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[d374492] | 203 | */ |
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| 204 | |
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| 205 | #define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24) |
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| 206 | #define SMSC9218I_IRQ_CFG_GET_INT_DEAS(reg) SMSC9218I_GET_FIELD_8(reg, 24) |
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| 207 | #define SMSC9218I_IRQ_CFG_INT_DEAS_CLR SMSC9218I_FLAG(14) |
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| 208 | #define SMSC9218I_IRQ_CFG_INT_DEAS_STS SMSC9218I_FLAG(13) |
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| 209 | #define SMSC9218I_IRQ_CFG_IRQ_INT SMSC9218I_FLAG(12) |
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| 210 | #define SMSC9218I_IRQ_CFG_IRQ_EN SMSC9218I_FLAG(8) |
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| 211 | #define SMSC9218I_IRQ_CFG_IRQ_POL SMSC9218I_FLAG(4) |
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| 212 | #define SMSC9218I_IRQ_CFG_IRQ_TYPE SMSC9218I_FLAG(0) |
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| 213 | |
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| 214 | /** @} */ |
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| 215 | |
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| 216 | /** |
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[a4475277] | 217 | * @name Interrupt Enable and Status |
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| 218 | * @{ |
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| 219 | */ |
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| 220 | |
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| 221 | #define SMSC9218I_INT_SW SMSC9218I_FLAG(31) |
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| 222 | #define SMSC9218I_INT_TXSTOP SMSC9218I_FLAG(25) |
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| 223 | #define SMSC9218I_INT_RXSTOP SMSC9218I_FLAG(24) |
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| 224 | #define SMSC9218I_INT_RXDFH SMSC9218I_FLAG(23) |
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| 225 | #define SMSC9218I_INT_TIOC SMSC9218I_FLAG(21) |
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| 226 | #define SMSC9218I_INT_RXD SMSC9218I_FLAG(20) |
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| 227 | #define SMSC9218I_INT_GPT SMSC9218I_FLAG(19) |
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| 228 | #define SMSC9218I_INT_PHY SMSC9218I_FLAG(18) |
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| 229 | #define SMSC9218I_INT_PME SMSC9218I_FLAG(17) |
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| 230 | #define SMSC9218I_INT_TXSO SMSC9218I_FLAG(16) |
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| 231 | #define SMSC9218I_INT_RWT SMSC9218I_FLAG(15) |
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| 232 | #define SMSC9218I_INT_RXE SMSC9218I_FLAG(14) |
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| 233 | #define SMSC9218I_INT_TXE SMSC9218I_FLAG(13) |
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| 234 | #define SMSC9218I_INT_TDFO SMSC9218I_FLAG(10) |
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| 235 | #define SMSC9218I_INT_TDFA SMSC9218I_FLAG(9) |
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| 236 | #define SMSC9218I_INT_TSFF SMSC9218I_FLAG(8) |
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| 237 | #define SMSC9218I_INT_TSFL SMSC9218I_FLAG(7) |
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| 238 | #define SMSC9218I_INT_RSFF SMSC9218I_FLAG(4) |
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| 239 | #define SMSC9218I_INT_RSFL SMSC9218I_FLAG(3) |
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| 240 | #define SMSC9218I_INT_GPIO2 SMSC9218I_FLAG(2) |
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| 241 | #define SMSC9218I_INT_GPIO1 SMSC9218I_FLAG(1) |
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| 242 | #define SMSC9218I_INT_GPIO0 SMSC9218I_FLAG(0) |
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[d374492] | 243 | |
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| 244 | /** @} */ |
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| 245 | |
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| 246 | /** |
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| 247 | * @name Byte Order Testing |
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[ac7af4a] | 248 | * @{ |
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[d374492] | 249 | */ |
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| 250 | |
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| 251 | #define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U) |
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| 252 | |
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| 253 | /** @} */ |
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| 254 | |
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| 255 | /** |
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| 256 | * @name FIFO Level Interrupts |
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[ac7af4a] | 257 | * @{ |
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[d374492] | 258 | */ |
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| 259 | |
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| 260 | #define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24) |
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| 261 | #define SMSC9218I_FIFO_INT_GET_TDAL(reg) SMSC9218I_GET_FIELD_8(reg, 24) |
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| 262 | #define SMSC9218I_FIFO_INT_TSL(val) SMSC9218I_FIELD_8(val, 16) |
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| 263 | #define SMSC9218I_FIFO_INT_GET_TSL(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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| 264 | #define SMSC9218I_FIFO_INT_RSL(val) SMSC9218I_FIELD_8(val, 0) |
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| 265 | #define SMSC9218I_FIFO_INT_GET_RSL(reg) SMSC9218I_GET_FIELD_8(reg, 0) |
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| 266 | |
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| 267 | /** @} */ |
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| 268 | |
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| 269 | /** |
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| 270 | * @name Receive Configuration |
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[ac7af4a] | 271 | * @{ |
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[d374492] | 272 | */ |
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| 273 | |
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| 274 | #define SMSC9218I_RX_CFG_END_ALIGN_4 0 |
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| 275 | #define SMSC9218I_RX_CFG_END_ALIGN_16 SMSC9218I_FLAG(30) |
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| 276 | #define SMSC9218I_RX_CFG_END_ALIGN_32 SMSC9218I_FLAG(31) |
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| 277 | #define SMSC9218I_RX_CFG_DMA_CNT(val) SMSC9218I_FIELD_8(val, 24) |
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| 278 | #define SMSC9218I_RX_CFG_GET_DMA_CNT(reg) SMSC9218I_GET_FIELD_8(reg, 24) |
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| 279 | #define SMSC9218I_RX_CFG_DUMP SMSC9218I_FLAG(15) |
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| 280 | #define SMSC9218I_RX_CFG_DOFF(val) SMSC9218I_FIELD_8(val, 8) |
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| 281 | #define SMSC9218I_RX_CFG_GET_DOFF(reg) SMSC9218I_GET_FIELD_8(reg, 8) |
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| 282 | |
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| 283 | /** @} */ |
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| 284 | |
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| 285 | /** |
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| 286 | * @name Transmit Configuration |
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[ac7af4a] | 287 | * @{ |
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[d374492] | 288 | */ |
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| 289 | |
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| 290 | #define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15) |
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| 291 | #define SMSC9218I_TX_CFG_DDUMP SMSC9218I_FLAG(14) |
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| 292 | #define SMSC9218I_TX_CFG_SAO SMSC9218I_FLAG(2) |
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| 293 | #define SMSC9218I_TX_CFG_ON SMSC9218I_FLAG(1) |
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| 294 | #define SMSC9218I_TX_CFG_STOP SMSC9218I_FLAG(0) |
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| 295 | |
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| 296 | /** @} */ |
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| 297 | |
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| 298 | /** |
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| 299 | * @name Hardware Configuration |
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[ac7af4a] | 300 | * @{ |
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[d374492] | 301 | */ |
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| 302 | |
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[dec7231] | 303 | #define SMSC9218I_HW_CFG_LED_3 SMSC9218I_FLAG(30) |
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| 304 | #define SMSC9218I_HW_CFG_LED_2 SMSC9218I_FLAG(29) |
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| 305 | #define SMSC9218I_HW_CFG_LED_1 SMSC9218I_FLAG(28) |
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[d374492] | 306 | #define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24) |
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| 307 | #define SMSC9218I_HW_CFG_MBO SMSC9218I_FLAG(20) |
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| 308 | #define SMSC9218I_HW_CFG_TX_FIF_SZ(val) SMSC9218I_FIELD_8(val, 16) |
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| 309 | #define SMSC9218I_HW_CFG_GET_TX_FIF_SZ(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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| 310 | #define SMSC9218I_HW_CFG_BITMD_32 SMSC9218I_FLAG(2) |
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| 311 | #define SMSC9218I_HW_CFG_SRST_TO SMSC9218I_FLAG(1) |
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| 312 | #define SMSC9218I_HW_CFG_SRST SMSC9218I_FLAG(0) |
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| 313 | |
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| 314 | /** @} */ |
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| 315 | |
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| 316 | /** |
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| 317 | * @name Receive Datapath Control |
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[ac7af4a] | 318 | * @{ |
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[d374492] | 319 | */ |
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| 320 | |
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| 321 | #define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31) |
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| 322 | |
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| 323 | /** @} */ |
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| 324 | |
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| 325 | /** |
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| 326 | * @name Receive FIFO Information |
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[ac7af4a] | 327 | * @{ |
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[d374492] | 328 | */ |
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| 329 | |
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| 330 | #define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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| 331 | #define SMSC9218I_RX_FIFO_INF_GET_DUSED(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
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| 332 | |
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| 333 | /** @} */ |
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| 334 | |
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| 335 | /** |
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| 336 | * @name Transmit FIFO Information |
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[ac7af4a] | 337 | * @{ |
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[d374492] | 338 | */ |
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| 339 | |
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| 340 | #define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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| 341 | #define SMSC9218I_TX_FIFO_INF_GET_FREE(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
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| 342 | |
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| 343 | /** @} */ |
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| 344 | |
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| 345 | /** |
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| 346 | * @name Power Management Control |
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[ac7af4a] | 347 | * @{ |
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[d374492] | 348 | */ |
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| 349 | |
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| 350 | #define SMSC9218I_PMT_CTRL_PM_MODE_D0 0 |
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| 351 | #define SMSC9218I_PMT_CTRL_PM_MODE_D1 SMSC9218I_FLAG(12) |
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| 352 | #define SMSC9218I_PMT_CTRL_PM_MODE_D2 SMSC9218I_FLAG(13) |
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| 353 | #define SMSC9218I_PMT_CTRL_PHY_RST SMSC9218I_FLAG(10) |
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| 354 | #define SMSC9218I_PMT_CTRL_WOL_EN SMSC9218I_FLAG(9) |
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| 355 | #define SMSC9218I_PMT_CTRL_ED_EN SMSC9218I_FLAG(8) |
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| 356 | #define SMSC9218I_PMT_CTRL_PME_TYPE_PUPU SMSC9218I_FLAG(6) |
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| 357 | #define SMSC9218I_PMT_CTRL_WUPS_NO 0 |
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| 358 | #define SMSC9218I_PMT_CTRL_WUPS_ENERGY SMSC9218I_FLAG(4) |
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| 359 | #define SMSC9218I_PMT_CTRL_WUPS_MAGIC SMSC9218I_FLAG(5) |
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| 360 | #define SMSC9218I_PMT_CTRL_PME_IND SMSC9218I_FLAG(3) |
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| 361 | #define SMSC9218I_PMT_CTRL_PME_POL SMSC9218I_FLAG(2) |
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| 362 | #define SMSC9218I_PMT_CTRL_PME_EN SMSC9218I_FLAG(1) |
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| 363 | #define SMSC9218I_PMT_CTRL_READY SMSC9218I_FLAG(0) |
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| 364 | |
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| 365 | /** @} */ |
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| 366 | |
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| 367 | /** |
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| 368 | * @name General Purpose IO Configuration |
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[ac7af4a] | 369 | * @{ |
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[d374492] | 370 | */ |
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| 371 | |
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| 372 | #define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30) |
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| 373 | #define SMSC9218I_GPIO_CFG_LED2 SMSC9218I_FLAG(29) |
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| 374 | #define SMSC9218I_GPIO_CFG_LED1 SMSC9218I_FLAG(28) |
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| 375 | #define SMSC9218I_GPIO_CFG_GPIO2_INT_POL SMSC9218I_FLAG(26) |
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| 376 | #define SMSC9218I_GPIO_CFG_GPIO1_INT_POL SMSC9218I_FLAG(25) |
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| 377 | #define SMSC9218I_GPIO_CFG_GPIO0_INT_POL SMSC9218I_FLAG(24) |
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| 378 | #define SMSC9218I_GPIO_CFG_GPIOBUF2 SMSC9218I_FLAG(18) |
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| 379 | #define SMSC9218I_GPIO_CFG_GPIOBUF1 SMSC9218I_FLAG(17) |
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| 380 | #define SMSC9218I_GPIO_CFG_GPIOBUF0 SMSC9218I_FLAG(16) |
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| 381 | #define SMSC9218I_GPIO_CFG_GPIODIR2 SMSC9218I_FLAG(10) |
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| 382 | #define SMSC9218I_GPIO_CFG_GPIODIR1 SMSC9218I_FLAG(9) |
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| 383 | #define SMSC9218I_GPIO_CFG_GPIODIR0 SMSC9218I_FLAG(8) |
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| 384 | #define SMSC9218I_GPIO_CFG_GPO4 SMSC9218I_FLAG(4) |
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| 385 | #define SMSC9218I_GPIO_CFG_GPO3 SMSC9218I_FLAG(3) |
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| 386 | #define SMSC9218I_GPIO_CFG_GPIO0 SMSC9218I_FLAG(0) |
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| 387 | #define SMSC9218I_GPIO_CFG_GPIO2 SMSC9218I_FLAG(2) |
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| 388 | #define SMSC9218I_GPIO_CFG_GPIO1 SMSC9218I_FLAG(1) |
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| 389 | |
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| 390 | /** @} */ |
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| 391 | |
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| 392 | /** |
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| 393 | * @name General Purpose Timer Configuration |
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[ac7af4a] | 394 | * @{ |
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[d374492] | 395 | */ |
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| 396 | |
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| 397 | #define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29) |
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| 398 | #define SMSC9218I_GPT_CFG_LOAD(val) SMSC9218I_FIELD_16(val, 0) |
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| 399 | #define SMSC9218I_GPT_CFG_GET_LOAD(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
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| 400 | |
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| 401 | /** @} */ |
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| 402 | |
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| 403 | /** |
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| 404 | * @name General Purpose Timer Count |
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[ac7af4a] | 405 | * @{ |
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[d374492] | 406 | */ |
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| 407 | |
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| 408 | #define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0) |
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| 409 | |
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| 410 | /** @} */ |
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| 411 | |
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| 412 | /** |
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| 413 | * @name Word Swap |
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[ac7af4a] | 414 | * @{ |
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[d374492] | 415 | */ |
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| 416 | |
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| 417 | #define SMSC9218I_ENDIAN_BIG 0xffffffffU |
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| 418 | |
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| 419 | /** @} */ |
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| 420 | |
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| 421 | /** |
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| 422 | * @name Free Run Counter |
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[ac7af4a] | 423 | * @{ |
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[d374492] | 424 | */ |
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| 425 | |
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| 426 | #define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg) |
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| 427 | |
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| 428 | /** @} */ |
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| 429 | |
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| 430 | /** |
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| 431 | * @name Receiver Dropped Frames Counter |
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[ac7af4a] | 432 | * @{ |
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[d374492] | 433 | */ |
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| 434 | |
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| 435 | #define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg) |
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| 436 | |
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| 437 | /** @} */ |
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| 438 | |
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[a4475277] | 439 | /** |
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| 440 | * @name EEPROM Command Register |
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| 441 | * @{ |
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| 442 | */ |
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| 443 | |
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| 444 | #define SMSC9218I_E2P_CMD_EPC_BUSY SMSC9218I_FLAG(31) |
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| 445 | |
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| 446 | /** @} */ |
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| 447 | |
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[d374492] | 448 | /** |
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| 449 | * @name MAC Control and Status Synchronizer Command |
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[ac7af4a] | 450 | * @{ |
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[d374492] | 451 | */ |
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| 452 | |
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| 453 | #define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31) |
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| 454 | #define SMSC9218I_MAC_CSR_CMD_READ SMSC9218I_FLAG(30) |
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| 455 | #define SMSC9218I_MAC_CSR_CMD_ADDR(val) SMSC9218I_FIELD_8(val, 0) |
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| 456 | #define SMSC9218I_MAC_CSR_CMD_GET_ADDR(reg) SMSC9218I_GET_FIELD_8(reg, 0) |
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| 457 | |
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| 458 | /** @} */ |
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| 459 | |
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| 460 | /** |
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| 461 | * @name MAC Control Register |
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[ac7af4a] | 462 | * @{ |
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[d374492] | 463 | */ |
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| 464 | |
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| 465 | #define SMSC9218I_MAC_CR 0x00000001U |
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| 466 | #define SMSC9218I_MAC_CR_RXALL 0x80000000U |
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| 467 | #define SMSC9218I_MAC_CR_HBDIS 0x10000000U |
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| 468 | #define SMSC9218I_MAC_CR_RCVOWN 0x00800000U |
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| 469 | #define SMSC9218I_MAC_CR_LOOPBK 0x00200000U |
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| 470 | #define SMSC9218I_MAC_CR_FDPX 0x00100000U |
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| 471 | #define SMSC9218I_MAC_CR_MCPAS 0x00080000U |
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| 472 | #define SMSC9218I_MAC_CR_PRMS 0x00040000U |
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| 473 | #define SMSC9218I_MAC_CR_INVFILT 0x00020000U |
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| 474 | #define SMSC9218I_MAC_CR_PASSBAD 0x00010000U |
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| 475 | #define SMSC9218I_MAC_CR_HFILT 0x00008000U |
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| 476 | #define SMSC9218I_MAC_CR_HPFILT 0x00002000U |
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| 477 | #define SMSC9218I_MAC_CR_LCOLL 0x00001000U |
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| 478 | #define SMSC9218I_MAC_CR_BCAST 0x00000800U |
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| 479 | #define SMSC9218I_MAC_CR_DISRTY 0x00000400U |
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| 480 | #define SMSC9218I_MAC_CR_PADSTR 0x00000100U |
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| 481 | #define SMSC9218I_MAC_CR_BOLMT_MASK 0x000000c0U |
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| 482 | #define SMSC9218I_MAC_CR_BOLMT_10 0x00000000U |
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| 483 | #define SMSC9218I_MAC_CR_BOLMT_8 0x00000040U |
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| 484 | #define SMSC9218I_MAC_CR_BOLMT_4 0x00000080U |
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| 485 | #define SMSC9218I_MAC_CR_BOLMT_1 0x000000c0U |
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| 486 | #define SMSC9218I_MAC_CR_DFCHK 0x00000020U |
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| 487 | #define SMSC9218I_MAC_CR_TXEN 0x00000008U |
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| 488 | #define SMSC9218I_MAC_CR_RXEN 0x00000004U |
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| 489 | |
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| 490 | /** @} */ |
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| 491 | |
---|
| 492 | /** |
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| 493 | * @name MAC Address High |
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[ac7af4a] | 494 | * @{ |
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[d374492] | 495 | */ |
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| 496 | |
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| 497 | #define SMSC9218I_MAC_ADDRH 0x00000002U |
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| 498 | #define SMSC9218I_MAC_ADDRH_MASK 0x0000ffffU |
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| 499 | |
---|
| 500 | /** @} */ |
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| 501 | |
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| 502 | /** |
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| 503 | * @name MAC Address Low |
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[ac7af4a] | 504 | * @{ |
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[d374492] | 505 | */ |
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| 506 | |
---|
| 507 | #define SMSC9218I_MAC_ADDRL 0x00000003U |
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| 508 | #define SMSC9218I_MAC_ADDRL_MASK 0xffffffffU |
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| 509 | |
---|
| 510 | /** @} */ |
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| 511 | |
---|
| 512 | /** |
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| 513 | * @name Multicast Hash Table High |
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[ac7af4a] | 514 | * @{ |
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[d374492] | 515 | */ |
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| 516 | |
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| 517 | #define SMSC9218I_MAC_HASHH 0x00000004U |
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| 518 | #define SMSC9218I_MAC_HASHH_MASK 0xffffffffU |
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| 519 | |
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| 520 | /** @} */ |
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| 521 | |
---|
| 522 | /** |
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| 523 | * @name Multicast Hash Table Low |
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[ac7af4a] | 524 | * @{ |
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[d374492] | 525 | */ |
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| 526 | |
---|
| 527 | #define SMSC9218I_MAC_HASHL 0x00000005U |
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| 528 | #define SMSC9218I_MAC_HASHL_MASK 0xffffffffU |
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| 529 | |
---|
| 530 | /** @} */ |
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| 531 | |
---|
| 532 | /** |
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| 533 | * @name MII Access |
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[ac7af4a] | 534 | * @{ |
---|
[d374492] | 535 | */ |
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| 536 | |
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| 537 | #define SMSC9218I_MAC_MII_ACC 0x00000006U |
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| 538 | #define SMSC9218I_MAC_MII_ACC_PHY_DEFAULT (1U << 11) |
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| 539 | #define SMSC9218I_MAC_MII_ACC_WRITE (1U << 1) |
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| 540 | #define SMSC9218I_MAC_MII_ACC_BUSY (1U << 0) |
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| 541 | #define SMSC9218I_MAC_MII_ACC_ADDR(addr) ((addr) << 6) |
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| 542 | |
---|
| 543 | /** @} */ |
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| 544 | |
---|
| 545 | /** |
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| 546 | * @name MII Data |
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[ac7af4a] | 547 | * @{ |
---|
[d374492] | 548 | */ |
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| 549 | |
---|
| 550 | #define SMSC9218I_MAC_MII_DATA 0x00000007U |
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| 551 | |
---|
| 552 | /** @} */ |
---|
| 553 | |
---|
| 554 | /** |
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| 555 | * @name Flow Control |
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[ac7af4a] | 556 | * @{ |
---|
[d374492] | 557 | */ |
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| 558 | |
---|
| 559 | #define SMSC9218I_MAC_FLOW 0x00000008U |
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| 560 | #define SMSC9218I_MAC_FLOW_FCPT_MASK 0xffff0000U |
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| 561 | #define SMSC9218I_MAC_FLOW_FCPASS 0x00000004U |
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| 562 | #define SMSC9218I_MAC_FLOW_FCEN 0x00000002U |
---|
| 563 | #define SMSC9218I_MAC_FLOW_FCBSY 0x00000001U |
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| 564 | |
---|
| 565 | /** @} */ |
---|
| 566 | |
---|
| 567 | /** |
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| 568 | * @name VLAN1 Tag |
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[ac7af4a] | 569 | * @{ |
---|
[d374492] | 570 | */ |
---|
| 571 | |
---|
| 572 | #define SMSC9218I_MAC_VLAN1 0x00000009U |
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| 573 | |
---|
| 574 | /** @} */ |
---|
| 575 | |
---|
| 576 | /** |
---|
| 577 | * @name VLAN2 Tag |
---|
[ac7af4a] | 578 | * @{ |
---|
[d374492] | 579 | */ |
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| 580 | |
---|
| 581 | #define SMSC9218I_MAC_VLAN2 0x0000000aU |
---|
| 582 | |
---|
| 583 | /** @} */ |
---|
| 584 | |
---|
| 585 | /** |
---|
| 586 | * @name Wake-up Frame Filter |
---|
[ac7af4a] | 587 | * @{ |
---|
[d374492] | 588 | */ |
---|
| 589 | |
---|
| 590 | #define SMSC9218I_MAC_WUFF 0x0000000bU |
---|
| 591 | |
---|
| 592 | /** @} */ |
---|
| 593 | |
---|
| 594 | /** |
---|
| 595 | * @name Wake-up Control and Status |
---|
[ac7af4a] | 596 | * @{ |
---|
[d374492] | 597 | */ |
---|
| 598 | |
---|
| 599 | #define SMSC9218I_MAC_WUCSR 0x0000000cU |
---|
| 600 | #define SMSC9218I_MAC_WUCSR_GUE 0x00000200U |
---|
| 601 | #define SMSC9218I_MAC_WUCSR_WUFR 0x00000040U |
---|
| 602 | #define SMSC9218I_MAC_WUCSR_MPR 0x00000020U |
---|
| 603 | #define SMSC9218I_MAC_WUCSR_WUEN 0x00000004U |
---|
| 604 | #define SMSC9218I_MAC_WUCSR_MPEN 0x00000002U |
---|
| 605 | |
---|
| 606 | /** @} */ |
---|
| 607 | |
---|
| 608 | /** |
---|
| 609 | * @name PHY Identifier 1 |
---|
[ac7af4a] | 610 | * @{ |
---|
[d374492] | 611 | */ |
---|
| 612 | |
---|
[a4475277] | 613 | #define SMSC9218I_PHY_ID1_LAN9118 0x7 |
---|
[d374492] | 614 | |
---|
| 615 | /** @} */ |
---|
| 616 | |
---|
| 617 | /** |
---|
| 618 | * @name PHY Identifier 2 |
---|
[ac7af4a] | 619 | * @{ |
---|
[d374492] | 620 | */ |
---|
| 621 | |
---|
[a4475277] | 622 | #define SMSC9218I_PHY_ID2_LAN9218 0xc0c3 |
---|
[d374492] | 623 | |
---|
| 624 | /** @} */ |
---|
| 625 | |
---|
| 626 | /** |
---|
| 627 | * @name Mode Control and Status |
---|
[ac7af4a] | 628 | * @{ |
---|
[d374492] | 629 | */ |
---|
| 630 | |
---|
| 631 | #define SMSC9218I_PHY_MCSR 0x00000011U |
---|
| 632 | #define SMSC9218I_PHY_MCSR_EDPWRDOWN 0x00002000U |
---|
| 633 | #define SMSC9218I_PHY_MCSR_ENERGYON 0x00000002U |
---|
| 634 | |
---|
| 635 | /** @} */ |
---|
| 636 | |
---|
| 637 | /** |
---|
| 638 | * @name Special Modes |
---|
[ac7af4a] | 639 | * @{ |
---|
[d374492] | 640 | */ |
---|
| 641 | |
---|
| 642 | #define SMSC9218I_PHY_SPMODES 0x00000012U |
---|
| 643 | |
---|
| 644 | /** @} */ |
---|
| 645 | |
---|
| 646 | /** |
---|
| 647 | * @name Special Control and Status Indications |
---|
[ac7af4a] | 648 | * @{ |
---|
[d374492] | 649 | */ |
---|
| 650 | |
---|
| 651 | #define SMSC9218I_PHY_CSIR 0x0000001bU |
---|
| 652 | #define SMSC9218I_PHY_CSIR_SQEOFF 0x00000800U |
---|
| 653 | #define SMSC9218I_PHY_CSIR_FEFIEN 0x00000020U |
---|
| 654 | #define SMSC9218I_PHY_CSIR_XPOL 0x00000010U |
---|
| 655 | |
---|
| 656 | /** @} */ |
---|
| 657 | |
---|
| 658 | /** |
---|
| 659 | * @name Interrupt Source Flag |
---|
[ac7af4a] | 660 | * @{ |
---|
[d374492] | 661 | */ |
---|
| 662 | |
---|
| 663 | #define SMSC9218I_PHY_ISR 0x0000001dU |
---|
| 664 | #define SMSC9218I_PHY_ISR_INT7 0x00000080U |
---|
| 665 | #define SMSC9218I_PHY_ISR_INT6 0x00000040U |
---|
| 666 | #define SMSC9218I_PHY_ISR_INT5 0x00000020U |
---|
| 667 | #define SMSC9218I_PHY_ISR_INT4 0x00000010U |
---|
| 668 | #define SMSC9218I_PHY_ISR_INT3 0x00000008U |
---|
| 669 | #define SMSC9218I_PHY_ISR_INT2 0x00000004U |
---|
| 670 | #define SMSC9218I_PHY_ISR_INT1 0x00000002U |
---|
| 671 | |
---|
| 672 | /** @} */ |
---|
| 673 | |
---|
| 674 | /** |
---|
| 675 | * @name Interrupt Mask |
---|
[ac7af4a] | 676 | * @{ |
---|
[d374492] | 677 | */ |
---|
| 678 | |
---|
| 679 | #define SMSC9218I_PHY_IMR 0x0000001eU |
---|
| 680 | #define SMSC9218I_PHY_IMR_INT7 0x00000080U |
---|
| 681 | #define SMSC9218I_PHY_IMR_INT6 0x00000040U |
---|
| 682 | #define SMSC9218I_PHY_IMR_INT5 0x00000020U |
---|
| 683 | #define SMSC9218I_PHY_IMR_INT4 0x00000010U |
---|
| 684 | #define SMSC9218I_PHY_IMR_INT3 0x00000008U |
---|
| 685 | #define SMSC9218I_PHY_IMR_INT2 0x00000004U |
---|
| 686 | #define SMSC9218I_PHY_IMR_INT1 0x00000002U |
---|
| 687 | |
---|
| 688 | /** @} */ |
---|
| 689 | |
---|
| 690 | /** |
---|
| 691 | * @name PHY Special Control and Status |
---|
[ac7af4a] | 692 | * @{ |
---|
[d374492] | 693 | */ |
---|
| 694 | |
---|
| 695 | #define SMSC9218I_PHY_PHYSCSR 0x0000001fU |
---|
| 696 | #define SMSC9218I_PHY_PHYSCSR_ANDONE 0x00001000U |
---|
| 697 | #define SMSC9218I_PHY_PHYSCSR_4B5B_EN 0x00000040U |
---|
| 698 | #define SMSC9218I_PHY_PHYSCSR_SPEED_MASK 0x0000001cU |
---|
| 699 | #define SMSC9218I_PHY_PHYSCSR_SPEED_10HD 0x00000004U |
---|
| 700 | #define SMSC9218I_PHY_PHYSCSR_SPEED_10FD 0x00000014U |
---|
| 701 | #define SMSC9218I_PHY_PHYSCSR_SPEED_100HD 0x00000008U |
---|
| 702 | #define SMSC9218I_PHY_PHYSCSR_SPEED_100FD 0x00000018U |
---|
| 703 | |
---|
| 704 | /** @} */ |
---|