source: rtems/bsps/powerpc/motorola_powerpc/start/bspstart.c @ c4ccf26c

5
Last change on this file since c4ccf26c was c4ccf26c, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 17, 2018 at 4:57:46 AM

bsps: Convert all bsp_predriver_hook()

Use RTEMS_SYSINIT_ITEM() instead.

Update #2408.

  • Property mode set to 100644
File size: 9.9 KB
Line 
1/*
2 *  This routine does the bulk of the system initialization.
3 */
4
5/*
6 *  COPYRIGHT (c) 1989-2007.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 *
13 *  Modified to support the MCP750.
14 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
15 */
16
17#include <string.h>
18
19#include <bsp.h>
20#include <bsp/bootcard.h>
21#include <rtems/bspIo.h>
22#include <rtems/counter.h>
23#include <rtems/sysinit.h>
24#include <bsp/consoleIo.h>
25#include <libcpu/spr.h>
26#include <bsp/residual.h>
27#include <bsp/pci.h>
28#include <bsp/openpic.h>
29#include <bsp/irq.h>
30#include <libcpu/bat.h>
31#include <libcpu/pte121.h>
32#include <libcpu/cpuIdent.h>
33#include <bsp/vectors.h>
34#include <bsp/VME.h>
35#include <bsp/motorola.h>
36#include <rtems/powerpc/powerpc.h>
37
38extern void _return_to_ppcbug(void);
39extern unsigned long __rtems_end[];
40extern void L1_caches_enables(void);
41extern unsigned get_L2CR(void);
42extern void set_L2CR(unsigned);
43extern Triv121PgTbl BSP_pgtbl_setup(unsigned int *);
44extern void                     BSP_pgtbl_activate(Triv121PgTbl);
45
46SPR_RW(SPRG1)
47
48#if defined(DEBUG_BATS)
49extern void ShowBATS(void);
50#endif
51
52/*
53 *  Driver configuration parameters
54 */
55uint32_t   bsp_clicks_per_usec;
56
57/*
58 * Copy of residuals passed by firmware
59 */
60RESIDUAL residualCopy;
61/*
62 * Copy Additional boot param passed by boot loader
63 */
64#define MAX_LOADER_ADD_PARM 80
65char loaderParam[MAX_LOADER_ADD_PARM];
66
67char *BSP_commandline_string = loaderParam;
68/*
69 * Vital Board data Start using DATA RESIDUAL
70 */
71/*
72 * Total memory using RESIDUAL DATA
73 */
74unsigned int BSP_mem_size;
75
76/*
77 * PCI Bus Frequency
78 */
79unsigned int BSP_bus_frequency;
80/*
81 * processor clock frequency
82 */
83unsigned int BSP_processor_frequency;
84/*
85 * Time base divisior (how many tick for 1 second).
86 */
87unsigned int BSP_time_base_divisor;
88
89/*
90 *  Use the shared implementations of the following routines
91 */
92
93char *save_boot_params(
94  void *r3,
95  void *r4,
96  void *r5,
97  char *cmdline_start,
98  char *cmdline_end
99)
100{
101
102  residualCopy = *(RESIDUAL *)r3;
103  strncpy(loaderParam, cmdline_start, MAX_LOADER_ADD_PARM);
104  loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
105  return loaderParam;
106}
107
108#if defined(mvme2100)
109unsigned int EUMBBAR;
110
111/*
112 * Return the current value of the Embedded Utilities Memory Block Base Address
113 * Register (EUMBBAR) as read from the processor configuration register using
114 * Processor Address Map B (CHRP).
115 */
116static unsigned int get_eumbbar(void) {
117  out_le32( (volatile uint32_t *)0xfec00000, 0x80000078 );
118  return in_le32( (volatile uint32_t *)0xfee00000 );
119}
120#endif
121
122/*
123 *  bsp_start
124 *
125 *  This routine does the bulk of the system initialization.
126 */
127
128void bsp_start( void )
129{
130#if !defined(mvme2100)
131  unsigned l2cr;
132#endif
133  uintptr_t intrStackStart;
134  uintptr_t intrStackSize;
135  prep_t boardManufacturer;
136  motorolaBoard myBoard;
137  Triv121PgTbl  pt=0;
138
139  /*
140   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
141   * function store the result in global variables so that it can be used
142   * later...
143   */
144  get_ppc_cpu_type();
145  get_ppc_cpu_revision();
146
147  /*
148   * Init MMU block address translation to enable hardware access
149   */
150
151#if !defined(mvme2100)
152  /*
153   * PC legacy IO space used for inb/outb and all PC compatible hardware
154   */
155  setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
156#endif
157
158  /*
159   * PCI devices memory area. Needed to access OpenPIC features
160   * provided by the Raven
161   *
162   * T. Straumann: give more PCI address space
163   */
164  setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE);
165
166  /*
167   * Must have acces to open pic PCI ACK registers provided by the RAVEN
168   */
169#ifndef qemu
170  setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
171#else
172  setdbat(3, 0xb0000000, 0xb0000000, 0x10000000, IO_PAGE);
173#endif
174
175#if defined(mvme2100)
176  /* Need 0xfec00000 mapped for this */
177  EUMBBAR = get_eumbbar();
178#endif
179
180  /*
181   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
182   * relevant CPU type so that the reason why there is no use of myCpu...
183   */
184  L1_caches_enables();
185
186  select_console(CONSOLE_LOG);
187
188  /*
189   * We check that the keyboard is present and immediately
190   * select the serial console if not.
191   */
192#if defined(BSP_KBD_IOBASE)
193  { int err;
194    err = kbdreset();
195    if (err) select_console(CONSOLE_SERIAL);
196  }
197#else
198  select_console(CONSOLE_SERIAL);
199#endif
200
201
202#if !defined(mvme2100)
203  /*
204   * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
205   * relevant CPU type (mpc750)...
206   */
207  l2cr = get_L2CR();
208#ifdef SHOW_LCR2_REGISTER
209  printk("Initial L2CR value = %x\n", l2cr);
210#endif
211  if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
212    set_L2CR(0xb9A14000);
213#endif
214
215  /*
216   * Initialize the interrupt related settings.
217   */
218  intrStackStart = (uintptr_t) __rtems_end;
219  intrStackSize = rtems_configuration_get_interrupt_stack_size();
220
221  /*
222   * Initialize default raw exception handlers.
223   */
224  ppc_exc_initialize(intrStackStart, intrStackSize);
225
226  boardManufacturer   =  checkPrepBoardType(&residualCopy);
227  if (boardManufacturer != PREP_Motorola) {
228    printk("Unsupported hardware vendor\n");
229    while (1);
230  }
231  myBoard = getMotorolaBoard();
232
233  printk("-----------------------------------------\n");
234  printk("Welcome to %s on %s\n", _RTEMS_version,
235                                    motorolaBoardToString(myBoard));
236  printk("-----------------------------------------\n");
237#ifdef SHOW_MORE_INIT_SETTINGS
238  printk("Residuals are located at %x\n", (unsigned) &residualCopy);
239  printk("Additionnal boot options are %s\n", loaderParam);
240  printk("Software IRQ stack starts at %x with size %u\n", intrStackStart, intrStackSize);
241  printk("-----------------------------------------\n");
242#endif
243
244#ifdef TEST_RETURN_TO_PPCBUG
245  printk("Hit <Enter> to return to PPCBUG monitor\n");
246  printk("When Finished hit GO. It should print <Back from monitor>\n");
247  debug_getc();
248  _return_to_ppcbug();
249  printk("Back from monitor\n");
250  _return_to_ppcbug();
251#endif /* TEST_RETURN_TO_PPCBUG  */
252
253#ifdef SHOW_MORE_INIT_SETTINGS
254  printk("Going to start PCI buses scanning and initialization\n");
255#endif
256
257  pci_initialize();
258  {
259    const struct _int_map *bspmap  = motorolaIntMap(currentBoard);
260    if( bspmap ) {
261       printk("pci : Configuring interrupt routing for '%s'\n",
262          motorolaBoardToString(currentBoard));
263       FixupPCI(bspmap, motorolaIntSwizzle(currentBoard));
264    }
265    else
266       printk("pci : Interrupt routing not available for this bsp\n");
267 }
268
269#ifdef SHOW_MORE_INIT_SETTINGS
270  printk("Number of PCI buses found is : %d\n", pci_bus_count());
271#endif
272#ifdef TEST_RAW_EXCEPTION_CODE
273  printk("Testing exception handling Part 1\n");
274  /*
275   * Cause a software exception
276   */
277  __asm__ __volatile ("sc");
278  /*
279   * Check we can still catch exceptions and return coorectly.
280   */
281  printk("Testing exception handling Part 2\n");
282  __asm__ __volatile ("sc");
283
284  /*
285   * Somehow doing the above seems to clobber SPRG0 on the mvme2100.  The
286   * interrupt disable mask is stored in SPRG0. Is this a problem?
287   */
288  ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT);
289
290#endif
291
292/* See above */
293
294  BSP_mem_size            = residualCopy.TotalMemory;
295  BSP_bus_frequency       = residualCopy.VitalProductData.ProcessorBusHz;
296  BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
297  BSP_time_base_divisor   = (residualCopy.VitalProductData.TimeBaseDivisor?
298                    residualCopy.VitalProductData.TimeBaseDivisor : 4000);
299
300  /* clear hostbridge errors but leave MCP disabled -
301   * PCI config space scanning code will trip otherwise :-(
302   */
303  _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);
304
305  if (BSP_mem_size > 0x10000000)
306  {
307    /* Support cases of system memory size larger than 256Mb.
308     *
309     * We use BAT3 in order to obtain access to the top section of the RAM.
310     * We also need to do this just before setting up the page table because
311     * this is where the page table will be located.
312     */
313    const unsigned int mem256Count = (BSP_mem_size / 0x10000000);
314    const unsigned int BAT3Addr    = ((BSP_mem_size % 0x10000000)  ?
315                                       (mem256Count     * 0x10000000) :
316                                      ((mem256Count-1) * 0x10000000));
317    setdbat(3, BAT3Addr, BAT3Addr, 0x10000000, IO_PAGE);
318#ifdef SHOW_MORE_INIT_SETTINGS
319    printk("Setting up BAT3 for large memory support. (BAT3 --> 0x%x)\n", BAT3Addr);
320#endif
321  }
322
323  /* Allocate and set up the page table mappings
324   * This is only available on >604 CPUs.
325   *
326   * NOTE: This setup routine may modify the available memory
327   *       size. It is essential to call it before
328   *       calculating the workspace etc.
329   */
330  pt = BSP_pgtbl_setup(&BSP_mem_size);
331
332  if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
333            pt, TRIV121_121_VSID,
334#ifndef qemu
335            0xfeff0000,
336#else
337            0xbffff000,
338#endif
339            1,
340            TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
341        printk("WARNING: unable to setup page tables VME "
342               "bridge must share PCI space\n");
343  }
344
345  /*
346   *  initialize the device driver parameters
347   */
348  bsp_clicks_per_usec    = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
349  rtems_counter_initialize_converter(
350    BSP_bus_frequency / (BSP_time_base_divisor / 1000)
351  );
352
353  /*
354   * Initalize RTEMS IRQ system
355   */
356  BSP_rtems_irq_mng_init(0);
357
358  /* Activate the page table mappings only after
359   * initializing interrupts because the irq_mng_init()
360   * routine needs to modify the text
361   */
362  if (pt) {
363#ifdef  SHOW_MORE_INIT_SETTINGS
364    printk("Page table setup finished; will activate it NOW...\n");
365#endif
366    BSP_pgtbl_activate(pt);
367    /* finally, switch off DBAT3 */
368    setdbat(3, 0, 0, 0, 0);
369  }
370
371#if defined(DEBUG_BATS)
372  ShowBATS();
373#endif
374
375#ifdef SHOW_MORE_INIT_SETTINGS
376  printk("Exit from bspstart\n");
377#endif
378}
379
380RTEMS_SYSINIT_ITEM(
381  BSP_vme_config,
382  RTEMS_SYSINIT_BSP_PRE_DRIVERS,
383  RTEMS_SYSINIT_ORDER_MIDDLE
384);
Note: See TracBrowser for help on using the repository browser.