source: rtems/bsps/powerpc/motorola_powerpc/start/bspstart.c @ 54d87f2

5
Last change on this file since 54d87f2 was 54d87f2, checked in by Sebastian Huber <sebastian.huber@…>, on Sep 4, 2018 at 4:28:57 PM

bsps/powerpc: Simplify ppc_exc_initialize()

Remove parameters from ppc_exc_initialize() since all BSPs passed the
same values.

Update #3459.

  • Property mode set to 100644
File size: 9.5 KB
Line 
1/*
2 *  This routine does the bulk of the system initialization.
3 */
4
5/*
6 *  COPYRIGHT (c) 1989-2007.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 *
13 *  Modified to support the MCP750.
14 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
15 */
16
17#include <string.h>
18
19#include <bsp.h>
20#include <bsp/bootcard.h>
21#include <rtems/bspIo.h>
22#include <rtems/counter.h>
23#include <rtems/sysinit.h>
24#include <bsp/consoleIo.h>
25#include <libcpu/spr.h>
26#include <bsp/residual.h>
27#include <bsp/pci.h>
28#include <bsp/openpic.h>
29#include <bsp/irq.h>
30#include <libcpu/bat.h>
31#include <libcpu/pte121.h>
32#include <libcpu/cpuIdent.h>
33#include <bsp/vectors.h>
34#include <bsp/VME.h>
35#include <bsp/motorola.h>
36#include <rtems/powerpc/powerpc.h>
37
38extern void _return_to_ppcbug(void);
39extern unsigned long __rtems_end[];
40extern void L1_caches_enables(void);
41extern unsigned get_L2CR(void);
42extern void set_L2CR(unsigned);
43extern Triv121PgTbl BSP_pgtbl_setup(unsigned int *);
44extern void                     BSP_pgtbl_activate(Triv121PgTbl);
45
46SPR_RW(SPRG1)
47
48#if defined(DEBUG_BATS)
49extern void ShowBATS(void);
50#endif
51
52/*
53 *  Driver configuration parameters
54 */
55uint32_t   bsp_clicks_per_usec;
56
57/*
58 * Copy of residuals passed by firmware
59 */
60RESIDUAL residualCopy;
61/*
62 * Copy Additional boot param passed by boot loader
63 */
64#define MAX_LOADER_ADD_PARM 80
65char loaderParam[MAX_LOADER_ADD_PARM];
66
67char *BSP_commandline_string = loaderParam;
68/*
69 * Vital Board data Start using DATA RESIDUAL
70 */
71/*
72 * Total memory using RESIDUAL DATA
73 */
74unsigned int BSP_mem_size;
75
76/*
77 * PCI Bus Frequency
78 */
79unsigned int BSP_bus_frequency;
80/*
81 * processor clock frequency
82 */
83unsigned int BSP_processor_frequency;
84/*
85 * Time base divisior (how many tick for 1 second).
86 */
87unsigned int BSP_time_base_divisor;
88
89/*
90 *  Use the shared implementations of the following routines
91 */
92
93char *save_boot_params(
94  void *r3,
95  void *r4,
96  void *r5,
97  char *cmdline_start,
98  char *cmdline_end
99)
100{
101
102  residualCopy = *(RESIDUAL *)r3;
103  strncpy(loaderParam, cmdline_start, MAX_LOADER_ADD_PARM);
104  loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
105  return loaderParam;
106}
107
108#if defined(mvme2100)
109unsigned int EUMBBAR;
110
111/*
112 * Return the current value of the Embedded Utilities Memory Block Base Address
113 * Register (EUMBBAR) as read from the processor configuration register using
114 * Processor Address Map B (CHRP).
115 */
116static unsigned int get_eumbbar(void) {
117  out_le32( (volatile uint32_t *)0xfec00000, 0x80000078 );
118  return in_le32( (volatile uint32_t *)0xfee00000 );
119}
120#endif
121
122uint32_t _CPU_Counter_frequency(void)
123{
124  return BSP_bus_frequency / (BSP_time_base_divisor / 1000);
125}
126
127/*
128 *  bsp_start
129 *
130 *  This routine does the bulk of the system initialization.
131 */
132
133void bsp_start( void )
134{
135#if !defined(mvme2100)
136  unsigned l2cr;
137#endif
138  prep_t boardManufacturer;
139  motorolaBoard myBoard;
140  Triv121PgTbl  pt=0;
141
142  /*
143   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
144   * function store the result in global variables so that it can be used
145   * later...
146   */
147  get_ppc_cpu_type();
148  get_ppc_cpu_revision();
149
150  /*
151   * Init MMU block address translation to enable hardware access
152   */
153
154#if !defined(mvme2100)
155  /*
156   * PC legacy IO space used for inb/outb and all PC compatible hardware
157   */
158  setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
159#endif
160
161  /*
162   * PCI devices memory area. Needed to access OpenPIC features
163   * provided by the Raven
164   *
165   * T. Straumann: give more PCI address space
166   */
167  setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE);
168
169  /*
170   * Must have acces to open pic PCI ACK registers provided by the RAVEN
171   */
172#ifndef qemu
173  setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
174#else
175  setdbat(3, 0xb0000000, 0xb0000000, 0x10000000, IO_PAGE);
176#endif
177
178#if defined(mvme2100)
179  /* Need 0xfec00000 mapped for this */
180  EUMBBAR = get_eumbbar();
181#endif
182
183  /*
184   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
185   * relevant CPU type so that the reason why there is no use of myCpu...
186   */
187  L1_caches_enables();
188
189  select_console(CONSOLE_LOG);
190
191  /*
192   * We check that the keyboard is present and immediately
193   * select the serial console if not.
194   */
195#if defined(BSP_KBD_IOBASE)
196  { int err;
197    err = kbdreset();
198    if (err) select_console(CONSOLE_SERIAL);
199  }
200#else
201  select_console(CONSOLE_SERIAL);
202#endif
203
204
205#if !defined(mvme2100)
206  /*
207   * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
208   * relevant CPU type (mpc750)...
209   */
210  l2cr = get_L2CR();
211#ifdef SHOW_LCR2_REGISTER
212  printk("Initial L2CR value = %x\n", l2cr);
213#endif
214  if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
215    set_L2CR(0xb9A14000);
216#endif
217
218  ppc_exc_initialize();
219
220  boardManufacturer   =  checkPrepBoardType(&residualCopy);
221  if (boardManufacturer != PREP_Motorola) {
222    printk("Unsupported hardware vendor\n");
223    while (1);
224  }
225  myBoard = getMotorolaBoard();
226
227  printk("-----------------------------------------\n");
228  printk("Welcome to %s on %s\n", _RTEMS_version,
229                                    motorolaBoardToString(myBoard));
230  printk("-----------------------------------------\n");
231#ifdef SHOW_MORE_INIT_SETTINGS
232  printk("Residuals are located at %x\n", (unsigned) &residualCopy);
233  printk("Additionnal boot options are %s\n", loaderParam);
234  printk("-----------------------------------------\n");
235#endif
236
237#ifdef TEST_RETURN_TO_PPCBUG
238  printk("Hit <Enter> to return to PPCBUG monitor\n");
239  printk("When Finished hit GO. It should print <Back from monitor>\n");
240  debug_getc();
241  _return_to_ppcbug();
242  printk("Back from monitor\n");
243  _return_to_ppcbug();
244#endif /* TEST_RETURN_TO_PPCBUG  */
245
246#ifdef SHOW_MORE_INIT_SETTINGS
247  printk("Going to start PCI buses scanning and initialization\n");
248#endif
249
250  pci_initialize();
251  {
252    const struct _int_map *bspmap  = motorolaIntMap(currentBoard);
253    if( bspmap ) {
254       printk("pci : Configuring interrupt routing for '%s'\n",
255          motorolaBoardToString(currentBoard));
256       FixupPCI(bspmap, motorolaIntSwizzle(currentBoard));
257    }
258    else
259       printk("pci : Interrupt routing not available for this bsp\n");
260 }
261
262#ifdef SHOW_MORE_INIT_SETTINGS
263  printk("Number of PCI buses found is : %d\n", pci_bus_count());
264#endif
265#ifdef TEST_RAW_EXCEPTION_CODE
266  printk("Testing exception handling Part 1\n");
267  /*
268   * Cause a software exception
269   */
270  __asm__ __volatile ("sc");
271  /*
272   * Check we can still catch exceptions and return coorectly.
273   */
274  printk("Testing exception handling Part 2\n");
275  __asm__ __volatile ("sc");
276
277  /*
278   * Somehow doing the above seems to clobber SPRG0 on the mvme2100.  The
279   * interrupt disable mask is stored in SPRG0. Is this a problem?
280   */
281  ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT);
282
283#endif
284
285/* See above */
286
287  BSP_mem_size            = residualCopy.TotalMemory;
288  BSP_bus_frequency       = residualCopy.VitalProductData.ProcessorBusHz;
289  BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
290  BSP_time_base_divisor   = (residualCopy.VitalProductData.TimeBaseDivisor?
291                    residualCopy.VitalProductData.TimeBaseDivisor : 4000);
292
293  /* clear hostbridge errors but leave MCP disabled -
294   * PCI config space scanning code will trip otherwise :-(
295   */
296  _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);
297
298  if (BSP_mem_size > 0x10000000)
299  {
300    /* Support cases of system memory size larger than 256Mb.
301     *
302     * We use BAT3 in order to obtain access to the top section of the RAM.
303     * We also need to do this just before setting up the page table because
304     * this is where the page table will be located.
305     */
306    const unsigned int mem256Count = (BSP_mem_size / 0x10000000);
307    const unsigned int BAT3Addr    = ((BSP_mem_size % 0x10000000)  ?
308                                       (mem256Count     * 0x10000000) :
309                                      ((mem256Count-1) * 0x10000000));
310    setdbat(3, BAT3Addr, BAT3Addr, 0x10000000, IO_PAGE);
311#ifdef SHOW_MORE_INIT_SETTINGS
312    printk("Setting up BAT3 for large memory support. (BAT3 --> 0x%x)\n", BAT3Addr);
313#endif
314  }
315
316  /* Allocate and set up the page table mappings
317   * This is only available on >604 CPUs.
318   *
319   * NOTE: This setup routine may modify the available memory
320   *       size. It is essential to call it before
321   *       calculating the workspace etc.
322   */
323  pt = BSP_pgtbl_setup(&BSP_mem_size);
324
325  if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
326            pt, TRIV121_121_VSID,
327#ifndef qemu
328            0xfeff0000,
329#else
330            0xbffff000,
331#endif
332            1,
333            TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
334        printk("WARNING: unable to setup page tables VME "
335               "bridge must share PCI space\n");
336  }
337
338  /*
339   *  initialize the device driver parameters
340   */
341  bsp_clicks_per_usec    = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
342
343  /*
344   * Initalize RTEMS IRQ system
345   */
346  BSP_rtems_irq_mng_init(0);
347
348  /* Activate the page table mappings only after
349   * initializing interrupts because the irq_mng_init()
350   * routine needs to modify the text
351   */
352  if (pt) {
353#ifdef  SHOW_MORE_INIT_SETTINGS
354    printk("Page table setup finished; will activate it NOW...\n");
355#endif
356    BSP_pgtbl_activate(pt);
357    /* finally, switch off DBAT3 */
358    setdbat(3, 0, 0, 0, 0);
359  }
360
361#if defined(DEBUG_BATS)
362  ShowBATS();
363#endif
364
365#ifdef SHOW_MORE_INIT_SETTINGS
366  printk("Exit from bspstart\n");
367#endif
368}
369
370RTEMS_SYSINIT_ITEM(
371  BSP_vme_config,
372  RTEMS_SYSINIT_BSP_PRE_DRIVERS,
373  RTEMS_SYSINIT_ORDER_MIDDLE
374);
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