source: rtems/bsps/powerpc/motorola_powerpc/start/bspstart.c @ 4b9b6dd

5
Last change on this file since 4b9b6dd was 4b9b6dd, checked in by Sebastian Huber <sebastian.huber@…>, on May 5, 2020 at 12:34:32 PM

Use rtems_get_version_string()

Update #3970.

  • Property mode set to 100644
File size: 9.6 KB
Line 
1/*
2 *  This routine does the bulk of the system initialization.
3 */
4
5/*
6 *  COPYRIGHT (c) 1989-2007.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 *
13 *  Modified to support the MCP750.
14 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
15 */
16
17#include <string.h>
18
19#include <bsp.h>
20#include <bsp/bootcard.h>
21#include <rtems/bspIo.h>
22#include <rtems/counter.h>
23#include <rtems/sysinit.h>
24#include <bsp/consoleIo.h>
25#include <libcpu/spr.h>
26#include <bsp/residual.h>
27#include <bsp/pci.h>
28#include <bsp/openpic.h>
29#include <bsp/irq.h>
30#include <libcpu/bat.h>
31#include <libcpu/pte121.h>
32#include <libcpu/cpuIdent.h>
33#include <bsp/vectors.h>
34#include <bsp/VME.h>
35#include <bsp/motorola.h>
36#include <rtems/powerpc/powerpc.h>
37
38extern void _return_to_ppcbug(void);
39extern unsigned long __rtems_end[];
40extern void L1_caches_enables(void);
41extern unsigned get_L2CR(void);
42extern void set_L2CR(unsigned);
43extern Triv121PgTbl BSP_pgtbl_setup(unsigned int *);
44extern void                     BSP_pgtbl_activate(Triv121PgTbl);
45
46SPR_RW(SPRG1)
47
48#if defined(DEBUG_BATS)
49extern void ShowBATS(void);
50#endif
51
52/*
53 *  Driver configuration parameters
54 */
55uint32_t   bsp_clicks_per_usec;
56
57/*
58 * Copy of residuals passed by firmware
59 */
60RESIDUAL residualCopy;
61/*
62 * Copy Additional boot param passed by boot loader
63 */
64#define MAX_LOADER_ADD_PARM 80
65char loaderParam[MAX_LOADER_ADD_PARM];
66
67char *BSP_commandline_string = loaderParam;
68/*
69 * Vital Board data Start using DATA RESIDUAL
70 */
71/*
72 * Total memory using RESIDUAL DATA
73 */
74unsigned int BSP_mem_size;
75
76/*
77 * PCI Bus Frequency
78 */
79unsigned int BSP_bus_frequency;
80/*
81 * processor clock frequency
82 */
83unsigned int BSP_processor_frequency;
84/*
85 * Time base divisior (how many tick for 1 second).
86 */
87unsigned int BSP_time_base_divisor;
88
89/*
90 *  Use the shared implementations of the following routines
91 */
92
93char *save_boot_params(
94  void *r3,
95  void *r4,
96  void *r5,
97  char *cmdline_start,
98  char *cmdline_end
99)
100{
101
102  residualCopy = *(RESIDUAL *)r3;
103  strncpy(loaderParam, cmdline_start, MAX_LOADER_ADD_PARM);
104  loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
105  return loaderParam;
106}
107
108#if defined(mvme2100)
109unsigned int EUMBBAR;
110
111/*
112 * Return the current value of the Embedded Utilities Memory Block Base Address
113 * Register (EUMBBAR) as read from the processor configuration register using
114 * Processor Address Map B (CHRP).
115 */
116static unsigned int get_eumbbar(void) {
117  out_le32( (volatile uint32_t *)0xfec00000, 0x80000078 );
118  return in_le32( (volatile uint32_t *)0xfee00000 );
119}
120#endif
121
122uint32_t _CPU_Counter_frequency(void)
123{
124  return BSP_bus_frequency / (BSP_time_base_divisor / 1000);
125}
126
127static void bsp_early( void )
128{
129#if !defined(mvme2100)
130  unsigned l2cr;
131#endif
132  prep_t boardManufacturer;
133  motorolaBoard myBoard;
134  Triv121PgTbl  pt=0;
135
136  /*
137   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
138   * function store the result in global variables so that it can be used
139   * later...
140   */
141  get_ppc_cpu_type();
142  get_ppc_cpu_revision();
143
144  /*
145   * Init MMU block address translation to enable hardware access
146   */
147
148#if !defined(mvme2100)
149  /*
150   * PC legacy IO space used for inb/outb and all PC compatible hardware
151   */
152  setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
153#endif
154
155  /*
156   * PCI devices memory area. Needed to access OpenPIC features
157   * provided by the Raven
158   *
159   * T. Straumann: give more PCI address space
160   */
161  setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE);
162
163  /*
164   * Must have acces to open pic PCI ACK registers provided by the RAVEN
165   */
166#ifndef qemu
167  setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
168#else
169  setdbat(3, 0xb0000000, 0xb0000000, 0x10000000, IO_PAGE);
170#endif
171
172#if defined(mvme2100)
173  /* Need 0xfec00000 mapped for this */
174  EUMBBAR = get_eumbbar();
175#endif
176
177  /*
178   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
179   * relevant CPU type so that the reason why there is no use of myCpu...
180   */
181  L1_caches_enables();
182
183  select_console(CONSOLE_LOG);
184
185  /*
186   * We check that the keyboard is present and immediately
187   * select the serial console if not.
188   */
189#if defined(BSP_KBD_IOBASE)
190  { int err;
191    err = kbdreset();
192    if (err) select_console(CONSOLE_SERIAL);
193  }
194#else
195  select_console(CONSOLE_SERIAL);
196#endif
197
198
199#if !defined(mvme2100)
200  /*
201   * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
202   * relevant CPU type (mpc750)...
203   */
204  l2cr = get_L2CR();
205#ifdef SHOW_LCR2_REGISTER
206  printk("Initial L2CR value = %x\n", l2cr);
207#endif
208  if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
209    set_L2CR(0xb9A14000);
210#endif
211
212  ppc_exc_initialize();
213
214  boardManufacturer   =  checkPrepBoardType(&residualCopy);
215  if (boardManufacturer != PREP_Motorola) {
216    printk("Unsupported hardware vendor\n");
217    while (1);
218  }
219  myBoard = getMotorolaBoard();
220
221  printk("-----------------------------------------\n");
222  printk("Welcome to %s on %s\n", rtems_get_version_string(),
223                                    motorolaBoardToString(myBoard));
224  printk("-----------------------------------------\n");
225#ifdef SHOW_MORE_INIT_SETTINGS
226  printk("Residuals are located at %x\n", (unsigned) &residualCopy);
227  printk("Additionnal boot options are %s\n", loaderParam);
228  printk("-----------------------------------------\n");
229#endif
230
231#ifdef TEST_RETURN_TO_PPCBUG
232  printk("Hit <Enter> to return to PPCBUG monitor\n");
233  printk("When Finished hit GO. It should print <Back from monitor>\n");
234  debug_getc();
235  _return_to_ppcbug();
236  printk("Back from monitor\n");
237  _return_to_ppcbug();
238#endif /* TEST_RETURN_TO_PPCBUG  */
239
240#ifdef SHOW_MORE_INIT_SETTINGS
241  printk("Going to start PCI buses scanning and initialization\n");
242#endif
243
244  pci_initialize();
245  {
246    const struct _int_map *bspmap  = motorolaIntMap(currentBoard);
247    if( bspmap ) {
248       printk("pci : Configuring interrupt routing for '%s'\n",
249          motorolaBoardToString(currentBoard));
250       FixupPCI(bspmap, motorolaIntSwizzle(currentBoard));
251    }
252    else
253       printk("pci : Interrupt routing not available for this bsp\n");
254 }
255
256#ifdef SHOW_MORE_INIT_SETTINGS
257  printk("Number of PCI buses found is : %d\n", pci_bus_count());
258#endif
259#ifdef TEST_RAW_EXCEPTION_CODE
260  printk("Testing exception handling Part 1\n");
261  /*
262   * Cause a software exception
263   */
264  __asm__ __volatile ("sc");
265  /*
266   * Check we can still catch exceptions and return coorectly.
267   */
268  printk("Testing exception handling Part 2\n");
269  __asm__ __volatile ("sc");
270
271  /*
272   * Somehow doing the above seems to clobber SPRG0 on the mvme2100.  The
273   * interrupt disable mask is stored in SPRG0. Is this a problem?
274   */
275  ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT);
276
277#endif
278
279/* See above */
280
281  BSP_mem_size            = residualCopy.TotalMemory;
282  BSP_bus_frequency       = residualCopy.VitalProductData.ProcessorBusHz;
283  BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
284  BSP_time_base_divisor   = (residualCopy.VitalProductData.TimeBaseDivisor?
285                    residualCopy.VitalProductData.TimeBaseDivisor : 4000);
286
287  /* clear hostbridge errors but leave MCP disabled -
288   * PCI config space scanning code will trip otherwise :-(
289   */
290  _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);
291
292  if (BSP_mem_size > 0x10000000)
293  {
294    /* Support cases of system memory size larger than 256Mb.
295     *
296     * We use BAT3 in order to obtain access to the top section of the RAM.
297     * We also need to do this just before setting up the page table because
298     * this is where the page table will be located.
299     */
300    const unsigned int mem256Count = (BSP_mem_size / 0x10000000);
301    const unsigned int BAT3Addr    = ((BSP_mem_size % 0x10000000)  ?
302                                       (mem256Count     * 0x10000000) :
303                                      ((mem256Count-1) * 0x10000000));
304    setdbat(3, BAT3Addr, BAT3Addr, 0x10000000, IO_PAGE);
305#ifdef SHOW_MORE_INIT_SETTINGS
306    printk("Setting up BAT3 for large memory support. (BAT3 --> 0x%x)\n", BAT3Addr);
307#endif
308  }
309
310  /* Allocate and set up the page table mappings
311   * This is only available on >604 CPUs.
312   *
313   * NOTE: This setup routine may modify the available memory
314   *       size. It is essential to call it before
315   *       calculating the workspace etc.
316   */
317  pt = BSP_pgtbl_setup(&BSP_mem_size);
318
319  if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
320            pt, TRIV121_121_VSID,
321#ifndef qemu
322            0xfeff0000,
323#else
324            0xbffff000,
325#endif
326            1,
327            TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
328        printk("WARNING: unable to setup page tables VME "
329               "bridge must share PCI space\n");
330  }
331
332  /*
333   *  initialize the device driver parameters
334   */
335  bsp_clicks_per_usec    = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
336
337  /*
338   * Initalize RTEMS IRQ system
339   */
340  BSP_rtems_irq_mng_init(0);
341
342  /* Activate the page table mappings only after
343   * initializing interrupts because the irq_mng_init()
344   * routine needs to modify the text
345   */
346  if (pt) {
347#ifdef  SHOW_MORE_INIT_SETTINGS
348    printk("Page table setup finished; will activate it NOW...\n");
349#endif
350    BSP_pgtbl_activate(pt);
351    /* finally, switch off DBAT3 */
352    setdbat(3, 0, 0, 0, 0);
353  }
354
355#if defined(DEBUG_BATS)
356  ShowBATS();
357#endif
358
359#ifdef SHOW_MORE_INIT_SETTINGS
360  printk("Exit from bspstart\n");
361#endif
362}
363
364RTEMS_SYSINIT_ITEM(
365  bsp_early,
366  RTEMS_SYSINIT_BSP_EARLY,
367  RTEMS_SYSINIT_ORDER_MIDDLE
368);
369
370void bsp_start( void )
371{
372  /* Initialization was done by bsp_early() */
373}
374
375RTEMS_SYSINIT_ITEM(
376  BSP_vme_config,
377  RTEMS_SYSINIT_BSP_PRE_DRIVERS,
378  RTEMS_SYSINIT_ORDER_MIDDLE
379);
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