[acc25ee] | 1 | /* |
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[ad38073] | 2 | * This routine does the bulk of the system initialization. |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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[28f398e7] | 6 | * COPYRIGHT (c) 1989-2007. |
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[acc25ee] | 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * |
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| 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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[c499856] | 11 | * http://www.rtems.org/license/LICENSE. |
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[acc25ee] | 12 | * |
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| 13 | * Modified to support the MCP750. |
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| 14 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 15 | */ |
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| 16 | |
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| 17 | #include <string.h> |
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[eba2e4f] | 18 | |
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[e79a1947] | 19 | #include <bsp.h> |
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[ad38073] | 20 | #include <bsp/bootcard.h> |
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[d1999c8b] | 21 | #include <rtems/bspIo.h> |
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[24bf11e] | 22 | #include <rtems/counter.h> |
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[c4ccf26c] | 23 | #include <rtems/sysinit.h> |
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[acc25ee] | 24 | #include <bsp/consoleIo.h> |
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| 25 | #include <libcpu/spr.h> |
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| 26 | #include <bsp/residual.h> |
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| 27 | #include <bsp/pci.h> |
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| 28 | #include <bsp/openpic.h> |
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| 29 | #include <bsp/irq.h> |
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| 30 | #include <libcpu/bat.h> |
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[4f3e4f33] | 31 | #include <libcpu/pte121.h> |
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[70f1268d] | 32 | #include <libcpu/cpuIdent.h> |
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[acc25ee] | 33 | #include <bsp/vectors.h> |
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[c4ccf26c] | 34 | #include <bsp/VME.h> |
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[acc25ee] | 35 | #include <bsp/motorola.h> |
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[1899fe4] | 36 | #include <rtems/powerpc/powerpc.h> |
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[acc25ee] | 37 | |
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[cc981e1] | 38 | extern void _return_to_ppcbug(void); |
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[64f8ae4] | 39 | extern unsigned long __rtems_end[]; |
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[cc981e1] | 40 | extern void L1_caches_enables(void); |
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| 41 | extern unsigned get_L2CR(void); |
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[acc25ee] | 42 | extern void set_L2CR(unsigned); |
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[86939c94] | 43 | extern Triv121PgTbl BSP_pgtbl_setup(unsigned int *); |
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[cc981e1] | 44 | extern void BSP_pgtbl_activate(Triv121PgTbl); |
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[4f3e4f33] | 45 | |
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[ec821af] | 46 | SPR_RW(SPRG1) |
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[4f3e4f33] | 47 | |
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[e79a1947] | 48 | #if defined(DEBUG_BATS) |
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[cc981e1] | 49 | extern void ShowBATS(void); |
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[e79a1947] | 50 | #endif |
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| 51 | |
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[28f398e7] | 52 | /* |
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| 53 | * Driver configuration parameters |
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| 54 | */ |
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| 55 | uint32_t bsp_clicks_per_usec; |
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| 56 | |
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[acc25ee] | 57 | /* |
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| 58 | * Copy of residuals passed by firmware |
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| 59 | */ |
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[6128a4a] | 60 | RESIDUAL residualCopy; |
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[acc25ee] | 61 | /* |
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| 62 | * Copy Additional boot param passed by boot loader |
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| 63 | */ |
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| 64 | #define MAX_LOADER_ADD_PARM 80 |
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| 65 | char loaderParam[MAX_LOADER_ADD_PARM]; |
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[1051054] | 66 | |
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| 67 | char *BSP_commandline_string = loaderParam; |
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[acc25ee] | 68 | /* |
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| 69 | * Vital Board data Start using DATA RESIDUAL |
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| 70 | */ |
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| 71 | /* |
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| 72 | * Total memory using RESIDUAL DATA |
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| 73 | */ |
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| 74 | unsigned int BSP_mem_size; |
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[db77b92] | 75 | |
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[acc25ee] | 76 | /* |
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| 77 | * PCI Bus Frequency |
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| 78 | */ |
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| 79 | unsigned int BSP_bus_frequency; |
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| 80 | /* |
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| 81 | * processor clock frequency |
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| 82 | */ |
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| 83 | unsigned int BSP_processor_frequency; |
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| 84 | /* |
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| 85 | * Time base divisior (how many tick for 1 second). |
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| 86 | */ |
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| 87 | unsigned int BSP_time_base_divisor; |
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| 88 | |
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| 89 | /* |
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| 90 | * Use the shared implementations of the following routines |
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| 91 | */ |
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[6128a4a] | 92 | |
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[9ffca502] | 93 | char *save_boot_params( |
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| 94 | void *r3, |
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| 95 | void *r4, |
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| 96 | void *r5, |
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| 97 | char *cmdline_start, |
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| 98 | char *cmdline_end |
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[db77b92] | 99 | ) |
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[acc25ee] | 100 | { |
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[6128a4a] | 101 | |
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[9ffca502] | 102 | residualCopy = *(RESIDUAL *)r3; |
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| 103 | strncpy(loaderParam, cmdline_start, MAX_LOADER_ADD_PARM); |
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[acc25ee] | 104 | loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0'; |
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[ec625ec] | 105 | return loaderParam; |
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[acc25ee] | 106 | } |
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| 107 | |
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[416ec41] | 108 | #if defined(mvme2100) |
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[e79a1947] | 109 | unsigned int EUMBBAR; |
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| 110 | |
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[ac7af4a] | 111 | /* |
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[e79a1947] | 112 | * Return the current value of the Embedded Utilities Memory Block Base Address |
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| 113 | * Register (EUMBBAR) as read from the processor configuration register using |
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| 114 | * Processor Address Map B (CHRP). |
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[ac7af4a] | 115 | */ |
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[7294054b] | 116 | static unsigned int get_eumbbar(void) { |
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[2d5c486] | 117 | out_le32( (volatile uint32_t *)0xfec00000, 0x80000078 ); |
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| 118 | return in_le32( (volatile uint32_t *)0xfee00000 ); |
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[e79a1947] | 119 | } |
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| 120 | #endif |
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| 121 | |
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[acc25ee] | 122 | /* |
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| 123 | * bsp_start |
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| 124 | * |
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| 125 | * This routine does the bulk of the system initialization. |
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| 126 | */ |
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| 127 | |
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| 128 | void bsp_start( void ) |
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| 129 | { |
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[416ec41] | 130 | #if !defined(mvme2100) |
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[acc25ee] | 131 | unsigned l2cr; |
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[e79a1947] | 132 | #endif |
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[2d2de4eb] | 133 | uintptr_t intrStackStart; |
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| 134 | uintptr_t intrStackSize; |
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[acc25ee] | 135 | prep_t boardManufacturer; |
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| 136 | motorolaBoard myBoard; |
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[4f3e4f33] | 137 | Triv121PgTbl pt=0; |
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[e79a1947] | 138 | |
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[acc25ee] | 139 | /* |
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[e79a1947] | 140 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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[ac7af4a] | 141 | * function store the result in global variables so that it can be used |
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[e79a1947] | 142 | * later... |
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[acc25ee] | 143 | */ |
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[c506cc98] | 144 | get_ppc_cpu_type(); |
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| 145 | get_ppc_cpu_revision(); |
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[e79a1947] | 146 | |
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[ab20575] | 147 | /* |
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| 148 | * Init MMU block address translation to enable hardware access |
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| 149 | */ |
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| 150 | |
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| 151 | #if !defined(mvme2100) |
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| 152 | /* |
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| 153 | * PC legacy IO space used for inb/outb and all PC compatible hardware |
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| 154 | */ |
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| 155 | setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE); |
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| 156 | #endif |
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| 157 | |
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| 158 | /* |
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| 159 | * PCI devices memory area. Needed to access OpenPIC features |
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| 160 | * provided by the Raven |
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| 161 | * |
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| 162 | * T. Straumann: give more PCI address space |
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| 163 | */ |
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| 164 | setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE); |
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| 165 | |
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| 166 | /* |
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| 167 | * Must have acces to open pic PCI ACK registers provided by the RAVEN |
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| 168 | */ |
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[58127230] | 169 | #ifndef qemu |
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[ab20575] | 170 | setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); |
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[58127230] | 171 | #else |
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| 172 | setdbat(3, 0xb0000000, 0xb0000000, 0x10000000, IO_PAGE); |
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| 173 | #endif |
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[ab20575] | 174 | |
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[e79a1947] | 175 | #if defined(mvme2100) |
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[ab20575] | 176 | /* Need 0xfec00000 mapped for this */ |
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[ac7af4a] | 177 | EUMBBAR = get_eumbbar(); |
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[e79a1947] | 178 | #endif |
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| 179 | |
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[acc25ee] | 180 | /* |
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| 181 | * enables L1 Cache. Note that the L1_caches_enables() codes checks for |
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| 182 | * relevant CPU type so that the reason why there is no use of myCpu... |
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| 183 | */ |
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| 184 | L1_caches_enables(); |
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[e79a1947] | 185 | |
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[4b6692f] | 186 | select_console(CONSOLE_LOG); |
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| 187 | |
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| 188 | /* |
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| 189 | * We check that the keyboard is present and immediately |
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| 190 | * select the serial console if not. |
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| 191 | */ |
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| 192 | #if defined(BSP_KBD_IOBASE) |
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| 193 | { int err; |
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| 194 | err = kbdreset(); |
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| 195 | if (err) select_console(CONSOLE_SERIAL); |
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| 196 | } |
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| 197 | #else |
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| 198 | select_console(CONSOLE_SERIAL); |
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| 199 | #endif |
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| 200 | |
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| 201 | |
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[416ec41] | 202 | #if !defined(mvme2100) |
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[acc25ee] | 203 | /* |
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| 204 | * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for |
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| 205 | * relevant CPU type (mpc750)... |
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| 206 | */ |
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| 207 | l2cr = get_L2CR(); |
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| 208 | #ifdef SHOW_LCR2_REGISTER |
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| 209 | printk("Initial L2CR value = %x\n", l2cr); |
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[6128a4a] | 210 | #endif |
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[acc25ee] | 211 | if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1)) |
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| 212 | set_L2CR(0xb9A14000); |
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[e79a1947] | 213 | #endif |
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| 214 | |
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[acc25ee] | 215 | /* |
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[a86f3aac] | 216 | * Initialize the interrupt related settings. |
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[acc25ee] | 217 | */ |
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[2d2de4eb] | 218 | intrStackStart = (uintptr_t) __rtems_end; |
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[a86f3aac] | 219 | intrStackSize = rtems_configuration_get_interrupt_stack_size(); |
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[ec821af] | 220 | |
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[acc25ee] | 221 | /* |
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[a86f3aac] | 222 | * Initialize default raw exception handlers. |
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[acc25ee] | 223 | */ |
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[801b5d8] | 224 | ppc_exc_initialize(intrStackStart, intrStackSize); |
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[e79a1947] | 225 | |
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[acc25ee] | 226 | boardManufacturer = checkPrepBoardType(&residualCopy); |
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| 227 | if (boardManufacturer != PREP_Motorola) { |
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| 228 | printk("Unsupported hardware vendor\n"); |
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| 229 | while (1); |
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| 230 | } |
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| 231 | myBoard = getMotorolaBoard(); |
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[6128a4a] | 232 | |
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[acc25ee] | 233 | printk("-----------------------------------------\n"); |
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[e79a1947] | 234 | printk("Welcome to %s on %s\n", _RTEMS_version, |
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| 235 | motorolaBoardToString(myBoard)); |
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[acc25ee] | 236 | printk("-----------------------------------------\n"); |
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[6128a4a] | 237 | #ifdef SHOW_MORE_INIT_SETTINGS |
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[acc25ee] | 238 | printk("Residuals are located at %x\n", (unsigned) &residualCopy); |
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| 239 | printk("Additionnal boot options are %s\n", loaderParam); |
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[a86f3aac] | 240 | printk("Software IRQ stack starts at %x with size %u\n", intrStackStart, intrStackSize); |
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[acc25ee] | 241 | printk("-----------------------------------------\n"); |
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| 242 | #endif |
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| 243 | |
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[6128a4a] | 244 | #ifdef TEST_RETURN_TO_PPCBUG |
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[acc25ee] | 245 | printk("Hit <Enter> to return to PPCBUG monitor\n"); |
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| 246 | printk("When Finished hit GO. It should print <Back from monitor>\n"); |
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| 247 | debug_getc(); |
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| 248 | _return_to_ppcbug(); |
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| 249 | printk("Back from monitor\n"); |
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| 250 | _return_to_ppcbug(); |
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| 251 | #endif /* TEST_RETURN_TO_PPCBUG */ |
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| 252 | |
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| 253 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 254 | printk("Going to start PCI buses scanning and initialization\n"); |
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[6128a4a] | 255 | #endif |
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[3a3e0b0e] | 256 | |
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[4820d95] | 257 | pci_initialize(); |
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[e79a1947] | 258 | { |
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| 259 | const struct _int_map *bspmap = motorolaIntMap(currentBoard); |
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| 260 | if( bspmap ) { |
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| 261 | printk("pci : Configuring interrupt routing for '%s'\n", |
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| 262 | motorolaBoardToString(currentBoard)); |
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| 263 | FixupPCI(bspmap, motorolaIntSwizzle(currentBoard)); |
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[3a3e0b0e] | 264 | } |
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| 265 | else |
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| 266 | printk("pci : Interrupt routing not available for this bsp\n"); |
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| 267 | } |
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| 268 | |
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[acc25ee] | 269 | #ifdef SHOW_MORE_INIT_SETTINGS |
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[548ed3f] | 270 | printk("Number of PCI buses found is : %d\n", pci_bus_count()); |
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[acc25ee] | 271 | #endif |
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[6128a4a] | 272 | #ifdef TEST_RAW_EXCEPTION_CODE |
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[acc25ee] | 273 | printk("Testing exception handling Part 1\n"); |
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| 274 | /* |
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| 275 | * Cause a software exception |
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| 276 | */ |
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| 277 | __asm__ __volatile ("sc"); |
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| 278 | /* |
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[e79a1947] | 279 | * Check we can still catch exceptions and return coorectly. |
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[acc25ee] | 280 | */ |
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| 281 | printk("Testing exception handling Part 2\n"); |
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| 282 | __asm__ __volatile ("sc"); |
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[e79a1947] | 283 | |
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| 284 | /* |
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[a86f3aac] | 285 | * Somehow doing the above seems to clobber SPRG0 on the mvme2100. The |
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| 286 | * interrupt disable mask is stored in SPRG0. Is this a problem? |
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[e79a1947] | 287 | */ |
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[a86f3aac] | 288 | ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT); |
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| 289 | |
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[6128a4a] | 290 | #endif |
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[acc25ee] | 291 | |
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[a86f3aac] | 292 | /* See above */ |
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| 293 | |
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[e79a1947] | 294 | BSP_mem_size = residualCopy.TotalMemory; |
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| 295 | BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz; |
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| 296 | BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz; |
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| 297 | BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor? |
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| 298 | residualCopy.VitalProductData.TimeBaseDivisor : 4000); |
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[4f3e4f33] | 299 | |
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[674b9497] | 300 | /* clear hostbridge errors but leave MCP disabled - |
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| 301 | * PCI config space scanning code will trip otherwise :-( |
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| 302 | */ |
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| 303 | _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/); |
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[14ec2d4] | 304 | |
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[5cf0656] | 305 | if (BSP_mem_size > 0x10000000) |
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| 306 | { |
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| 307 | /* Support cases of system memory size larger than 256Mb. |
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| 308 | * |
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| 309 | * We use BAT3 in order to obtain access to the top section of the RAM. |
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| 310 | * We also need to do this just before setting up the page table because |
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| 311 | * this is where the page table will be located. |
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| 312 | */ |
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| 313 | const unsigned int mem256Count = (BSP_mem_size / 0x10000000); |
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| 314 | const unsigned int BAT3Addr = ((BSP_mem_size % 0x10000000) ? |
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| 315 | (mem256Count * 0x10000000) : |
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| 316 | ((mem256Count-1) * 0x10000000)); |
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| 317 | setdbat(3, BAT3Addr, BAT3Addr, 0x10000000, IO_PAGE); |
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| 318 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 319 | printk("Setting up BAT3 for large memory support. (BAT3 --> 0x%x)\n", BAT3Addr); |
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| 320 | #endif |
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| 321 | } |
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| 322 | |
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[4f3e4f33] | 323 | /* Allocate and set up the page table mappings |
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| 324 | * This is only available on >604 CPUs. |
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| 325 | * |
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| 326 | * NOTE: This setup routine may modify the available memory |
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| 327 | * size. It is essential to call it before |
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| 328 | * calculating the workspace etc. |
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| 329 | */ |
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| 330 | pt = BSP_pgtbl_setup(&BSP_mem_size); |
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| 331 | |
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[e79a1947] | 332 | if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap( |
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[58127230] | 333 | pt, TRIV121_121_VSID, |
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| 334 | #ifndef qemu |
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| 335 | 0xfeff0000, |
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| 336 | #else |
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| 337 | 0xbffff000, |
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| 338 | #endif |
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| 339 | 1, |
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[e79a1947] | 340 | TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) { |
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| 341 | printk("WARNING: unable to setup page tables VME " |
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| 342 | "bridge must share PCI space\n"); |
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[4f3e4f33] | 343 | } |
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[6128a4a] | 344 | |
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[acc25ee] | 345 | /* |
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[7321ff0] | 346 | * initialize the device driver parameters |
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[acc25ee] | 347 | */ |
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[28f398e7] | 348 | bsp_clicks_per_usec = BSP_bus_frequency/(BSP_time_base_divisor * 1000); |
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[24bf11e] | 349 | rtems_counter_initialize_converter( |
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| 350 | BSP_bus_frequency / (BSP_time_base_divisor / 1000) |
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| 351 | ); |
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[acc25ee] | 352 | |
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| 353 | /* |
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| 354 | * Initalize RTEMS IRQ system |
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| 355 | */ |
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| 356 | BSP_rtems_irq_mng_init(0); |
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[4f3e4f33] | 357 | |
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| 358 | /* Activate the page table mappings only after |
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| 359 | * initializing interrupts because the irq_mng_init() |
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| 360 | * routine needs to modify the text |
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[6128a4a] | 361 | */ |
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[4f3e4f33] | 362 | if (pt) { |
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| 363 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 364 | printk("Page table setup finished; will activate it NOW...\n"); |
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| 365 | #endif |
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| 366 | BSP_pgtbl_activate(pt); |
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[e79a1947] | 367 | /* finally, switch off DBAT3 */ |
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[ac7af4a] | 368 | setdbat(3, 0, 0, 0, 0); |
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[4f3e4f33] | 369 | } |
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| 370 | |
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[e79a1947] | 371 | #if defined(DEBUG_BATS) |
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| 372 | ShowBATS(); |
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| 373 | #endif |
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| 374 | |
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[acc25ee] | 375 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 376 | printk("Exit from bspstart\n"); |
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[6128a4a] | 377 | #endif |
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[acc25ee] | 378 | } |
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[c4ccf26c] | 379 | |
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| 380 | RTEMS_SYSINIT_ITEM( |
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| 381 | BSP_vme_config, |
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| 382 | RTEMS_SYSINIT_BSP_PRE_DRIVERS, |
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| 383 | RTEMS_SYSINIT_ORDER_MIDDLE |
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| 384 | ); |
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