source: rtems/bsps/powerpc/motorola_powerpc/include/bsp/irq.h @ 45d0659

5
Last change on this file since 45d0659 was 45d0659, checked in by Sebastian Huber <sebastian.huber@…>, on 05/11/19 at 12:57:39

bsps: Always build generic interrupt support

This makes it possible to write tests for the generic interrupt
controller support.

Update #3269.
  • Property mode set to 100644
File size: 6.8 KB
Line 
1/* irq.h
2 *
3 *  This include file describe the data structure and the functions implemented
4 *  by RTEMS to write interrupt handlers.
5 *
6 *  Copyright (C) 1999 valette@crf.canon.fr
7 *
8 *  This code is heavilly inspired by the public specification of STREAM V2
9 *  that can be found at :
10 *
11 *      <http://www.chorus.com/Documentation/index.html> by following
12 *  the STREAM API Specification Document link.
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef BSP_POWERPC_IRQ_H
20#define BSP_POWERPC_IRQ_H
21
22#define BSP_SHARED_HANDLER_SUPPORT      1
23#include <rtems/irq.h>
24#include <bsp/irq-default.h>
25
26/*
27 * 8259 edge/level control definitions at VIA
28 */
29#define ISA8259_M_ELCR          0x4d0
30#define ISA8259_S_ELCR          0x4d1
31
32#define ELCRS_INT15_LVL         0x80
33#define ELCRS_INT14_LVL         0x40
34#define ELCRS_INT13_LVL         0x20
35#define ELCRS_INT12_LVL         0x10
36#define ELCRS_INT11_LVL         0x08
37#define ELCRS_INT10_LVL         0x04
38#define ELCRS_INT9_LVL          0x02
39#define ELCRS_INT8_LVL          0x01
40#define ELCRM_INT7_LVL          0x80
41#define ELCRM_INT6_LVL          0x40
42#define ELCRM_INT5_LVL          0x20
43#define ELCRM_INT4_LVL          0x10
44#define ELCRM_INT3_LVL          0x8
45#define ELCRM_INT2_LVL          0x4
46#define ELCRM_INT1_LVL          0x2
47#define ELCRM_INT0_LVL          0x1
48
49    /* PIC's command and mask registers */
50#define PIC_MASTER_COMMAND_IO_PORT              0x20    /* Master PIC command register */
51#define PIC_SLAVE_COMMAND_IO_PORT               0xa0    /* Slave PIC command register */
52#define PIC_MASTER_IMR_IO_PORT                  0x21    /* Master PIC Interrupt Mask Register */
53#define PIC_SLAVE_IMR_IO_PORT                   0xa1    /* Slave PIC Interrupt Mask Register */
54
55    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
56#define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
57#define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
58#define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
59
60#ifndef ASM
61
62#ifdef __cplusplus
63extern "C" {
64#endif
65
66/*
67 * rtems_irq_number Definitions
68 */
69
70/*
71 * ISA IRQ handler related definitions
72 */
73#define BSP_ISA_IRQ_NUMBER              (16)
74#define BSP_ISA_IRQ_LOWEST_OFFSET       (0)
75#define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
76/*
77 * PCI IRQ handlers related definitions
78 * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
79 */
80#ifndef qemu
81#define BSP_PCI_IRQ_NUMBER              (16)
82#else
83#define BSP_PCI_IRQ_NUMBER              (0)
84#endif
85#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_ISA_IRQ_NUMBER)
86#define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
87/*
88 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
89 * handler might be connected
90 */
91#define BSP_PROCESSOR_IRQ_NUMBER        (1)
92#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
93#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
94/* Misc vectors for OPENPIC irqs (IPI, timers)
95 */
96#ifndef qemu
97#define BSP_MISC_IRQ_NUMBER             (8)
98#else
99#define BSP_MISC_IRQ_NUMBER             (0)
100#endif
101
102#define BSP_MISC_IRQ_LOWEST_OFFSET      (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
103#define BSP_MISC_IRQ_MAX_OFFSET         (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
104/*
105 * Summary
106 */
107#define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
108#define BSP_LOWEST_OFFSET               (BSP_ISA_IRQ_LOWEST_OFFSET)
109#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
110/*
111 * Some ISA IRQ symbolic name definition
112 */
113#define BSP_ISA_PERIODIC_TIMER          (0)
114#define BSP_ISA_KEYBOARD                (1)
115#define BSP_ISA_UART_COM2_IRQ           (3)
116#define BSP_ISA_UART_COM1_IRQ           (4)
117#define BSP_ISA_RT_TIMER1               (8)
118#define BSP_ISA_RT_TIMER3               (10)
119/*
120 * Some PCI IRQ symbolic name definition
121 */
122#define BSP_PCI_IRQ0                    (BSP_PCI_IRQ_LOWEST_OFFSET)
123#if     BSP_PCI_IRQ_NUMBER > 0
124#define BSP_PCI_ISA_BRIDGE_IRQ          (BSP_PCI_IRQ0)
125#endif
126
127#if defined(mvme2100)
128#define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
129#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
130#define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
131#define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
132#define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
133#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
134#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
135#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
136#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
137#define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
138#define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
139#define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
140#else
141#define BSP_UART_COM1_IRQ               BSP_ISA_UART_COM1_IRQ
142#define BSP_UART_COM2_IRQ               BSP_ISA_UART_COM2_IRQ
143#endif
144
145/*
146 * Some Processor execption handled as RTEMS IRQ symbolic name definition
147 */
148#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
149
150
151/*
152 * Type definition for RTEMS managed interrupts
153 */
154typedef unsigned short rtems_i8259_masks;
155
156extern  volatile rtems_i8259_masks i8259s_cache;
157
158/*-------------------------------------------------------------------------+
159| Function Prototypes.
160+--------------------------------------------------------------------------*/
161/*
162 * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
163 */
164void BSP_i8259s_init(void);
165
166/*
167 * function to disable a particular irq at 8259 level. After calling
168 * this function, even if the device asserts the interrupt line it will
169 * not be propagated further to the processor
170 *
171 * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
172 *          a value < 0 on error.
173 */
174int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
175/*
176 * function to enable a particular irq at 8259 level. After calling
177 * this function, if the device asserts the interrupt line it will
178 * be propagated further to the processor
179 */
180int BSP_irq_enable_at_i8259s            (const rtems_irq_number irqLine);
181/*
182 * function to acknowledge a particular irq at 8259 level. After calling
183 * this function, if a device asserts an enabled interrupt line it will
184 * be propagated further to the processor. Mainly usefull for people
185 * writing raw handlers as this is automagically done for RTEMS managed
186 * handlers.
187 */
188int BSP_irq_ack_at_i8259s               (const rtems_irq_number irqLine);
189/*
190 * function to check if a particular irq is enabled at 8259 level. After calling
191 */
192int BSP_irq_enabled_at_i8259s           (const rtems_irq_number irqLine);
193
194extern void BSP_rtems_irq_mng_init(unsigned cpuId);
195extern void BSP_i8259s_init(void);
196
197/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
198#include <bsp/irq_supp.h>
199
200#ifdef __cplusplus
201};
202#endif
203
204#endif
205#endif
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