source: rtems/bsps/powerpc/motorola_powerpc/include/bsp/irq.h @ 2f56b737

5
Last change on this file since 2f56b737 was 2f56b737, checked in by Chris Johns <chrisj@…>, on 02/12/21 at 19:35:40

Update motorola_power to irq-generic interrupt management

  • Add support to the BSP to enable irq-generic management
  • Update the powerpc shared irq code to support irq-generic. This is an opt in option for existing powerpc bsps. This change should be simpler now
  • Fix a number of issues in ISA IRQ controller handling by porting fixes from the i386 (PC) BSP

Closes #4247
Closes #4248
  • Property mode set to 100644
File size: 7.1 KB
Line 
1/* irq.h
2 *
3 *  This include file describe the data structure and the functions implemented
4 *  by RTEMS to write interrupt handlers.
5 *
6 *  Copyright (C) 1999 valette@crf.canon.fr
7 *
8 *  This code is heavilly inspired by the public specification of STREAM V2
9 *  that can be found at :
10 *
11 *      <http://www.chorus.com/Documentation/index.html> by following
12 *  the STREAM API Specification Document link.
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef BSP_POWERPC_IRQ_H
20#define BSP_POWERPC_IRQ_H
21
22#ifndef BSP_SHARED_HANDLER_SUPPORT
23#define BSP_SHARED_HANDLER_SUPPORT      1
24#endif
25
26#include <rtems/irq.h>
27
28/*
29 * Switch to using the generic support. Remove this when all BSPs have
30 * been converted.
31 */
32#define BSP_POWERPC_IRQ_GENERIC_SUPPORT 1
33
34/*
35 * 8259 edge/level control definitions at VIA
36 */
37#define ISA8259_M_ELCR          0x4d0
38#define ISA8259_S_ELCR          0x4d1
39
40#define ELCRS_INT15_LVL         0x80
41#define ELCRS_INT14_LVL         0x40
42#define ELCRS_INT13_LVL         0x20
43#define ELCRS_INT12_LVL         0x10
44#define ELCRS_INT11_LVL         0x08
45#define ELCRS_INT10_LVL         0x04
46#define ELCRS_INT9_LVL          0x02
47#define ELCRS_INT8_LVL          0x01
48#define ELCRM_INT7_LVL          0x80
49#define ELCRM_INT6_LVL          0x40
50#define ELCRM_INT5_LVL          0x20
51#define ELCRM_INT4_LVL          0x10
52#define ELCRM_INT3_LVL          0x8
53#define ELCRM_INT2_LVL          0x4
54#define ELCRM_INT1_LVL          0x2
55#define ELCRM_INT0_LVL          0x1
56
57    /* PIC's command and mask registers */
58#define PIC_MASTER_COMMAND_IO_PORT              0x20    /* Master PIC command register */
59#define PIC_SLAVE_COMMAND_IO_PORT               0xa0    /* Slave PIC command register */
60#define PIC_MASTER_IMR_IO_PORT                  0x21    /* Master PIC Interrupt Mask Register */
61#define PIC_SLAVE_IMR_IO_PORT                   0xa1    /* Slave PIC Interrupt Mask Register */
62
63    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
64#define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
65#define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
66#define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
67
68#ifndef ASM
69
70#ifdef __cplusplus
71extern "C" {
72#endif
73
74/*
75 * rtems_irq_number Definitions
76 */
77
78/*
79 * ISA IRQ handler related definitions
80 */
81#define BSP_ISA_IRQ_NUMBER              (16)
82#define BSP_ISA_IRQ_LOWEST_OFFSET       (0)
83#define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
84/*
85 * PCI IRQ handlers related definitions
86 * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
87 */
88#ifndef qemu
89#define BSP_PCI_IRQ_NUMBER              (16)
90#else
91#define BSP_PCI_IRQ_NUMBER              (0)
92#endif
93#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_ISA_IRQ_NUMBER)
94#define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
95/*
96 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
97 * handler might be connected
98 */
99#define BSP_PROCESSOR_IRQ_NUMBER        (1)
100#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
101#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
102/* Misc vectors for OPENPIC irqs (IPI, timers)
103 */
104#ifndef qemu
105#define BSP_MISC_IRQ_NUMBER             (8)
106#else
107#define BSP_MISC_IRQ_NUMBER             (0)
108#endif
109
110#define BSP_MISC_IRQ_LOWEST_OFFSET      (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
111#define BSP_MISC_IRQ_MAX_OFFSET         (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
112/*
113 * Summary
114 */
115#define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
116#define BSP_LOWEST_OFFSET               (BSP_ISA_IRQ_LOWEST_OFFSET)
117#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
118#define BSP_INTERRUPT_VECTOR_MIN        (BSP_LOWEST_OFFSET)
119#define BSP_INTERRUPT_VECTOR_MAX        (BSP_MAX_OFFSET)
120/*
121 * Some ISA IRQ symbolic name definition
122 */
123#define BSP_ISA_PERIODIC_TIMER          (0)
124#define BSP_ISA_KEYBOARD                (1)
125#define BSP_ISA_UART_COM2_IRQ           (3)
126#define BSP_ISA_UART_COM1_IRQ           (4)
127#define BSP_ISA_RT_TIMER1               (8)
128#define BSP_ISA_RT_TIMER3               (10)
129/*
130 * Some PCI IRQ symbolic name definition
131 */
132#define BSP_PCI_IRQ0                    (BSP_PCI_IRQ_LOWEST_OFFSET)
133#if     BSP_PCI_IRQ_NUMBER > 0
134#define BSP_PCI_ISA_BRIDGE_IRQ          (BSP_PCI_IRQ0)
135#endif
136
137#if defined(mvme2100)
138#define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
139#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
140#define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
141#define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
142#define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
143#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
144#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
145#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
146#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
147#define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
148#define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
149#define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
150#else
151#define BSP_UART_COM1_IRQ               BSP_ISA_UART_COM1_IRQ
152#define BSP_UART_COM2_IRQ               BSP_ISA_UART_COM2_IRQ
153#endif
154
155/*
156 * Some Processor execption handled as RTEMS IRQ symbolic name definition
157 */
158#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
159
160
161/*
162 * Type definition for RTEMS managed interrupts
163 */
164typedef unsigned short rtems_i8259_masks;
165
166extern  volatile rtems_i8259_masks i8259s_cache;
167
168/*-------------------------------------------------------------------------+
169| Function Prototypes.
170+--------------------------------------------------------------------------*/
171/*
172 * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
173 */
174void BSP_i8259s_init(void);
175
176/*
177 * function to disable a particular irq at 8259 level. After calling
178 * this function, even if the device asserts the interrupt line it will
179 * not be propagated further to the processor
180 *
181 * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
182 *          a value < 0 on error.
183 */
184int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
185/*
186 * function to enable a particular irq at 8259 level. After calling
187 * this function, if the device asserts the interrupt line it will
188 * be propagated further to the processor
189 */
190int BSP_irq_enable_at_i8259s            (const rtems_irq_number irqLine);
191/*
192 * function to acknowledge a particular irq at 8259 level. After calling
193 * this function, if a device asserts an enabled interrupt line it will
194 * be propagated further to the processor. Mainly usefull for people
195 * writing raw handlers as this is automagically done for RTEMS managed
196 * handlers.
197 */
198int BSP_irq_ack_at_i8259s               (const rtems_irq_number irqLine);
199/*
200 * function to check if a particular irq is enabled at 8259 level. After calling
201 */
202int BSP_irq_enabled_at_i8259s           (const rtems_irq_number irqLine);
203
204unsigned short BSP_irq_suspend_i8259s(unsigned short mask);
205void BSP_irq_resume_i8259s(unsigned short in_progress_save);
206
207extern void BSP_rtems_irq_mng_init(unsigned cpuId);
208extern void BSP_i8259s_init(void);
209
210/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
211#include <bsp/irq_supp.h>
212
213#ifdef __cplusplus
214};
215#endif
216
217#endif
218#endif
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