source: rtems/bsps/powerpc/motorola_powerpc/include/bsp/irq.h @ 2afb22b

Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 6.7 KB
Line 
1/* irq.h
2 *
3 *  This include file describe the data structure and the functions implemented
4 *  by RTEMS to write interrupt handlers.
5 *
6 *  Copyright (C) 1999 valette@crf.canon.fr
7 *
8 *  This code is heavilly inspired by the public specification of STREAM V2
9 *  that can be found at :
10 *
11 *      <http://www.chorus.com/Documentation/index.html> by following
12 *  the STREAM API Specification Document link.
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef BSP_POWERPC_IRQ_H
20#define BSP_POWERPC_IRQ_H
21
22#define BSP_SHARED_HANDLER_SUPPORT      1
23#include <rtems/irq.h>
24
25/*
26 * 8259 edge/level control definitions at VIA
27 */
28#define ISA8259_M_ELCR          0x4d0
29#define ISA8259_S_ELCR          0x4d1
30
31#define ELCRS_INT15_LVL         0x80
32#define ELCRS_INT14_LVL         0x40
33#define ELCRS_INT13_LVL         0x20
34#define ELCRS_INT12_LVL         0x10
35#define ELCRS_INT11_LVL         0x08
36#define ELCRS_INT10_LVL         0x04
37#define ELCRS_INT9_LVL          0x02
38#define ELCRS_INT8_LVL          0x01
39#define ELCRM_INT7_LVL          0x80
40#define ELCRM_INT6_LVL          0x40
41#define ELCRM_INT5_LVL          0x20
42#define ELCRM_INT4_LVL          0x10
43#define ELCRM_INT3_LVL          0x8
44#define ELCRM_INT2_LVL          0x4
45#define ELCRM_INT1_LVL          0x2
46#define ELCRM_INT0_LVL          0x1
47
48    /* PIC's command and mask registers */
49#define PIC_MASTER_COMMAND_IO_PORT              0x20    /* Master PIC command register */
50#define PIC_SLAVE_COMMAND_IO_PORT               0xa0    /* Slave PIC command register */
51#define PIC_MASTER_IMR_IO_PORT                  0x21    /* Master PIC Interrupt Mask Register */
52#define PIC_SLAVE_IMR_IO_PORT                   0xa1    /* Slave PIC Interrupt Mask Register */
53
54    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
55#define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
56#define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
57#define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
58
59#ifndef ASM
60
61#ifdef __cplusplus
62extern "C" {
63#endif
64
65/*
66 * rtems_irq_number Definitions
67 */
68
69/*
70 * ISA IRQ handler related definitions
71 */
72#define BSP_ISA_IRQ_NUMBER              (16)
73#define BSP_ISA_IRQ_LOWEST_OFFSET       (0)
74#define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
75/*
76 * PCI IRQ handlers related definitions
77 * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
78 */
79#ifndef qemu
80#define BSP_PCI_IRQ_NUMBER              (16)
81#else
82#define BSP_PCI_IRQ_NUMBER              (0)
83#endif
84#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_ISA_IRQ_NUMBER)
85#define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
86/*
87 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
88 * handler might be connected
89 */
90#define BSP_PROCESSOR_IRQ_NUMBER        (1)
91#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
92#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
93/* Misc vectors for OPENPIC irqs (IPI, timers)
94 */
95#ifndef qemu
96#define BSP_MISC_IRQ_NUMBER             (8)
97#else
98#define BSP_MISC_IRQ_NUMBER             (0)
99#endif
100
101#define BSP_MISC_IRQ_LOWEST_OFFSET      (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
102#define BSP_MISC_IRQ_MAX_OFFSET         (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
103/*
104 * Summary
105 */
106#define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
107#define BSP_LOWEST_OFFSET               (BSP_ISA_IRQ_LOWEST_OFFSET)
108#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
109/*
110 * Some ISA IRQ symbolic name definition
111 */
112#define BSP_ISA_PERIODIC_TIMER          (0)
113#define BSP_ISA_KEYBOARD                (1)
114#define BSP_ISA_UART_COM2_IRQ           (3)
115#define BSP_ISA_UART_COM1_IRQ           (4)
116#define BSP_ISA_RT_TIMER1               (8)
117#define BSP_ISA_RT_TIMER3               (10)
118/*
119 * Some PCI IRQ symbolic name definition
120 */
121#define BSP_PCI_IRQ0                    (BSP_PCI_IRQ_LOWEST_OFFSET)
122#if     BSP_PCI_IRQ_NUMBER > 0
123#define BSP_PCI_ISA_BRIDGE_IRQ          (BSP_PCI_IRQ0)
124#endif
125
126#if defined(mvme2100)
127#define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
128#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
129#define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
130#define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
131#define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
132#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
133#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
134#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
135#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
136#define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
137#define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
138#define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
139#else
140#define BSP_UART_COM1_IRQ               BSP_ISA_UART_COM1_IRQ
141#define BSP_UART_COM2_IRQ               BSP_ISA_UART_COM2_IRQ
142#endif
143
144/*
145 * Some Processor execption handled as RTEMS IRQ symbolic name definition
146 */
147#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
148
149
150/*
151 * Type definition for RTEMS managed interrupts
152 */
153typedef unsigned short rtems_i8259_masks;
154
155extern  volatile rtems_i8259_masks i8259s_cache;
156
157/*-------------------------------------------------------------------------+
158| Function Prototypes.
159+--------------------------------------------------------------------------*/
160/*
161 * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
162 */
163void BSP_i8259s_init(void);
164
165/*
166 * function to disable a particular irq at 8259 level. After calling
167 * this function, even if the device asserts the interrupt line it will
168 * not be propagated further to the processor
169 *
170 * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
171 *          a value < 0 on error.
172 */
173int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
174/*
175 * function to enable a particular irq at 8259 level. After calling
176 * this function, if the device asserts the interrupt line it will
177 * be propagated further to the processor
178 */
179int BSP_irq_enable_at_i8259s            (const rtems_irq_number irqLine);
180/*
181 * function to acknowledge a particular irq at 8259 level. After calling
182 * this function, if a device asserts an enabled interrupt line it will
183 * be propagated further to the processor. Mainly usefull for people
184 * writing raw handlers as this is automagically done for RTEMS managed
185 * handlers.
186 */
187int BSP_irq_ack_at_i8259s               (const rtems_irq_number irqLine);
188/*
189 * function to check if a particular irq is enabled at 8259 level. After calling
190 */
191int BSP_irq_enabled_at_i8259s           (const rtems_irq_number irqLine);
192
193extern void BSP_rtems_irq_mng_init(unsigned cpuId);
194extern void BSP_i8259s_init(void);
195
196/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
197#include <bsp/irq_supp.h>
198
199#ifdef __cplusplus
200};
201#endif
202
203#endif
204#endif
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