source: rtems/bsps/powerpc/motorola_powerpc/include/bsp.h @ c991eeec

5
Last change on this file since c991eeec was c991eeec, checked in by Sebastian Huber <sebastian.huber@…>, on 03/04/19 at 14:32:15

bsps: Adjust bsp.h Doxygen groups

Update #3706.
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1/**
2 * @file
3 *
4 * @ingroup RTEMSBSPsPowerPCMotorola
5 *
6 * @brief Global BSP definitions.
7 */
8
9/*
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.org/license/LICENSE.
14 */
15#ifndef LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H
16#define LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H
17
18/**
19 * @defgroup RTEMSBSPsPowerPCMotorola Motorola
20 *
21 * @ingroup RTEMSBSPsPowerPC
22 *
23 * @brief Motorola Board Support Package.
24 *
25 * @{
26 */
27
28#include <bspopts.h>
29#include <bsp/default-initial-extension.h>
30
31#include <rtems.h>
32#include <libcpu/io.h>
33#include <bsp/vectors.h>
34 
35#ifdef qemu
36#include <rtems/bspcmdline.h>
37#endif
38 
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43/*
44 * diagram illustrating the role of the configuration
45 * constants
46 *  PCI_MEM_WIN0:        CPU starting addr where PCI memory space is visible
47 *  PCI_MEM_BASE:        CPU address of PCI mem addr. zero. (regardless of this
48 *                       address being 'visible' or not!).
49 * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME
50 * _VME_A32_WIN0_ON_VME: VME address of that same window
51 *
52 * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between
53 * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI
54 * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to
55 * the base address read from PCI config.space in order to translate that
56 * into a CPU address.
57 *
58 * NOTE: VME addresses should NEVER be translated using these constants!
59 *       they are strictly for BSP internal use. Drivers etc. should use
60 *       the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs).
61 *
62 *           CPU ADDR                  PCI_ADDR                                VME ADDR
63 *
64 *           00000000                  XXXXXXXX                                XXXXXXXX
65 *    ^  ^   ........
66 *    |  |
67 *    |  |  e.g., RAM                  XXXXXXXX
68 *    |  |                                                                     00000000
69 *    |  |  .........                                                          ^
70 *    |  |            (possible offset                                         |
71 *    |  |             between pci and XXXXXXXX                                | ......
72 *    |  |             cpu addresses)                                          |
73 *    |  v                                                                     |
74 *    |  PCI_MEM_BASE  ------------->  00000000 ---------------                |
75 *    |     ........                   ........               ^                |
76 *    |                                invisible              |                |
77 *    |     ........                   from CPU               |                |
78 *    v                                                       |                |
79 *       PCI_MEM_WIN0 =============  first visible PCI addr   |                |
80 *                                                            |                |
81 *        pci devices   pci window                            |                |
82 *       visible here                                         v                v
83 *                      mapped by   ========== _VME_A32_WIN0_ON_PCI =======  _VME_A32_WIN0_ON_VME
84 *                                                 vme window
85 *        VME devices   hostbridge                 mapped by
86 *       visible here                              universe
87 *                    =====================================================
88 *
89 */
90
91/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
92#if defined(mvme2100)
93#define _IO_BASE                CHRP_ISA_IO_BASE
94#define _ISA_MEM_BASE           CHRP_ISA_MEM_BASE
95/* address of our ram on the PCI bus   */
96#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
97/* offset of pci memory as seen from the CPU */
98#define PCI_MEM_BASE            0
99/* where (in CPU addr. space) does the PCI window start */
100#define PCI_MEM_WIN0            0x80000000
101
102#else
103#define _IO_BASE                PREP_ISA_IO_BASE
104#define _ISA_MEM_BASE           PREP_ISA_MEM_BASE
105#ifndef qemu
106/* address of our ram on the PCI bus   */
107#define PCI_DRAM_OFFSET         PREP_PCI_DRAM_OFFSET
108/* offset of pci memory as seen from the CPU */
109#define PCI_MEM_BASE            PREP_ISA_MEM_BASE
110#define PCI_MEM_WIN0            0
111#else
112#define PCI_DRAM_OFFSET         0
113#define PCI_MEM_BASE            0
114#define PCI_MEM_WIN0            PREP_ISA_MEM_BASE
115#endif
116#endif
117
118
119/*
120 *  Base address definitions for several devices
121 *
122 *  MVME2100 is very similar but has fewer devices and uses on-CPU EPIC
123 *  implementation of OpenPIC controller.  It also cannot be probed to
124 *  find out what it is which is VERY different from other Motorola boards.
125 */
126
127#if defined(mvme2100)
128#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000)
129/* #define BSP_UART_IOBASE_COM1     (0xffe10000) */
130#define BSP_OPEN_PIC_BASE_OFFSET 0x40000
131
132#define MVME_HAS_DEC21140
133#else
134#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8)
135#define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8)
136
137#if ! defined(qemu)
138#define BSP_KBD_IOBASE       ((_IO_BASE)+0x60)
139#define BSP_VGA_IOBASE       ((_IO_BASE)+0x3c0)
140#endif
141
142#if defined(mvme2300)
143#define MVME_HAS_DEC21140
144#endif
145#endif
146
147#define BSP_CONSOLE_PORT        BSP_UART_COM1
148#define BSP_UART_BAUD_BASE      115200
149
150struct rtems_bsdnet_ifconfig;
151
152#if defined(MVME_HAS_DEC21140)
153#define RTEMS_BSP_NETWORK_DRIVER_NAME "dc1"
154#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach
155extern int rtems_dec21140_driver_attach(struct rtems_bsdnet_ifconfig *, int);
156#endif
157
158#ifdef qemu
159#define RTEMS_BSP_NETWORK_DRIVER_NAME "ne1"
160#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach
161extern int rtems_ne_driver_attach(struct rtems_bsdnet_ifconfig *, int);
162
163RTEMS_INLINE_ROUTINE const char* bsp_cmdline_arg(const char* arg)
164{
165  return rtems_bsp_cmdline_get_param_raw(arg);
166}
167#endif
168
169#ifdef qemu
170#define BSP_IDLE_TASK_BODY bsp_ppc_idle_task_body
171extern void *bsp_ppc_idle_task_body(uintptr_t arg);
172#endif
173
174#include <bsp/openpic.h>
175/* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver
176 * to implement VME IRQ priorities in software.
177 * Note that this requires support by the interrupt controller
178 * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c)
179 * and the BSP-specific universe initialization/configuration
180 * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c)
181 *
182 * ********* IMPORTANT NOTE ********
183 * When deriving from this file (new BSPs)
184 * DO NOT define "BSP_PIC_DO_EOI" if you don't know what
185 * you are doing i.e., w/o implementing the required pieces
186 * mentioned above.
187 * ********* IMPORTANT NOTE ********
188 */
189#define BSP_PIC_DO_EOI openpic_eoi(0)
190
191#ifndef ASM
192#define outport_byte(port,value) outb(value,port)
193#define outport_word(port,value) outw(value,port)
194#define outport_long(port,value) outl(value,port)
195
196#define inport_byte(port,value) (value = inb(port))
197#define inport_word(port,value) (value = inw(port))
198#define inport_long(port,value) (value = inl(port))
199
200/*
201 * Vital Board data Start using DATA RESIDUAL
202 */
203
204/*
205 * Total memory using RESIDUAL DATA
206 */
207extern unsigned int BSP_mem_size;
208/*
209 * Start of the heap
210 */
211extern unsigned int BSP_heap_start;
212/*
213 * PCI Bus Frequency
214 */
215extern unsigned int BSP_bus_frequency;
216/*
217 * processor clock frequency
218 */
219extern unsigned int BSP_processor_frequency;
220/*
221 * Time base divisior (how many tick for 1 second).
222 */
223extern unsigned int BSP_time_base_divisor;
224
225/*
226 * String passed by the bootloader.
227 */
228extern char *BSP_commandline_string;
229
230#define BSP_Convert_decrementer( _value ) \
231  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
232
233/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */
234extern int BSP_disconnect_clock_handler (void);
235extern int BSP_connect_clock_handler (void);
236
237/* clear hostbridge errors
238 *
239 * NOTE: The routine returns always (-1) if 'enableMCP==1'
240 *       [semantics needed by libbspExt] if the MCP input is not wired.
241 *       It returns and clears the error bits of the PCI status register.
242 *       MCP support is disabled because:
243 *         a) the 2100 has no raven chip
244 *         b) the raven (2300) would raise machine check interrupts
245 *            on PCI config space access to empty slots.
246 */
247extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
248
249/*
250 * Prototypes for methods called only from .S for dependency tracking
251 */
252char *save_boot_params(
253  void *r3,
254  void *r4,
255  void *r5,
256  char *cmdline_start,
257  char *cmdline_end
258);
259void zero_bss(void);
260
261/*
262 * Prototypes for BSP methods which cross file boundaries
263 */
264void VIA_isa_bridge_interrupts_setup(void);
265
266#endif
267
268#ifdef __cplusplus
269};
270#endif
271
272/** @} */
273
274#endif
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