[23090f33] | 1 | /* |
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| 2 | * |
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| 3 | * The license and distribution terms for this file may be |
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[0c875c6a] | 4 | * found in the file LICENSE in this distribution or at |
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[c499856] | 5 | * http://www.rtems.org/license/LICENSE. |
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[23090f33] | 6 | */ |
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[9cff822a] | 7 | #ifndef LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H |
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| 8 | #define LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H |
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[23090f33] | 9 | |
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| 10 | #include <bspopts.h> |
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[a052181] | 11 | #include <bsp/default-initial-extension.h> |
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[23090f33] | 12 | |
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| 13 | #include <rtems.h> |
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| 14 | #include <libcpu/io.h> |
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| 15 | #include <bsp/vectors.h> |
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[f616734f] | 16 | |
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| 17 | #ifdef qemu |
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| 18 | #include <rtems/bspcmdline.h> |
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| 19 | #endif |
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| 20 | |
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| 21 | #ifdef __cplusplus |
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| 22 | extern "C" { |
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| 23 | #endif |
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[23090f33] | 24 | |
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[be45f8e] | 25 | /* |
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| 26 | * diagram illustrating the role of the configuration |
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| 27 | * constants |
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| 28 | * PCI_MEM_WIN0: CPU starting addr where PCI memory space is visible |
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| 29 | * PCI_MEM_BASE: CPU address of PCI mem addr. zero. (regardless of this |
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| 30 | * address being 'visible' or not!). |
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| 31 | * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME |
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| 32 | * _VME_A32_WIN0_ON_VME: VME address of that same window |
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| 33 | * |
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| 34 | * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between |
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| 35 | * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI |
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| 36 | * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to |
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| 37 | * the base address read from PCI config.space in order to translate that |
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| 38 | * into a CPU address. |
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| 39 | * |
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| 40 | * NOTE: VME addresses should NEVER be translated using these constants! |
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| 41 | * they are strictly for BSP internal use. Drivers etc. should use |
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| 42 | * the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs). |
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[ac7af4a] | 43 | * |
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[be45f8e] | 44 | * CPU ADDR PCI_ADDR VME ADDR |
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[ac7af4a] | 45 | * |
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[be45f8e] | 46 | * 00000000 XXXXXXXX XXXXXXXX |
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[ac7af4a] | 47 | * ^ ^ ........ |
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[be45f8e] | 48 | * | | |
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| 49 | * | | e.g., RAM XXXXXXXX |
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| 50 | * | | 00000000 |
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| 51 | * | | ......... ^ |
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| 52 | * | | (possible offset | |
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| 53 | * | | between pci and XXXXXXXX | ...... |
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| 54 | * | | cpu addresses) | |
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| 55 | * | v | |
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| 56 | * | PCI_MEM_BASE -------------> 00000000 --------------- | |
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| 57 | * | ........ ........ ^ | |
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| 58 | * | invisible | | |
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| 59 | * | ........ from CPU | | |
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| 60 | * v | | |
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| 61 | * PCI_MEM_WIN0 ============= first visible PCI addr | | |
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| 62 | * | | |
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| 63 | * pci devices pci window | | |
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| 64 | * visible here v v |
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| 65 | * mapped by ========== _VME_A32_WIN0_ON_PCI ======= _VME_A32_WIN0_ON_VME |
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| 66 | * vme window |
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| 67 | * VME devices hostbridge mapped by |
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| 68 | * visible here universe |
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| 69 | * ===================================================== |
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[ac7af4a] | 70 | * |
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[be45f8e] | 71 | */ |
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| 72 | |
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[f9877d25] | 73 | /* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */ |
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| 74 | #if defined(mvme2100) |
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| 75 | #define _IO_BASE CHRP_ISA_IO_BASE |
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| 76 | #define _ISA_MEM_BASE CHRP_ISA_MEM_BASE |
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| 77 | /* address of our ram on the PCI bus */ |
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| 78 | #define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET |
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[be45f8e] | 79 | /* offset of pci memory as seen from the CPU */ |
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[cc2fcc1] | 80 | #define PCI_MEM_BASE 0 |
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[be45f8e] | 81 | /* where (in CPU addr. space) does the PCI window start */ |
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[ac7af4a] | 82 | #define PCI_MEM_WIN0 0x80000000 |
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[f9877d25] | 83 | |
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| 84 | #else |
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| 85 | #define _IO_BASE PREP_ISA_IO_BASE |
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[23090f33] | 86 | #define _ISA_MEM_BASE PREP_ISA_MEM_BASE |
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[f616734f] | 87 | #ifndef qemu |
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[23090f33] | 88 | /* address of our ram on the PCI bus */ |
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| 89 | #define PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET |
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| 90 | /* offset of pci memory as seen from the CPU */ |
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| 91 | #define PCI_MEM_BASE PREP_ISA_MEM_BASE |
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[cc2fcc1] | 92 | #define PCI_MEM_WIN0 0 |
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[f616734f] | 93 | #else |
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| 94 | #define PCI_DRAM_OFFSET 0 |
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| 95 | #define PCI_MEM_BASE 0 |
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| 96 | #define PCI_MEM_WIN0 PREP_ISA_MEM_BASE |
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| 97 | #endif |
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[f9877d25] | 98 | #endif |
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| 99 | |
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[23090f33] | 100 | |
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| 101 | /* |
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[f9877d25] | 102 | * Base address definitions for several devices |
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[23090f33] | 103 | * |
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[f9877d25] | 104 | * MVME2100 is very similar but has fewer devices and uses on-CPU EPIC |
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| 105 | * implementation of OpenPIC controller. It also cannot be probed to |
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| 106 | * find out what it is which is VERY different from other Motorola boards. |
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[23090f33] | 107 | */ |
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[f9877d25] | 108 | |
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| 109 | #if defined(mvme2100) |
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| 110 | #define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000) |
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| 111 | /* #define BSP_UART_IOBASE_COM1 (0xffe10000) */ |
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| 112 | #define BSP_OPEN_PIC_BASE_OFFSET 0x40000 |
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| 113 | |
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| 114 | #define MVME_HAS_DEC21140 |
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| 115 | #else |
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[23090f33] | 116 | #define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8) |
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| 117 | #define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8) |
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[f9877d25] | 118 | |
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[f616734f] | 119 | #if ! defined(qemu) |
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[23090f33] | 120 | #define BSP_KBD_IOBASE ((_IO_BASE)+0x60) |
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| 121 | #define BSP_VGA_IOBASE ((_IO_BASE)+0x3c0) |
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[f616734f] | 122 | #endif |
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[23090f33] | 123 | |
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[f9877d25] | 124 | #if defined(mvme2300) |
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| 125 | #define MVME_HAS_DEC21140 |
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| 126 | #endif |
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| 127 | #endif |
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| 128 | |
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[23090f33] | 129 | #define BSP_CONSOLE_PORT BSP_UART_COM1 |
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| 130 | #define BSP_UART_BAUD_BASE 115200 |
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[6128a4a] | 131 | |
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[43e74a47] | 132 | #if defined(MVME_HAS_DEC21140) |
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| 133 | struct rtems_bsdnet_ifconfig; |
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| 134 | #define RTEMS_BSP_NETWORK_DRIVER_NAME "dc1" |
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| 135 | #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach |
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| 136 | extern int rtems_dec21140_driver_attach(); |
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| 137 | #endif |
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| 138 | |
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[f616734f] | 139 | #ifdef qemu |
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| 140 | #define RTEMS_BSP_NETWORK_DRIVER_NAME "ne1" |
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| 141 | #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach |
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| 142 | extern int rtems_ne_driver_attach(); |
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| 143 | #endif |
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| 144 | |
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| 145 | #ifdef qemu |
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| 146 | #define BSP_IDLE_TASK_BODY bsp_ppc_idle_task_body |
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| 147 | extern void *bsp_ppc_idle_task_body(uintptr_t arg); |
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| 148 | #endif |
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| 149 | |
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[23090f33] | 150 | #include <bsp/openpic.h> |
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[1102f897] | 151 | /* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver |
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| 152 | * to implement VME IRQ priorities in software. |
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| 153 | * Note that this requires support by the interrupt controller |
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| 154 | * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c) |
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| 155 | * and the BSP-specific universe initialization/configuration |
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| 156 | * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c) |
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| 157 | * |
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| 158 | * ********* IMPORTANT NOTE ******** |
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| 159 | * When deriving from this file (new BSPs) |
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| 160 | * DO NOT define "BSP_PIC_DO_EOI" if you don't know what |
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| 161 | * you are doing i.e., w/o implementing the required pieces |
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| 162 | * mentioned above. |
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| 163 | * ********* IMPORTANT NOTE ******** |
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| 164 | */ |
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[23090f33] | 165 | #define BSP_PIC_DO_EOI openpic_eoi(0) |
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| 166 | |
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| 167 | #ifndef ASM |
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| 168 | #define outport_byte(port,value) outb(value,port) |
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| 169 | #define outport_word(port,value) outw(value,port) |
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| 170 | #define outport_long(port,value) outl(value,port) |
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| 171 | |
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| 172 | #define inport_byte(port,value) (value = inb(port)) |
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| 173 | #define inport_word(port,value) (value = inw(port)) |
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| 174 | #define inport_long(port,value) (value = inl(port)) |
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[f9877d25] | 175 | |
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[23090f33] | 176 | /* |
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| 177 | * Vital Board data Start using DATA RESIDUAL |
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| 178 | */ |
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[f9877d25] | 179 | |
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[23090f33] | 180 | /* |
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| 181 | * Total memory using RESIDUAL DATA |
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| 182 | */ |
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| 183 | extern unsigned int BSP_mem_size; |
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[be45f8e] | 184 | /* |
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| 185 | * Start of the heap |
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| 186 | */ |
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| 187 | extern unsigned int BSP_heap_start; |
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[23090f33] | 188 | /* |
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| 189 | * PCI Bus Frequency |
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| 190 | */ |
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| 191 | extern unsigned int BSP_bus_frequency; |
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| 192 | /* |
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| 193 | * processor clock frequency |
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| 194 | */ |
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| 195 | extern unsigned int BSP_processor_frequency; |
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| 196 | /* |
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| 197 | * Time base divisior (how many tick for 1 second). |
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| 198 | */ |
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| 199 | extern unsigned int BSP_time_base_divisor; |
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| 200 | |
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[1051054] | 201 | /* |
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| 202 | * String passed by the bootloader. |
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| 203 | */ |
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| 204 | extern char *BSP_commandline_string; |
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| 205 | |
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[23090f33] | 206 | #define BSP_Convert_decrementer( _value ) \ |
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| 207 | ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) |
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| 208 | |
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| 209 | /* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ |
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| 210 | extern int BSP_disconnect_clock_handler (void); |
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| 211 | extern int BSP_connect_clock_handler (void); |
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| 212 | |
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| 213 | /* clear hostbridge errors |
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| 214 | * |
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[be45f8e] | 215 | * NOTE: The routine returns always (-1) if 'enableMCP==1' |
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| 216 | * [semantics needed by libbspExt] if the MCP input is not wired. |
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| 217 | * It returns and clears the error bits of the PCI status register. |
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| 218 | * MCP support is disabled because: |
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| 219 | * a) the 2100 has no raven chip |
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| 220 | * b) the raven (2300) would raise machine check interrupts |
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| 221 | * on PCI config space access to empty slots. |
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[23090f33] | 222 | */ |
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| 223 | extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); |
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| 224 | |
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[9ffca502] | 225 | /* |
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| 226 | * Prototypes for methods called only from .S for dependency tracking |
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| 227 | */ |
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| 228 | char *save_boot_params( |
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| 229 | void *r3, |
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| 230 | void *r4, |
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| 231 | void *r5, |
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| 232 | char *cmdline_start, |
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| 233 | char *cmdline_end |
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| 234 | ); |
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| 235 | void zero_bss(void); |
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| 236 | |
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[04d3761] | 237 | /* |
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| 238 | * Prototypes for BSP methods which cross file boundaries |
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| 239 | */ |
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| 240 | void VIA_isa_bridge_interrupts_setup(void); |
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| 241 | |
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[23090f33] | 242 | #endif |
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| 243 | |
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[f616734f] | 244 | #ifdef __cplusplus |
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| 245 | }; |
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| 246 | #endif |
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| 247 | |
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[23090f33] | 248 | #endif |
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