[acc25ee] | 1 | /* |
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| 2 | * head.S -- Bootloader Entry point |
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| 3 | * |
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| 4 | * Copyright (C) 1998, 1999 Gabriel Paubert, paubert@iram.es |
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| 5 | * |
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| 6 | * Modified to compile in RTEMS development environment |
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| 7 | * by Eric Valette |
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| 8 | * |
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| 9 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may be |
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[0c875c6a] | 12 | * found in the file LICENSE in this distribution or at |
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[c499856] | 13 | * http://www.rtems.org/license/LICENSE. |
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[acc25ee] | 14 | */ |
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| 15 | |
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[b7768c55] | 16 | #include <rtems/asm.h> |
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[cd35cf9] | 17 | #include <rtems/score/cpu.h> |
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[acc25ee] | 18 | #include "bootldr.h" |
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[96d81ef5] | 19 | #include <bspopts.h> |
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[9cd4a6e8] | 20 | |
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[6128a4a] | 21 | #define TEST_PPCBUG_CALLS |
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[9cd4a6e8] | 22 | #undef TEST_PPCBUG_CALLS |
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[6128a4a] | 23 | |
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[acc25ee] | 24 | #define FRAME_SIZE 32 |
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[9cd4a6e8] | 25 | #define LOCK_CACHES (HID0_DLOCK | HID0_ILOCK) |
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| 26 | #define INVL_CACHES (HID0_DCI | HID0_ICFI) |
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| 27 | #define ENBL_CACHES (HID0_DCE | HID0_ICE) |
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[acc25ee] | 28 | |
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[96d81ef5] | 29 | #ifndef qemu |
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[acc25ee] | 30 | #define USE_PPCBUG |
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[96d81ef5] | 31 | #endif |
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[6128a4a] | 32 | |
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[9cd4a6e8] | 33 | #define PRINT_CHAR(c) \ |
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| 34 | addi r20,r3,0 ; \ |
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| 35 | li r3,c ; \ |
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| 36 | li r10,0x20 ; \ |
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| 37 | sc ; \ |
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| 38 | addi r3,r20,0 ; \ |
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| 39 | li r10,0x26 ; \ |
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| 40 | sc |
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[6128a4a] | 41 | |
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[acc25ee] | 42 | #define MONITOR_ENTER \ |
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| 43 | mfmsr r10 ; \ |
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| 44 | ori r10,r10,MSR_IP ; \ |
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| 45 | mtmsr r10 ; \ |
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| 46 | li r10,0x63 ; \ |
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| 47 | sc |
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[9cd4a6e8] | 48 | |
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[acc25ee] | 49 | START_GOT |
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| 50 | GOT_ENTRY(_GOT2_TABLE_) |
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| 51 | GOT_ENTRY(_FIXUP_TABLE_) |
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| 52 | GOT_ENTRY(.bss) |
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| 53 | GOT_ENTRY(codemove) |
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| 54 | GOT_ENTRY(0) |
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| 55 | GOT_ENTRY(__bd) |
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| 56 | GOT_ENTRY(moved) |
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| 57 | GOT_ENTRY(_binary_rtems_gz_start) |
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| 58 | GOT_ENTRY(_binary_initrd_gz_start) |
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| 59 | GOT_ENTRY(_binary_initrd_gz_end) |
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[6128a4a] | 60 | #ifdef TEST_PPCBUG_CALLS |
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[acc25ee] | 61 | GOT_ENTRY(banner_start) |
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| 62 | GOT_ENTRY(banner_end) |
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[6128a4a] | 63 | #endif |
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[732a3aee] | 64 | #ifdef USE_PPCBUG |
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| 65 | GOT_ENTRY(nioc_reset_packet) |
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| 66 | #endif |
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[acc25ee] | 67 | END_GOT |
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| 68 | .globl start |
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| 69 | .type start,@function |
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[6128a4a] | 70 | |
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[acc25ee] | 71 | /* Point the stack into the PreP partition header in the x86 reserved |
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[6128a4a] | 72 | * code area, so that simple C routines can be called. |
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[acc25ee] | 73 | */ |
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[6128a4a] | 74 | start: |
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[b56a278] | 75 | #if defined(USE_PPCBUG) && defined(DEBUG) && defined(REENTER_MONITOR) |
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[9cd4a6e8] | 76 | MONITOR_ENTER |
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[acc25ee] | 77 | #endif |
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| 78 | bl 1f |
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| 79 | 1: mflr r1 |
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| 80 | li r0,0 |
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| 81 | stwu r0,start-1b-0x400+0x1b0-FRAME_SIZE(r1) |
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| 82 | stmw r26,FRAME_SIZE-24(r1) |
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| 83 | GET_GOT |
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[9cd4a6e8] | 84 | mfmsr r28 /* Turn off interrupts */ |
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[acc25ee] | 85 | ori r0,r28,MSR_EE |
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| 86 | xori r0,r0,MSR_EE |
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| 87 | mtmsr r0 |
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[6128a4a] | 88 | |
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[acc25ee] | 89 | /* Enable the caches, from now on cr2.eq set means processor is 601 */ |
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[6128a4a] | 90 | |
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[acc25ee] | 91 | mfpvr r0 |
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| 92 | mfspr r29,HID0 |
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| 93 | srwi r0,r0,16 |
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| 94 | cmplwi cr2,r0,1 |
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| 95 | beq 2,2f |
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[9cd4a6e8] | 96 | |
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| 97 | /* |
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| 98 | * commented out, 11/7/2002, gregm. This instruction sequence seems to |
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| 99 | * be pathological on the 603e. |
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| 100 | * |
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[6128a4a] | 101 | |
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[acc25ee] | 102 | #ifndef USE_PPCBUG |
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| 103 | ori r0,r29,ENBL_CACHES|INVL_CACHES|LOCK_CACHES |
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| 104 | xori r0,r0,INVL_CACHES|LOCK_CACHES |
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| 105 | sync |
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| 106 | isync |
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| 107 | mtspr HID0,r0 |
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| 108 | #endif |
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[9cd4a6e8] | 109 | */ |
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[6128a4a] | 110 | |
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[acc25ee] | 111 | 2: bl reloc |
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[6128a4a] | 112 | |
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[acc25ee] | 113 | /* save all the parameters and the orginal msr/hid0/r31 */ |
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| 114 | lwz bd,GOT(__bd) |
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| 115 | stw r3,0(bd) |
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| 116 | stw r4,4(bd) |
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| 117 | stw r5,8(bd) |
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| 118 | stw r6,12(bd) |
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| 119 | stw r7,16(bd) |
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| 120 | stw r8,20(bd) |
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| 121 | stw r9,24(bd) |
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| 122 | stw r10,28(bd) |
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| 123 | stw r28,o_msr(bd) |
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| 124 | stw r29,o_hid0(bd) |
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| 125 | stw r31,o_r31(bd) |
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| 126 | |
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[732a3aee] | 127 | #ifdef USE_PPCBUG |
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| 128 | /* Stop the network interface - otherwise, memory can get |
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| 129 | * corrupted by the IF DMAing data into its old buffers or |
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| 130 | * by writing descriptors... |
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| 131 | */ |
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[6128a4a] | 132 | lwz r3,GOT(nioc_reset_packet) |
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[732a3aee] | 133 | li r10, 0x1d /* .NETCTRL */ |
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| 134 | sc |
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| 135 | #endif |
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| 136 | |
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[6128a4a] | 137 | /* Call the routine to fill boot_data structure from residual data. |
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| 138 | * And to find where the code has to be moved. |
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[acc25ee] | 139 | */ |
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[732a3aee] | 140 | lis r3,__size@sectoff@ha |
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| 141 | addi r3,r3,__size@sectoff@l |
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[acc25ee] | 142 | bl early_setup |
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| 143 | |
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[6128a4a] | 144 | /* Now we need to relocate ourselves, where we are told to. First put a |
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[acc25ee] | 145 | * copy of the codemove routine to some place in memory. |
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[6128a4a] | 146 | * (which may be where the 0x41 partition was loaded, so size is critical). |
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[acc25ee] | 147 | */ |
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| 148 | lwz r4,GOT(codemove) |
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| 149 | li r5,_size_codemove |
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| 150 | lwz r3,mover(bd) |
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| 151 | lwz r6,cache_lsize(bd) |
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[9cd4a6e8] | 152 | |
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[acc25ee] | 153 | bl codemove |
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[9cd4a6e8] | 154 | |
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[acc25ee] | 155 | mtctr r3 # Where the temporary codemove is. |
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| 156 | lwz r3,image(bd) |
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| 157 | lis r5,_edata@sectoff@ha |
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| 158 | lwz r4,GOT(0) # Our own address |
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| 159 | addi r5,r5,_edata@sectoff@l |
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| 160 | lwz r6,cache_lsize(bd) |
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| 161 | lwz r8,GOT(moved) |
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[9cd4a6e8] | 162 | |
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[acc25ee] | 163 | sub r7,r3,r4 # Difference to adjust pointers. |
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| 164 | add r8,r8,r7 |
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| 165 | add r30,r30,r7 |
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| 166 | add bd,bd,r7 |
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[9cd4a6e8] | 167 | |
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[acc25ee] | 168 | /* Call the copy routine but return to the new area. */ |
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[9cd4a6e8] | 169 | |
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[acc25ee] | 170 | mtlr r8 # for the return address |
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| 171 | bctr # returns to the moved instruction |
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[6128a4a] | 172 | |
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[acc25ee] | 173 | /* Establish the new top stack frame. */ |
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| 174 | moved: lwz r1,stack(bd) |
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| 175 | li r0,0 |
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| 176 | stwu r0,-16(r1) |
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| 177 | |
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| 178 | /* relocate again */ |
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[6128a4a] | 179 | bl reloc |
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[acc25ee] | 180 | /* Clear all of BSS */ |
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| 181 | lwz r10,GOT(.bss) |
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| 182 | li r0,__bss_words@sectoff@l |
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| 183 | subi r10,r10,4 |
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| 184 | cmpwi r0,0 |
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| 185 | mtctr r0 |
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| 186 | li r0,0 |
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| 187 | beq 4f |
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| 188 | 3: stwu r0,4(r10) |
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| 189 | bdnz 3b |
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| 190 | |
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| 191 | /* Final memory initialization. First switch to unmapped mode |
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| 192 | * in case the FW had set the MMU on, and flush the TLB to avoid |
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| 193 | * stale entries from interfering. No I/O access is allowed |
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| 194 | * during this time! |
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| 195 | */ |
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[9cd4a6e8] | 196 | 4: |
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[732a3aee] | 197 | #if defined(USE_PPCBUG) && defined(DEBUG) |
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[9cd4a6e8] | 198 | PRINT_CHAR('M') |
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| 199 | #endif |
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| 200 | bl MMUoff |
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| 201 | |
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[732a3aee] | 202 | #if defined(USE_PPCBUG) && defined(DEBUG) |
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[9cd4a6e8] | 203 | PRINT_CHAR('B') |
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| 204 | #endif |
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[acc25ee] | 205 | bl flush_tlb |
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[9cd4a6e8] | 206 | |
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[acc25ee] | 207 | /* Some firmware versions leave stale values in the BATs, it's time |
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| 208 | * to invalidate them to avoid interferences with our own mappings. |
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| 209 | * But the 601 valid bit is in the BATL (IBAT only) and others are in |
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[6128a4a] | 210 | * the [ID]BATU. Bloat, bloat.. fortunately thrown away later. |
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[acc25ee] | 211 | */ |
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[732a3aee] | 212 | #if defined(USE_PPCBUG) && defined(DEBUG) |
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[9cd4a6e8] | 213 | PRINT_CHAR('T') |
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| 214 | #endif |
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[acc25ee] | 215 | li r3,0 |
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| 216 | beq cr2,5f |
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| 217 | mtdbatu 0,r3 |
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| 218 | mtdbatu 1,r3 |
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| 219 | mtdbatu 2,r3 |
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| 220 | mtdbatu 3,r3 |
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| 221 | 5: mtibatu 0,r3 |
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| 222 | mtibatl 0,r3 |
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| 223 | mtibatu 1,r3 |
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| 224 | mtibatl 1,r3 |
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| 225 | mtibatu 2,r3 |
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| 226 | mtibatl 2,r3 |
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| 227 | mtibatu 3,r3 |
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| 228 | mtibatl 3,r3 |
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| 229 | lis r3,__size@sectoff@ha |
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| 230 | addi r3,r3,__size@sectoff@l |
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| 231 | sync # We are going to touch SDR1 ! |
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[732a3aee] | 232 | #if defined(USE_PPCBUG) && defined(DEBUG) |
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[9cd4a6e8] | 233 | PRINT_CHAR('i') |
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| 234 | #endif |
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[acc25ee] | 235 | bl mm_init |
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[6128a4a] | 236 | |
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[732a3aee] | 237 | #if defined(USE_PPCBUG) && defined(DEBUG) |
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[9cd4a6e8] | 238 | PRINT_CHAR('M') |
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| 239 | #endif |
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[acc25ee] | 240 | bl MMUon |
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[6128a4a] | 241 | |
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[acc25ee] | 242 | /* Now we are mapped and can perform I/O if we want */ |
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[6128a4a] | 243 | #ifdef TEST_PPCBUG_CALLS |
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[acc25ee] | 244 | /* Experience seems to show that PPCBug can only be called with the |
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| 245 | * data cache disabled and with MMU disabled. Bummer. |
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[6128a4a] | 246 | */ |
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[acc25ee] | 247 | li r10,0x22 # .OUTLN |
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| 248 | lwz r3,GOT(banner_start) |
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| 249 | lwz r4,GOT(banner_end) |
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| 250 | sc |
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[6128a4a] | 251 | #endif |
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[732a3aee] | 252 | #if defined(USE_PPCBUG) && defined(DEBUG) |
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[9cd4a6e8] | 253 | PRINT_CHAR('H') |
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| 254 | #endif |
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[acc25ee] | 255 | bl setup_hw |
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| 256 | lwz r4,GOT(_binary_rtems_gz_start) |
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| 257 | lis r5,_rtems_gz_size@sectoff@ha |
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| 258 | lwz r6,GOT(_binary_initrd_gz_start) |
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| 259 | lis r3,_rtems_size@sectoff@ha |
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| 260 | lwz r7,GOT(_binary_initrd_gz_end) |
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| 261 | addi r5,r5,_rtems_gz_size@sectoff@l |
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| 262 | addi r3,r3,_rtems_size@sectoff@l |
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| 263 | sub r7,r7,r6 |
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| 264 | bl decompress_kernel |
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| 265 | |
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| 266 | /* Back here we are unmapped and we start the kernel, passing up to eight |
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| 267 | * parameters just in case, only r3 to r7 used for now. Flush the tlb so |
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| 268 | * that the loaded image starts in a clean state. |
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| 269 | */ |
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| 270 | bl flush_tlb |
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| 271 | lwz r3,0(bd) |
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| 272 | lwz r4,4(bd) |
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| 273 | lwz r5,8(bd) |
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| 274 | lwz r6,12(bd) |
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| 275 | lwz r7,16(bd) |
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| 276 | lwz r8,20(bd) |
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| 277 | lwz r9,24(bd) |
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| 278 | lwz r10,28(bd) |
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| 279 | |
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| 280 | lwz r30,0(0) |
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| 281 | mtctr r30 |
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| 282 | /* |
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| 283 | * Linux code again |
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[9cd4a6e8] | 284 | * |
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[acc25ee] | 285 | lis r30,0xdeadc0de@ha |
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| 286 | addi r30,r30,0xdeadc0de@l |
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| 287 | stw r30,0(0) |
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| 288 | li r30,0 |
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| 289 | */ |
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| 290 | dcbst 0,r30 /* Make sure it's in memory ! */ |
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[6128a4a] | 291 | |
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| 292 | /* We just flash invalidate and disable the dcache, unless it's a 601, |
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| 293 | * critical areas have been flushed and we don't care about the stack |
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[acc25ee] | 294 | * and other scratch areas. |
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| 295 | */ |
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| 296 | beq cr2,1f |
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| 297 | mfspr r0,HID0 |
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| 298 | ori r0,r0,HID0_DCI|HID0_DCE |
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| 299 | sync |
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| 300 | mtspr HID0,r0 |
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| 301 | xori r0,r0,HID0_DCI|HID0_DCE |
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| 302 | mtspr HID0,r0 |
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[6128a4a] | 303 | |
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[acc25ee] | 304 | /* Provisional return to FW, works for PPCBug */ |
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[b56a278] | 305 | #if 0 && defined(REENTER_MONITOR) |
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[acc25ee] | 306 | MONITOR_ENTER |
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| 307 | #else |
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| 308 | 1: bctr |
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| 309 | #endif |
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[6128a4a] | 310 | |
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[acc25ee] | 311 | /* relocation function, r30 must point to got2+0x8000 */ |
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[6128a4a] | 312 | reloc: |
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[acc25ee] | 313 | /* Adjust got2 pointers, no need to check for 0, this code already puts |
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[6128a4a] | 314 | * a few entries in the table. |
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[acc25ee] | 315 | */ |
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| 316 | li r0,__got2_entries@sectoff@l |
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| 317 | la r12,GOT(_GOT2_TABLE_) |
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| 318 | lwz r11,GOT(_GOT2_TABLE_) |
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| 319 | mtctr r0 |
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| 320 | sub r11,r12,r11 |
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| 321 | addi r12,r12,-4 |
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| 322 | 1: lwzu r0,4(r12) |
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| 323 | add r0,r0,r11 |
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| 324 | stw r0,0(r12) |
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| 325 | bdnz 1b |
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[6128a4a] | 326 | |
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[acc25ee] | 327 | /* Now adjust the fixups and the pointers to the fixups in case we need |
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[6128a4a] | 328 | * to move ourselves again. |
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| 329 | */ |
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[acc25ee] | 330 | 2: li r0,__fixup_entries@sectoff@l |
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| 331 | lwz r12,GOT(_FIXUP_TABLE_) |
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| 332 | cmpwi r0,0 |
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| 333 | mtctr r0 |
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| 334 | addi r12,r12,-4 |
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| 335 | beqlr |
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| 336 | 3: lwzu r10,4(r12) |
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| 337 | lwzux r0,r10,r11 |
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| 338 | add r0,r0,r11 |
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| 339 | stw r10,0(r12) |
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| 340 | stw r0,0(r10) |
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| 341 | bdnz 3b |
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[6128a4a] | 342 | blr |
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[acc25ee] | 343 | |
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| 344 | /* Set the MMU on and off: code is always mapped 1:1 and does not need MMU, |
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| 345 | * but it does not cost so much to map it also and it catches calls through |
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[6128a4a] | 346 | * NULL function pointers. |
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[acc25ee] | 347 | */ |
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| 348 | .globl MMUon |
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| 349 | .type MMUon,@function |
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[9cd4a6e8] | 350 | MMUon: blr |
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| 351 | nop |
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| 352 | |
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[6128a4a] | 353 | /* |
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[9cd4a6e8] | 354 | mfmsr r0 |
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[acc25ee] | 355 | ori r0,r0,MSR_IR|MSR_DR|MSR_IP |
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| 356 | mflr r11 |
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| 357 | xori r0,r0,MSR_IP |
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| 358 | mtsrr0 r11 |
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| 359 | mtsrr1 r0 |
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| 360 | rfi |
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[9cd4a6e8] | 361 | */ |
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[acc25ee] | 362 | .globl MMUoff |
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| 363 | .type MMUoff,@function |
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[9cd4a6e8] | 364 | MMUoff: blr |
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| 365 | nop |
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[6128a4a] | 366 | |
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[9cd4a6e8] | 367 | /* |
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| 368 | mfmsr r0 |
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[acc25ee] | 369 | ori r0,r0,MSR_IR|MSR_DR|MSR_IP |
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| 370 | mflr r11 |
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| 371 | xori r0,r0,MSR_IR|MSR_DR |
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| 372 | mtsrr0 r11 |
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| 373 | mtsrr1 r0 |
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| 374 | rfi |
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[9cd4a6e8] | 375 | */ |
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[acc25ee] | 376 | |
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| 377 | /* Due to the PPC architecture (and according to the specifications), a |
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[6128a4a] | 378 | * series of tlbie which goes through a whole 256 MB segment always flushes |
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| 379 | * the whole TLB. This is obviously overkill and slow, but who cares ? |
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| 380 | * It takes about 1 ms on a 200 MHz 603e and works even if residual data |
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[acc25ee] | 381 | * get the number of TLB entries wrong. |
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| 382 | */ |
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| 383 | flush_tlb: |
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| 384 | lis r11,0x1000 |
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| 385 | 1: addic. r11,r11,-0x1000 |
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| 386 | tlbie r11 |
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| 387 | bnl 1b |
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| 388 | /* tlbsync is not implemented on 601, so use sync which seems to be a superset |
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| 389 | * of tlbsync in all cases and do not bother with CPU dependant code |
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| 390 | */ |
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[6128a4a] | 391 | sync |
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| 392 | blr |
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[acc25ee] | 393 | |
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| 394 | .globl codemove |
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| 395 | codemove: |
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| 396 | .type codemove,@function |
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| 397 | /* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */ |
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| 398 | cmplw cr1,r3,r4 |
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| 399 | addi r0,r5,3 |
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| 400 | srwi. r0,r0,2 |
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| 401 | beq cr1,4f /* In place copy is not necessary */ |
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| 402 | beq 7f /* Protect against 0 count */ |
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| 403 | mtctr r0 |
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| 404 | bge cr1,2f |
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[6128a4a] | 405 | |
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[acc25ee] | 406 | la r8,-4(r4) |
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| 407 | la r7,-4(r3) |
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| 408 | 1: lwzu r0,4(r8) |
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[6128a4a] | 409 | stwu r0,4(r7) |
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[acc25ee] | 410 | bdnz 1b |
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| 411 | b 4f |
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| 412 | |
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| 413 | 2: slwi r0,r0,2 |
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| 414 | add r8,r4,r0 |
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| 415 | add r7,r3,r0 |
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| 416 | 3: lwzu r0,-4(r8) |
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| 417 | stwu r0,-4(r7) |
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| 418 | bdnz 3b |
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[6128a4a] | 419 | |
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[acc25ee] | 420 | /* Now flush the cache: note that we must start from a cache aligned |
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[6128a4a] | 421 | * address. Otherwise we might miss one cache line. |
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[acc25ee] | 422 | */ |
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| 423 | 4: cmpwi r6,0 |
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| 424 | add r5,r3,r5 |
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[6128a4a] | 425 | beq 7f /* Always flush prefetch queue in any case */ |
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[acc25ee] | 426 | subi r0,r6,1 |
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| 427 | andc r3,r3,r0 |
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| 428 | mr r4,r3 |
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[6128a4a] | 429 | 5: cmplw r4,r5 |
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[acc25ee] | 430 | dcbst 0,r4 |
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| 431 | add r4,r4,r6 |
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| 432 | blt 5b |
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| 433 | sync /* Wait for all dcbst to complete on bus */ |
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| 434 | mr r4,r3 |
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[6128a4a] | 435 | 6: cmplw r4,r5 |
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[acc25ee] | 436 | icbi 0,r4 |
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| 437 | add r4,r4,r6 |
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| 438 | blt 6b |
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| 439 | 7: sync /* Wait for all icbi to complete on bus */ |
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| 440 | isync |
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| 441 | blr |
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| 442 | .size codemove,.-codemove |
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| 443 | _size_codemove=.-codemove |
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| 444 | |
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| 445 | .section ".data" # .rodata |
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[732a3aee] | 446 | .align 4 |
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| 447 | #ifdef USE_PPCBUG |
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| 448 | /* A control 'packet' for the .NETCTRL PPCBug syscall to |
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| 449 | * reset a network interface. Let's hope they used the |
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| 450 | * first one for booting!! (CLUN/DLUN == 0/0) |
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| 451 | * Must be 4-byte aligned... |
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| 452 | */ |
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| 453 | nioc_reset_packet: |
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| 454 | .byte 0 /* Contoller LUN */ |
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| 455 | .byte 0 /* Device LUN */ |
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| 456 | .word 0 /* status return */ |
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| 457 | .long 5 /* Command (5=RESET) */ |
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| 458 | .long 0 /* Mem. Addr. for real data (unused for reset) */ |
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| 459 | .long 0 /* Number of bytes */ |
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| 460 | .long 0 /* Status/Control Flags (unused for reset) */ |
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| 461 | #endif |
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[6128a4a] | 462 | #ifdef TEST_PPCBUG_CALLS |
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| 463 | banner_start: |
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[acc25ee] | 464 | .ascii "This message was printed by PPCBug with MMU enabled" |
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[6128a4a] | 465 | banner_end: |
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[acc25ee] | 466 | #endif |
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