source: rtems/bsps/powerpc/include/rtems/powerpc/powerpc.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 20.8 KB
Line 
1/**
2 * @file rtems/powerpc/powerpc.h
3 */
4
5/*
6 *  This file contains definitions for the IBM/Motorola PowerPC
7 *  family members.
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
14 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
15 *  Surrey Satellite Technology Limited
16 *
17 *  To anyone who acknowledges that this file is provided "AS IS"
18 *  without any express or implied warranty:
19 *      permission to use, copy, modify, and distribute this file
20 *      for any purpose is hereby granted without fee, provided that
21 *      the above copyright notice and this notice appears in all
22 *      copies, and that the name of i-cubed limited not be used in
23 *      advertising or publicity pertaining to distribution of the
24 *      software without specific, written prior permission.
25 *      i-cubed limited makes no representations about the suitability
26 *      of this software for any purpose.
27 *
28 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
29 *
30 *  COPYRIGHT (c) 1989-1997.
31 *  On-Line Applications Research Corporation (OAR).
32 *
33 *  The license and distribution terms for this file may in
34 *  the file LICENSE in this distribution or at
35 *  http://www.rtems.org/license/LICENSE.
36 *
37 *
38 * Note:
39 *      This file is included by both C and assembler code ( -DASM )
40 */
41
42
43#ifndef _RTEMS_POWERPC_POWERPC_H
44#define _RTEMS_POWERPC_POWERPC_H
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
50
51/* Till S. 2008/07/10:
52 *
53 * Using the macros/definitions which depend on a preprocessor
54 * symbol defining the CPU flavor is discouraged.
55 * I recommend to not use definitions from this file and
56 * in particular - not to add more bits and pieces.
57 *
58 * Instead, try to use run-time detection (see e.g. cpuIdent.c/cpuIdent.h)
59 * of features etc.
60 */
61
62#include <rtems/score/powerpc.h>
63
64/*
65 * Unfortunately it is very inefficient to use run-time detection for the cache
66 * line size, so give the BSP the opportunity to define it here.
67 */
68#include <bspopts.h>
69
70/*
71 *  This file contains the information required to build
72 *  RTEMS for a particular member of the PowerPC family.  It does
73 *  this by setting variables to indicate which implementation
74 *  dependent features are present in a particular member
75 *  of the family.
76 *
77 *  The following architectural feature definitions are defaulted
78 *  unless specifically set by the model definition:
79 *
80 *    + PPC_INTERRUPT_MAX        - 16
81 *    + PPC_CACHE_ALIGNMENT
82 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
83 *    + PPC_HAS_EXCEPTION_PREFIX - 1
84 *    + PPC_USE_MULTIPLE         - 0
85 */
86
87/*
88 *  Define the low power mode models
89 *
90 *  Standard:   as defined for 603e
91 *  Nap Mode:   nap mode only (604)
92 *  XXX 403GB, 603, 603e, 604, 821
93 */
94
95#define PPC_LOW_POWER_MODE_NONE      0
96#define PPC_LOW_POWER_MODE_STANDARD  1
97
98/**
99 * @brief For boards with no cache set PPC_CACHE_ALIGNMENT to this value.
100 */
101#define PPC_NO_CACHE_ALIGNMENT 4
102
103/**
104 * @brief Used to define PPC_CACHE_ALIGN_POWER for boards with no cache (and
105 * PPC_NO_CACHE_ALIGNMENT defined).
106 */
107#define PPC_NO_CACHE_ALIGNMENT_POWER 2
108
109/*
110 *  Figure out all CPU Model Feature Flags based upon compiler
111 *  predefines.
112 */
113
114#if defined(ppc403)
115/*
116 *  IBM 403
117 *
118 *  Developed for 403GA.  Book checked for 403GB.
119 *
120 *  Does not have user mode.
121 */
122
123#define PPC_CACHE_ALIGNMENT     16
124#define PPC_HAS_RI              0
125#define PPC_HAS_RFCI            1
126#define PPC_USE_MULTIPLE        1
127#define PPC_I_CACHE             2048
128#define PPC_D_CACHE             1024
129
130#define PPC_HAS_EXCEPTION_PREFIX 0
131#define PPC_HAS_EVPR             1
132
133#elif defined (ppc405)
134
135#define PPC_CACHE_ALIGNMENT     32
136#define PPC_HAS_RI           0
137#define PPC_HAS_RFCI            1
138#define PPC_USE_MULTIPLE        1
139#define PPC_I_CACHE             16384
140#define PPC_D_CACHE             16384           /* except GP/CR */
141#define PPC_HAS_EXCEPTION_PREFIX 0
142#define PPC_HAS_EVPR             1
143
144#elif defined (ppc440)
145
146#define PPC_CACHE_ALIGNMENT         32
147#define PPC_HAS_RI                   0
148#define PPC_HAS_RFCI                 1
149#define PPC_USE_MULTIPLE             1
150#define PPC_I_CACHE              32768
151#define PPC_D_CACHE              32768
152#define PPC_HAS_EXCEPTION_PREFIX     0
153#define PPC_HAS_EVPR                 1
154
155#elif defined(mpc555)
156
157/* Copied from mpc505 */
158#define PPC_CACHE_ALIGNMENT     PPC_NO_CACHE_ALIGNMENT
159
160/* Added by querbach@realtime.bc.ca */
161#define PPC_LOW_POWER_MODE      PPC_LOW_POWER_MODE_STANDARD
162
163/* Based on comments by Sergei Organov <osv@Javad.RU> */
164#define PPC_I_CACHE             0
165#define PPC_D_CACHE             0
166
167#elif defined(mpc505) || defined(mpc509)
168/*
169 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
170 *  3.6.0 long after 4.0 was released.   This is just an attempt
171 *  to get the setting correct.
172 */
173
174#define CPU_MODEL_NAME  "PowerPC 505/509"
175
176#define PPC_CACHE_ALIGNMENT     PPC_NO_CACHE_ALIGNMENT
177#define PPC_I_CACHE             4096
178#define PPC_D_CACHE             0
179
180
181#elif defined(ppc601)
182
183/*
184 *  Submitted with original port -- book checked only.
185 */
186
187#define PPC_USE_MULTIPLE        1
188#define PPC_I_CACHE             0
189#define PPC_D_CACHE             32768
190
191#elif defined(ppc603)
192/*
193 *  Submitted with original port -- book checked only.
194 */
195
196#define PPC_I_CACHE             8192
197#define PPC_D_CACHE             8192
198
199#elif defined(ppc603e)
200
201/*
202 *  Submitted with original port.
203 *
204 *  Known to work on real hardware.
205 */
206
207#define PPC_I_CACHE             16384
208#define PPC_D_CACHE             16384
209
210#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
211
212#elif defined(mpc604)
213/*
214 *  Submitted with original port -- book checked only.
215 */
216
217#define PPC_I_CACHE             16384
218#define PPC_D_CACHE             16384
219
220#elif defined(mpc860)
221/*
222 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
223 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
224 */
225#define PPC_I_CACHE             4096
226#define PPC_D_CACHE             4096
227#define PPC_CACHE_ALIGNMENT     16
228#define PPC_INTERRUPT_MAX       71
229#define PPC_USE_MULTIPLE        1
230
231#define PPC_MSR_0               0x00009000
232#define PPC_MSR_1               0x00001000
233#define PPC_MSR_2               0x00001000
234#define PPC_MSR_3               0x00000000
235
236#elif defined(mpc821)
237/*
238 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
239 */
240#define PPC_I_CACHE             4096
241#define PPC_D_CACHE             4096
242#define PPC_CACHE_ALIGNMENT     16
243#define PPC_INTERRUPT_MAX       71
244
245#define PPC_MSR_0               0x00009000
246#define PPC_MSR_1               0x00001000
247#define PPC_MSR_2               0x00001000
248#define PPC_MSR_3               0x00000000
249
250#elif defined(mpc750)
251
252#define PPC_I_CACHE             16384
253#define PPC_D_CACHE             16384
254
255#elif defined(mpc7400)
256
257#define PPC_I_CACHE             32768
258#define PPC_D_CACHE             32768
259
260#elif defined(mpc7455)
261/*
262 *  Added by S.K. Feng <feng1@bnl.gov> 10/03
263 */
264
265#define PPC_CACHE_ALIGNMENT     32
266#define PPC_I_CACHE             32768
267#define PPC_D_CACHE             32768
268
269#elif defined(mpc8260)
270/*
271 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
272 */
273#define PPC_I_CACHE             16384
274#define PPC_D_CACHE             16384
275#define PPC_CACHE_ALIGNMENT     32
276#define PPC_INTERRUPT_MAX       125
277#define PPC_USE_MULTIPLE        1
278
279#elif defined(__ppc_generic)
280
281#else
282
283#error "Unsupported CPU Model"
284
285#endif
286
287/*
288 *  If the maximum number of exception sources has not been defined,
289 *  then default it to 16.
290 */
291
292#ifndef PPC_INTERRUPT_MAX
293#define PPC_INTERRUPT_MAX       16
294#endif
295
296#ifndef PPC_CACHE_ALIGNMENT
297#define PPC_CACHE_ALIGNMENT PPC_DEFAULT_CACHE_LINE_SIZE
298#endif
299
300#if (PPC_CACHE_ALIGNMENT == 16)
301#define PPC_CACHE_ALIGN_POWER 4
302#elif (PPC_CACHE_ALIGNMENT == 32)
303#define PPC_CACHE_ALIGN_POWER 5
304#elif (PPC_CACHE_ALIGNMENT == 64)
305#define PPC_CACHE_ALIGN_POWER 6
306#elif (PPC_CACHE_ALIGNMENT == PPC_NO_CACHE_ALIGNMENT)
307#define PPC_CACHE_ALIGN_POWER PPC_NO_CACHE_ALIGNMENT_POWER
308#else
309#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
310#endif
311
312/*
313 *  Unless otherwise specified, assume the model has an IP/EP bit to
314 *  set the exception address prefix.
315 */
316
317#ifndef PPC_HAS_EXCEPTION_PREFIX
318#define PPC_HAS_EXCEPTION_PREFIX 1
319#endif
320/*
321 *  Unless otherwise specified, assume the model has an RI bit to
322 *  identify non-recoverable interrupts
323 */
324
325#ifndef PPC_HAS_RI
326#define PPC_HAS_RI 1
327#endif
328
329/*
330 *  Unless otherwise specified, assume the model does NOT have
331 *  403 style EVPR register to set the exception address prefix.
332 */
333
334#ifndef PPC_HAS_EVPR
335#define PPC_HAS_EVPR 0
336#endif
337
338/*
339 *  If no low power mode model was specified, then assume there is none.
340 */
341
342#ifndef PPC_LOW_POWER_MODE
343#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
344#endif
345
346/*
347 *  Unless specified above, then assume the model does NOT have critical
348 *  interrupt support.
349 */
350
351#ifndef PPC_HAS_RFCI
352#define PPC_HAS_RFCI 0
353#endif
354
355/*
356 *  Unless specified above, do not use the load/store multiple instructions
357 *  in a context switch.
358 */
359
360#ifndef PPC_USE_MULTIPLE
361#define PPC_USE_MULTIPLE 0
362#endif
363
364/*
365 *  The following exceptions are not maskable, and are not
366 *  necessarily predictable, so cannot be offered to RTEMS:
367 *    Alignment exception - handled by the CPU module
368 *    Data exceptions.
369 *    Instruction exceptions.
370 */
371
372/*
373 *  Base Interrupt vectors supported on all models.
374 */
375#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
376#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
377#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
378#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
379#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
380#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
381#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
382#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
383#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
384#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
385#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
386#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
387#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
388#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
389#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
390
391#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
392
393#if defined(ppc403) || defined(ppc405) || defined(ppc440)
394
395#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
396#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
397#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
398#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
399#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
400#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
401
402#elif defined(mpc505) || defined(mpc509)
403#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
404#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
405#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
406#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
407#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
408
409#elif defined(mpc555)
410#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
411#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
412#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
413#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
414#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
415#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
416#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
417#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
418
419#elif defined(ppc601)
420#undef PPC_IRQ_TRACE
421#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
422#define PPC_IRQ_LAST     PPC_IRQ_TRACE
423
424#elif defined(ppc602)
425#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
426
427#elif defined(ppc603) || defined(ppc603e)
428#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
429#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
430#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
431#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
432#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
433#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT
434
435#elif defined(mpc604)
436#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
437#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
438#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT
439
440#elif defined(mpc860) || defined(mpc821)
441#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
442#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
443#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
444#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
445#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
446#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
447#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
448#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
449#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
450#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
451#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
452#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
453#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
454#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
455#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
456#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
457#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
458#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
459#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
460#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
461#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
462#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
463#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
464#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
465#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
466#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
467#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
468#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
469#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
470#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
471#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
472#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
473#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
474#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
475#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
476#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
477#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
478#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
479#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
480#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
481#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
482#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
483#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
484#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
485#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
486#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
487#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
488#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
489#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
490#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
491#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
492#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
493#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
494#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
495#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
496#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
497#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
498
499#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
500
501#elif defined(mpc8260)
502
503#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
504#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
505#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
506#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
507#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
508#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
509/* 0x1600 - 0x2F00 reserved */
510#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
511#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
512#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
513#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
514#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
515#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
516#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
517#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
518#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
519#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
520#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
521#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
522#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
523#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
524#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
525#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
526#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
527#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
528#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
529#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
530#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
531#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
532#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
533#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
534#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
535#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
536#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
537#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
538#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
539#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
540#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
541#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
542#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
543#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
544#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
545#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
546#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
547#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
548#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
549#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
550#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
551#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
552#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
553#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
554#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
555#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
556#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
557#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
558#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
559#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
560#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
561#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
562#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
563#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
564#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
565#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
566#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
567#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
568#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
569#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
570#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
571#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
572#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
573#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
574
575#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
576
577#endif
578
579
580/*
581 *  If the maximum number of exception sources is too low,
582 *  then fix it
583 */
584
585#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
586#undef PPC_INTERRUPT_MAX
587#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
588#endif
589
590/*
591 *  Machine Status Register (MSR) Constants Used by RTEMS
592 */
593
594#if PPC_HAS_RI
595#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
596#endif
597
598#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
599#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
600
601/*
602 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
603 *  IP for no apparent reason.
604 */
605#if (PPC_HAS_EXCEPTION_PREFIX)
606#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
607#else
608#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
609#endif
610
611#if (PPC_HAS_FPU)
612#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
613#else
614#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
615#endif
616
617#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
618#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
619#else
620#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
621#endif
622
623#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
624#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
625
626#if (PPC_HAS_RFCI)
627#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
628#else
629#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
630#endif
631
632#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
633
634#if defined(__powerpc64__)
635#define PPC_MINIMUM_STACK_FRAME_SIZE 32
636#else
637#define PPC_MINIMUM_STACK_FRAME_SIZE PPC_STACK_ALIGNMENT
638#endif
639
640#ifdef __cplusplus
641}
642#endif
643
644#endif /* _RTEMS_POWERPC_POWERPC_H */
Note: See TracBrowser for help on using the repository browser.