source: rtems/bsps/powerpc/include/rtems/powerpc/powerpc.h @ 07c5976

5
Last change on this file since 07c5976 was 07c5976, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 7, 2018 at 4:58:59 AM

bsps/powerpc: Hack to fix the build

The ppc405 define must be checked before the ppc403 define. The ppc405
define is provided by <bspopts.h>. The ppc403 define is provided by GCC
as a built-in define if no ppc* or mpc* define is set via the
command line (see GCC sources "gcc/config/rs6000/rtems.h").

Update #3425.

  • Property mode set to 100644
File size: 21.1 KB
Line 
1/**
2 * @file rtems/powerpc/powerpc.h
3 */
4
5/*
6 *  This file contains definitions for the IBM/Motorola PowerPC
7 *  family members.
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
14 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
15 *  Surrey Satellite Technology Limited
16 *
17 *  To anyone who acknowledges that this file is provided "AS IS"
18 *  without any express or implied warranty:
19 *      permission to use, copy, modify, and distribute this file
20 *      for any purpose is hereby granted without fee, provided that
21 *      the above copyright notice and this notice appears in all
22 *      copies, and that the name of i-cubed limited not be used in
23 *      advertising or publicity pertaining to distribution of the
24 *      software without specific, written prior permission.
25 *      i-cubed limited makes no representations about the suitability
26 *      of this software for any purpose.
27 *
28 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
29 *
30 *  COPYRIGHT (c) 1989-1997.
31 *  On-Line Applications Research Corporation (OAR).
32 *
33 *  The license and distribution terms for this file may in
34 *  the file LICENSE in this distribution or at
35 *  http://www.rtems.org/license/LICENSE.
36 *
37 *
38 * Note:
39 *      This file is included by both C and assembler code ( -DASM )
40 */
41
42
43#ifndef _RTEMS_POWERPC_POWERPC_H
44#define _RTEMS_POWERPC_POWERPC_H
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
50
51/* Till S. 2008/07/10:
52 *
53 * Using the macros/definitions which depend on a preprocessor
54 * symbol defining the CPU flavor is discouraged.
55 * I recommend to not use definitions from this file and
56 * in particular - not to add more bits and pieces.
57 *
58 * Instead, try to use run-time detection (see e.g. cpuIdent.c/cpuIdent.h)
59 * of features etc.
60 */
61
62#include <rtems/score/powerpc.h>
63
64/*
65 * Unfortunately it is very inefficient to use run-time detection for the cache
66 * line size, so give the BSP the opportunity to define it here.
67 */
68#include <bspopts.h>
69
70/*
71 *  This file contains the information required to build
72 *  RTEMS for a particular member of the PowerPC family.  It does
73 *  this by setting variables to indicate which implementation
74 *  dependent features are present in a particular member
75 *  of the family.
76 *
77 *  The following architectural feature definitions are defaulted
78 *  unless specifically set by the model definition:
79 *
80 *    + PPC_INTERRUPT_MAX        - 16
81 *    + PPC_CACHE_ALIGNMENT
82 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
83 *    + PPC_HAS_EXCEPTION_PREFIX - 1
84 *    + PPC_USE_MULTIPLE         - 0
85 */
86
87/*
88 *  Define the low power mode models
89 *
90 *  Standard:   as defined for 603e
91 *  Nap Mode:   nap mode only (604)
92 *  XXX 403GB, 603, 603e, 604, 821
93 */
94
95#define PPC_LOW_POWER_MODE_NONE      0
96#define PPC_LOW_POWER_MODE_STANDARD  1
97
98/**
99 * @brief For boards with no cache set PPC_CACHE_ALIGNMENT to this value.
100 */
101#define PPC_NO_CACHE_ALIGNMENT 4
102
103/**
104 * @brief Used to define PPC_CACHE_ALIGN_POWER for boards with no cache (and
105 * PPC_NO_CACHE_ALIGNMENT defined).
106 */
107#define PPC_NO_CACHE_ALIGNMENT_POWER 2
108
109/*
110 *  Figure out all CPU Model Feature Flags based upon compiler
111 *  predefines.
112 */
113
114/*
115 * FIXME: The ppc405 define must be checked before the ppc403 define.  The
116 * ppc405 define is provided by <bspopts.h>.  The ppc403 define is provided by
117 * GCC as a built-in define if no ppc* or mpc* define is set via the
118 * command line (see GCC sources "gcc/config/rs6000/rtems.h").
119 */
120#if defined(ppc405)
121
122#define PPC_CACHE_ALIGNMENT     32
123#define PPC_HAS_RI           0
124#define PPC_HAS_RFCI            1
125#define PPC_USE_MULTIPLE        1
126#define PPC_I_CACHE             16384
127#define PPC_D_CACHE             16384           /* except GP/CR */
128#define PPC_HAS_EXCEPTION_PREFIX 0
129#define PPC_HAS_EVPR             1
130
131#elif defined(ppc403)
132/*
133 *  IBM 403
134 *
135 *  Developed for 403GA.  Book checked for 403GB.
136 *
137 *  Does not have user mode.
138 */
139
140#define PPC_CACHE_ALIGNMENT     16
141#define PPC_HAS_RI              0
142#define PPC_HAS_RFCI            1
143#define PPC_USE_MULTIPLE        1
144#define PPC_I_CACHE             2048
145#define PPC_D_CACHE             1024
146
147#define PPC_HAS_EXCEPTION_PREFIX 0
148#define PPC_HAS_EVPR             1
149
150#elif defined (ppc440)
151
152#define PPC_CACHE_ALIGNMENT         32
153#define PPC_HAS_RI                   0
154#define PPC_HAS_RFCI                 1
155#define PPC_USE_MULTIPLE             1
156#define PPC_I_CACHE              32768
157#define PPC_D_CACHE              32768
158#define PPC_HAS_EXCEPTION_PREFIX     0
159#define PPC_HAS_EVPR                 1
160
161#elif defined(mpc555)
162
163/* Copied from mpc505 */
164#define PPC_CACHE_ALIGNMENT     PPC_NO_CACHE_ALIGNMENT
165
166/* Added by querbach@realtime.bc.ca */
167#define PPC_LOW_POWER_MODE      PPC_LOW_POWER_MODE_STANDARD
168
169/* Based on comments by Sergei Organov <osv@Javad.RU> */
170#define PPC_I_CACHE             0
171#define PPC_D_CACHE             0
172
173#elif defined(mpc505) || defined(mpc509)
174/*
175 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
176 *  3.6.0 long after 4.0 was released.   This is just an attempt
177 *  to get the setting correct.
178 */
179
180#define CPU_MODEL_NAME  "PowerPC 505/509"
181
182#define PPC_CACHE_ALIGNMENT     PPC_NO_CACHE_ALIGNMENT
183#define PPC_I_CACHE             4096
184#define PPC_D_CACHE             0
185
186
187#elif defined(ppc601)
188
189/*
190 *  Submitted with original port -- book checked only.
191 */
192
193#define PPC_USE_MULTIPLE        1
194#define PPC_I_CACHE             0
195#define PPC_D_CACHE             32768
196
197#elif defined(ppc603)
198/*
199 *  Submitted with original port -- book checked only.
200 */
201
202#define PPC_I_CACHE             8192
203#define PPC_D_CACHE             8192
204
205#elif defined(ppc603e)
206
207/*
208 *  Submitted with original port.
209 *
210 *  Known to work on real hardware.
211 */
212
213#define PPC_I_CACHE             16384
214#define PPC_D_CACHE             16384
215
216#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
217
218#elif defined(mpc604)
219/*
220 *  Submitted with original port -- book checked only.
221 */
222
223#define PPC_I_CACHE             16384
224#define PPC_D_CACHE             16384
225
226#elif defined(mpc860)
227/*
228 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
229 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
230 */
231#define PPC_I_CACHE             4096
232#define PPC_D_CACHE             4096
233#define PPC_CACHE_ALIGNMENT     16
234#define PPC_INTERRUPT_MAX       71
235#define PPC_USE_MULTIPLE        1
236
237#define PPC_MSR_0               0x00009000
238#define PPC_MSR_1               0x00001000
239#define PPC_MSR_2               0x00001000
240#define PPC_MSR_3               0x00000000
241
242#elif defined(mpc821)
243/*
244 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
245 */
246#define PPC_I_CACHE             4096
247#define PPC_D_CACHE             4096
248#define PPC_CACHE_ALIGNMENT     16
249#define PPC_INTERRUPT_MAX       71
250
251#define PPC_MSR_0               0x00009000
252#define PPC_MSR_1               0x00001000
253#define PPC_MSR_2               0x00001000
254#define PPC_MSR_3               0x00000000
255
256#elif defined(mpc750)
257
258#define PPC_I_CACHE             16384
259#define PPC_D_CACHE             16384
260
261#elif defined(mpc7400)
262
263#define PPC_I_CACHE             32768
264#define PPC_D_CACHE             32768
265
266#elif defined(mpc7455)
267/*
268 *  Added by S.K. Feng <feng1@bnl.gov> 10/03
269 */
270
271#define PPC_CACHE_ALIGNMENT     32
272#define PPC_I_CACHE             32768
273#define PPC_D_CACHE             32768
274
275#elif defined(mpc8260)
276/*
277 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
278 */
279#define PPC_I_CACHE             16384
280#define PPC_D_CACHE             16384
281#define PPC_CACHE_ALIGNMENT     32
282#define PPC_INTERRUPT_MAX       125
283#define PPC_USE_MULTIPLE        1
284
285#elif defined(__ppc_generic)
286
287#else
288
289#error "Unsupported CPU Model"
290
291#endif
292
293/*
294 *  If the maximum number of exception sources has not been defined,
295 *  then default it to 16.
296 */
297
298#ifndef PPC_INTERRUPT_MAX
299#define PPC_INTERRUPT_MAX       16
300#endif
301
302#ifndef PPC_CACHE_ALIGNMENT
303#define PPC_CACHE_ALIGNMENT PPC_DEFAULT_CACHE_LINE_SIZE
304#endif
305
306#if (PPC_CACHE_ALIGNMENT == 16)
307#define PPC_CACHE_ALIGN_POWER 4
308#elif (PPC_CACHE_ALIGNMENT == 32)
309#define PPC_CACHE_ALIGN_POWER 5
310#elif (PPC_CACHE_ALIGNMENT == 64)
311#define PPC_CACHE_ALIGN_POWER 6
312#elif (PPC_CACHE_ALIGNMENT == PPC_NO_CACHE_ALIGNMENT)
313#define PPC_CACHE_ALIGN_POWER PPC_NO_CACHE_ALIGNMENT_POWER
314#else
315#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
316#endif
317
318/*
319 *  Unless otherwise specified, assume the model has an IP/EP bit to
320 *  set the exception address prefix.
321 */
322
323#ifndef PPC_HAS_EXCEPTION_PREFIX
324#define PPC_HAS_EXCEPTION_PREFIX 1
325#endif
326/*
327 *  Unless otherwise specified, assume the model has an RI bit to
328 *  identify non-recoverable interrupts
329 */
330
331#ifndef PPC_HAS_RI
332#define PPC_HAS_RI 1
333#endif
334
335/*
336 *  Unless otherwise specified, assume the model does NOT have
337 *  403 style EVPR register to set the exception address prefix.
338 */
339
340#ifndef PPC_HAS_EVPR
341#define PPC_HAS_EVPR 0
342#endif
343
344/*
345 *  If no low power mode model was specified, then assume there is none.
346 */
347
348#ifndef PPC_LOW_POWER_MODE
349#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
350#endif
351
352/*
353 *  Unless specified above, then assume the model does NOT have critical
354 *  interrupt support.
355 */
356
357#ifndef PPC_HAS_RFCI
358#define PPC_HAS_RFCI 0
359#endif
360
361/*
362 *  Unless specified above, do not use the load/store multiple instructions
363 *  in a context switch.
364 */
365
366#ifndef PPC_USE_MULTIPLE
367#define PPC_USE_MULTIPLE 0
368#endif
369
370/*
371 *  The following exceptions are not maskable, and are not
372 *  necessarily predictable, so cannot be offered to RTEMS:
373 *    Alignment exception - handled by the CPU module
374 *    Data exceptions.
375 *    Instruction exceptions.
376 */
377
378/*
379 *  Base Interrupt vectors supported on all models.
380 */
381#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
382#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
383#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
384#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
385#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
386#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
387#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
388#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
389#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
390#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
391#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
392#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
393#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
394#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
395#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
396
397#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
398
399#if defined(ppc403) || defined(ppc405) || defined(ppc440)
400
401#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
402#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
403#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
404#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
405#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
406#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
407
408#elif defined(mpc505) || defined(mpc509)
409#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
410#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
411#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
412#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
413#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
414
415#elif defined(mpc555)
416#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
417#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
418#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
419#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
420#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
421#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
422#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
423#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
424
425#elif defined(ppc601)
426#undef PPC_IRQ_TRACE
427#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
428#define PPC_IRQ_LAST     PPC_IRQ_TRACE
429
430#elif defined(ppc602)
431#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
432
433#elif defined(ppc603) || defined(ppc603e)
434#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
435#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
436#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
437#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
438#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
439#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT
440
441#elif defined(mpc604)
442#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
443#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
444#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT
445
446#elif defined(mpc860) || defined(mpc821)
447#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
448#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
449#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
450#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
451#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
452#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
453#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
454#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
455#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
456#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
457#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
458#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
459#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
460#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
461#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
462#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
463#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
464#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
465#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
466#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
467#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
468#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
469#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
470#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
471#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
472#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
473#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
474#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
475#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
476#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
477#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
478#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
479#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
480#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
481#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
482#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
483#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
484#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
485#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
486#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
487#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
488#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
489#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
490#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
491#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
492#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
493#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
494#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
495#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
496#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
497#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
498#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
499#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
500#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
501#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
502#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
503#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
504
505#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
506
507#elif defined(mpc8260)
508
509#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
510#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
511#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
512#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
513#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
514#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
515/* 0x1600 - 0x2F00 reserved */
516#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
517#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
518#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
519#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
520#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
521#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
522#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
523#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
524#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
525#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
526#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
527#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
528#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
529#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
530#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
531#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
532#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
533#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
534#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
535#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
536#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
537#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
538#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
539#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
540#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
541#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
542#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
543#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
544#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
545#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
546#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
547#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
548#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
549#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
550#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
551#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
552#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
553#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
554#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
555#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
556#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
557#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
558#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
559#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
560#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
561#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
562#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
563#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
564#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
565#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
566#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
567#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
568#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
569#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
570#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
571#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
572#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
573#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
574#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
575#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
576#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
577#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
578#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
579#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
580
581#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
582
583#endif
584
585
586/*
587 *  If the maximum number of exception sources is too low,
588 *  then fix it
589 */
590
591#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
592#undef PPC_INTERRUPT_MAX
593#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
594#endif
595
596/*
597 *  Machine Status Register (MSR) Constants Used by RTEMS
598 */
599
600#if PPC_HAS_RI
601#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
602#endif
603
604#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
605#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
606
607/*
608 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
609 *  IP for no apparent reason.
610 */
611#if (PPC_HAS_EXCEPTION_PREFIX)
612#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
613#else
614#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
615#endif
616
617#if (PPC_HAS_FPU)
618#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
619#else
620#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
621#endif
622
623#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
624#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
625#else
626#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
627#endif
628
629#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
630#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
631
632#if (PPC_HAS_RFCI)
633#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
634#else
635#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
636#endif
637
638#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
639
640#if defined(__powerpc64__)
641#define PPC_MINIMUM_STACK_FRAME_SIZE 32
642#else
643#define PPC_MINIMUM_STACK_FRAME_SIZE PPC_STACK_ALIGNMENT
644#endif
645
646#ifdef __cplusplus
647}
648#endif
649
650#endif /* _RTEMS_POWERPC_POWERPC_H */
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