[3c6fe2e] | 1 | |
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| 2 | /* SDRAM DCRs */ |
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| 3 | enum { |
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| 4 | SDRAM0_BESR0 = 0, |
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| 5 | SDRAM0_BESR1 = 8, |
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| 6 | SDRAM0_BEAR = 0x10, |
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| 7 | SDRAM0_CFG = 0x20, |
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| 8 | SDRAM0_STATUS = 0x24, |
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| 9 | SDRAM0_RTR = 0x30, |
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| 10 | SDRAM0_PMIT = 0x34, |
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| 11 | SDRAM0_TR = 0x80 |
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| 12 | }; |
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| 13 | |
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| 14 | |
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| 15 | /* EBC DCRs */ |
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| 16 | enum { |
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| 17 | EBC0_B0CR = 0, |
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| 18 | EBC0_B1CR = 1, |
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| 19 | EBC0_B2CR = 2, |
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| 20 | EBC0_B3CR = 3, |
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| 21 | EBC0_B4CR = 4, |
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| 22 | EBC0_B5CR = 5, |
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| 23 | EBC0_B6CR = 6, |
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| 24 | EBC0_B7CR = 7, |
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| 25 | EBC0_B0AP = 0x10, |
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| 26 | EBC0_B1AP = 0x11, |
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| 27 | EBC0_B2AP = 0x12, |
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| 28 | EBC0_B3AP = 0x13, |
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| 29 | EBC0_B4AP = 0x14, |
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| 30 | EBC0_B5AP = 0x15, |
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| 31 | EBC0_B6AP = 0x16, |
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| 32 | EBC0_B7AP = 0x17, |
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| 33 | EBC0_BEAR = 0x20, |
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| 34 | EBC0_BESR0 = 0x21, |
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| 35 | EBC0_BESR1 = 0x22, |
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| 36 | EBC0_CFG = 0x23 |
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| 37 | }; |
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| 38 | |
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[502609c8] | 39 | /* MAL DCRs, have to be #defines */ |
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| 40 | #define MAL0_CFG 0x180 |
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| 41 | #define MAL0_ESR 0x181 |
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| 42 | #define MAL0_IER 0x182 |
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| 43 | #define MAL0_TXCASR 0x184 |
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| 44 | #define MAL0_TXCARR 0x185 |
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| 45 | #define MAL0_TXEOBISR 0x186 |
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| 46 | #define MAL0_TXDEIR 0x187 |
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| 47 | #define MAL0_RXCASR 0x190 |
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| 48 | #define MAL0_RXCARR 0x191 |
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| 49 | #define MAL0_RXEOBISR 0x192 |
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| 50 | #define MAL0_RXDEIR 0x193 |
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| 51 | #define MAL0_TXCTP0R 0x1A0 |
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| 52 | #define MAL0_TXCTP1R 0x1A1 |
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| 53 | #define MAL0_RXCTP0R 0x1C0 |
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| 54 | #define MAL0_RXCTP1R 0x1C1 |
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| 55 | #define MAL0_RCBS0 0x1E0 |
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| 56 | #define MAL0_RCBS1 0x1E1 |
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| 57 | |
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[3c6fe2e] | 58 | /* Memory-mapped registers */ |
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| 59 | |
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| 60 | typedef struct EthernetRegisters_GP { |
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| 61 | uint32_t mode0; |
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| 62 | uint32_t mode1; |
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| 63 | uint32_t xmtMode0; |
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| 64 | uint32_t xmtMode1; |
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| 65 | uint32_t rcvMode; |
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| 66 | uint32_t intStatus; |
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| 67 | uint32_t intEnable; |
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| 68 | uint32_t addrHi; |
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| 69 | uint32_t addrLo; |
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| 70 | uint32_t VLANTPID; |
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| 71 | uint32_t VLANTCI; |
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| 72 | uint32_t pauseTimer; |
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[502609c8] | 73 | uint32_t g_indivHash[4]; /* EX non-IP multicast addr/mask */ |
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| 74 | uint32_t g_groupHash[4]; |
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[3c6fe2e] | 75 | uint32_t lastSrcLo; |
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| 76 | uint32_t lastSrcHi; |
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| 77 | uint32_t IPGap; |
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| 78 | uint32_t STAcontrol; |
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| 79 | uint32_t xmtReqThreshold; |
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[502609c8] | 80 | uint32_t rcvWatermarks; |
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[3c6fe2e] | 81 | uint32_t bytesXmtd; |
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| 82 | uint32_t bytesRcvd; |
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[502609c8] | 83 | uint32_t e_unused2; |
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| 84 | uint32_t e_revID; |
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| 85 | uint32_t e_unused3[2]; |
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| 86 | uint32_t e_indivHash[8]; |
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| 87 | uint32_t e_groupHash[8]; |
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| 88 | uint32_t e_xmtPause; |
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[3c6fe2e] | 89 | } EthernetRegisters_GP; |
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| 90 | |
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[502609c8] | 91 | typedef struct EthernetRegisters_GP EthernetRegisters_EX; |
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| 92 | |
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[3c6fe2e] | 93 | enum { EMACAddress = 0xEF600800 }; |
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[502609c8] | 94 | enum { EMAC0GPAddress = 0xEF600800 }; |
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[3c6fe2e] | 95 | |
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| 96 | enum { |
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| 97 | // Mode 0 bits |
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| 98 | kEMACRxIdle = 0x80000000, |
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| 99 | kEMACTxIdle = 0x40000000, |
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| 100 | kEMACSoftRst = 0x20000000, |
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| 101 | kEMACTxEnable = 0x10000000, |
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| 102 | kEMACRxEnable = 0x08000000, |
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[359e537] | 103 | |
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[3c6fe2e] | 104 | // Mode 1 bits |
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| 105 | kEMACFullDuplex = 0x80000000, |
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[502609c8] | 106 | kEMACDoFlowControl = 0x10000000, |
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[3c6fe2e] | 107 | kEMACIgnoreSQE = 0x01000000, |
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| 108 | kEMAC100MBbps = 0x00400000, |
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| 109 | kEMAC4KRxFIFO = 0x00300000, |
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| 110 | kEMAC2KTxFIFO = 0x00080000, |
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| 111 | kEMACTx0Multi = 0x00008000, |
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| 112 | kEMACTxDependent= 0x00014000, |
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[502609c8] | 113 | kEMAC100Mbps = 0x00400000, |
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| 114 | kgEMAC4KRxFIFO = 0x00300000, |
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| 115 | kgEMAC2KTxFIFO = 0x00080000, |
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| 116 | kgEMACTx0Multi = 0x00008000, |
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| 117 | kgEMACTxDependent= 0x00014000, |
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| 118 | |
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[359e537] | 119 | |
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[3c6fe2e] | 120 | // Tx mode bits |
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| 121 | kEMACNewPacket0 = 0x80000000, |
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| 122 | kEMACNewPacket1 = 0x40000000, |
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[359e537] | 123 | |
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[3c6fe2e] | 124 | // Receive mode bits |
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| 125 | kEMACStripPadding = 0x80000000, |
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| 126 | kEMACStripFCS = 0x40000000, |
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| 127 | kEMACRcvRunts = 0x20000000, |
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| 128 | kEMACRcvFCSErrs = 0x10000000, |
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| 129 | kEMACRcvOversize = 0x08000000, |
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| 130 | kEMACPromiscRcv = 0x01000000, |
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| 131 | kEMACPromMultRcv = 0x00800000, |
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| 132 | kEMACIndivRcv = 0x00400000, |
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| 133 | kEMACHashRcv = 0x00200000, |
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| 134 | kEMACBrcastRcv = 0x00100000, |
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| 135 | kEMACMultcastRcv = 0x00080000, |
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[502609c8] | 136 | keEMACNonIPMultcast = 0x00040000, |
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| 137 | keEMACRxFIFOAFMax = 7, |
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| 138 | |
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| 139 | // EMAC_STACR bits |
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| 140 | kgSTAComplete = 0x8000, |
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| 141 | kSTAErr = 0x4000, |
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| 142 | |
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| 143 | // Interrupt status bits |
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| 144 | kEMACIOverrun = 0x02000000, |
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| 145 | kEMACIPause = 0x01000000, |
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| 146 | kEMACIBadPkt = 0x00800000, |
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| 147 | kEMACIRuntPkt = 0x00400000, |
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| 148 | kEMACIShortEvt= 0x00200000, |
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| 149 | kEMACIAlignErr= 0x00100000, |
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| 150 | kEMACIBadFCS = 0x00080000, |
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| 151 | kEMACIOverSize= 0x00040000, |
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| 152 | kEMACILLCRange= 0x00020000, |
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| 153 | kEMACISQEErr = 0x00000080, |
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| 154 | kEMACITxErr = 0x00000040, |
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[359e537] | 155 | |
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[3c6fe2e] | 156 | // Buffer descriptor control bits |
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| 157 | kMALTxReady = 0x8000, |
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| 158 | kMALRxEmpty = 0x8000, |
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| 159 | kMALWrap = 0x4000, |
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| 160 | kMALContinuous = 0x2000, |
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| 161 | kMALLast = 0x1000, |
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| 162 | kMALRxFirst = 0x0800, |
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| 163 | kMALInterrupt = 0x0400, |
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[359e537] | 164 | |
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[502609c8] | 165 | kMALReset = 0x80000000, |
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| 166 | kMALLowPriority = 0, |
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| 167 | kMALMedLowPriority = 0x00400000, |
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| 168 | kMALMedHiPriority = 0x00800000, |
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| 169 | kMALHighPriority = 0x00C00000, |
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| 170 | kMALLatency8 = 0x00040000, |
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| 171 | kMALLockErr = 0x8000, |
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| 172 | kMALCanBurst = 0x4000, |
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| 173 | kMALLocksOPB = 0x80, |
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| 174 | kMALLocksErrs = 0x2, |
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| 175 | |
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| 176 | // MAL channel masks |
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| 177 | kMALChannel0 = 0x80000000, |
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| 178 | kMALChannel1 = 0x40000000, |
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| 179 | |
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[3c6fe2e] | 180 | // EMAC Tx descriptor bits sent |
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| 181 | kEMACGenFCS = 0x200, |
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| 182 | kEMACGenPad = 0x100, |
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| 183 | kEMACInsSrcAddr = 0x080, |
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| 184 | kEMACRepSrcAddr = 0x040, |
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| 185 | kEMACInsVLAN = 0x020, |
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| 186 | kEMACRepVLAN = 0x010, |
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[359e537] | 187 | |
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[3c6fe2e] | 188 | // EMAC TX descriptor bits returned |
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| 189 | kEMACErrMask = 0x3FF, |
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| 190 | kEMACFCSWrong = 0x200, |
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| 191 | kEMACBadPrev = 0x100, |
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| 192 | kEMACLostCarrier = 0x080, |
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| 193 | kEMACDeferred = 0x040, |
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| 194 | kEMACCollFail = 0x020, |
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| 195 | kEMACLateColl = 0x010, |
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| 196 | kEMACMultColl = 0x008, |
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| 197 | kEMACOneColl = 0x004, |
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| 198 | kEMACUnderrun = 0x002, |
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| 199 | kEMACSQEFail = 0x001, |
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[359e537] | 200 | |
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[3c6fe2e] | 201 | // EMAC Rx descriptor bits returned |
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| 202 | kEMACOverrun = 0x200, |
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| 203 | kEMACPausePkt = 0x100, |
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| 204 | kEMACBadPkt = 0x080, |
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| 205 | kEMACRuntPkt = 0x040, |
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| 206 | kEMACShortEvt = 0x020, |
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| 207 | kEMACAlignErr = 0x010, |
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| 208 | kEMACBadFCS = 0x008, |
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| 209 | kEMACPktLong = 0x004, |
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| 210 | kEMACPktOOR = 0x002, |
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| 211 | kEMACPktIRL = 0x001 |
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| 212 | }; |
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| 213 | |
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| 214 | |
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