1 | /* |
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2 | |
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3 | Constants for manipulating system registers of PPC 405EX in C |
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4 | |
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5 | Michael Hamel ADInstruments May 2008 |
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6 | |
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7 | */ |
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8 | |
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9 | #include <libcpu/powerpc-utility.h> |
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10 | /* Indirect access to Clocking/Power-On registers */ |
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11 | #define CPR0_DCR_BASE 0x0C |
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12 | #define cprcfga (CPR0_DCR_BASE+0x0) |
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13 | #define cprcfgd (CPR0_DCR_BASE+0x1) |
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14 | |
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15 | #define mtcpr(reg, d) \ |
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16 | do { \ |
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17 | PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ |
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18 | PPC_SET_DEVICE_CONTROL_REGISTER(cprcfgd,d); \ |
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19 | } while (0) |
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20 | |
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21 | #define mfcpr(reg, d) \ |
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22 | do { \ |
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23 | PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ |
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24 | d = PPC_DEVICE_CONTROL_REGISTER(cprcfgd); \ |
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25 | } while (0) |
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26 | |
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27 | |
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28 | /* Indirect access to System registers */ |
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29 | #define SDR_DCR_BASE 0x0E |
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30 | #define sdrcfga (SDR_DCR_BASE+0x0) |
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31 | #define sdrcfgd (SDR_DCR_BASE+0x1) |
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32 | |
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33 | #define mtsdr(reg, d) \ |
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34 | do { \ |
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35 | PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ |
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36 | PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfgd,d); \ |
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37 | } while (0) |
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38 | |
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39 | #define mfsdr(reg, d) \ |
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40 | do { \ |
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41 | PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ |
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42 | d = PPC_DEVICE_CONTROL_REGISTER(sdrcfgd); \ |
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43 | } while (0) |
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44 | |
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45 | /* Indirect access to EBC registers */ |
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46 | #define EBC_DCR_BASE 0x12 |
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47 | #define ebccfga (EBC_DCR_BASE+0x0) |
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48 | #define ebccfgd (EBC_DCR_BASE+0x1) |
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49 | |
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50 | #define mtebc(reg, d) \ |
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51 | do { \ |
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52 | PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ |
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53 | PPC_SET_DEVICE_CONTROL_REGISTER(ebccfgd,d); \ |
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54 | } while (0) |
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55 | |
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56 | #define mfebc(reg, d) \ |
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57 | do { \ |
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58 | PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ |
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59 | d = PPC_DEVICE_CONTROL_REGISTER(ebccfgd); \ |
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60 | } while (0) |
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61 | |
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62 | /* EBC DCRs */ |
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63 | enum { |
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64 | /* |
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65 | EBC0_B0CR = 0, |
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66 | EBC0_B1CR = 1, |
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67 | EBC0_B2CR = 2, |
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68 | EBC0_B3CR = 3, |
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69 | EBC0_B0AP = 0x10, |
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70 | EBC0_B1AP = 0x11, |
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71 | EBC0_B2AP = 0x12, |
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72 | EBC0_B3AP = 0x13, |
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73 | EBC0_BEAR = 0x20, |
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74 | EBC0_BESR = 0x21, |
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75 | EBC0_CFG = 0x23, |
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76 | */ |
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77 | EBC0_CID = 0x24 |
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78 | }; |
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79 | |
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80 | enum { |
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81 | SDR0_PINSTP = 0x40, |
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82 | SDR0_UART0 = 0x120, |
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83 | SDR0_UART1 = 0x121, |
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84 | SDR0_C405 = 0x180, |
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85 | SDR0_SRST0 = 0x200, |
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86 | SDR0_MALTBL = 0x280, |
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87 | SDR0_MALRBL = 0x2A0, |
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88 | SDR0_MALTBS = 0x2C0, |
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89 | SDR0_MALRBS = 0x2E0, |
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90 | SDR0_PFC2 = 0x4102, |
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91 | SDR0_MFR = 0x4300, |
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92 | SDR0_EMAC0RXST = 0x4301, |
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93 | SDR0_HSF = 0x4400 |
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94 | }; |
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95 | |
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96 | enum { |
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97 | CPR0_CLKUPD = 0x20, |
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98 | CPR0_PLLC = 0x40, |
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99 | CPR0_PLLD = 0x60, |
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100 | CPR0_CPUD = 0x80, |
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101 | CPR0_PLBD = 0xA0, |
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102 | CPR0_OPBD = 0xC0, |
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103 | CPR0_PERD = 0xE0, |
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104 | CPR0_AHBD = 0x100, |
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105 | CPR0_ICFG = 0x140 |
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106 | }; |
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107 | |
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108 | /* Memory-mapped registers */ |
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109 | |
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110 | |
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111 | /*======================= Ethernet =================== */ |
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112 | |
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113 | enum { |
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114 | EMAC0EXAddress = 0xEF600900, |
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115 | EMAC1EXAddress = 0xEF600A00, |
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116 | |
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117 | /* 405EX-specific bits in EMAC_MR1 */ |
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118 | keEMAC1000Mbps = 0x00800000, |
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119 | keEMAC16KRxFIFO = 0x00280000, |
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120 | keEMAC8KRxFIFO = 0x00200000, |
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121 | keEMAC4KRxFIFO = 0x00180000, |
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122 | keEMAC2KRxFIFO = 0x00100000, |
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123 | keEMAC1KRxFIFO = 0x00080000, |
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124 | keEMAC16KTxFIFO = 0x00050000, |
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125 | keEMAC8KTxFIFO = 0x00040000, |
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126 | keEMAC4KTxFIFO = 0x00030000, |
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127 | keEMAC2KTxFIFO = 0x00020000, |
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128 | keEMAC1KTxFIFO = 0x00010000, |
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129 | keEMACJumbo = 0x00000800, |
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130 | keEMACIPHYAddr4 = 0x180, |
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131 | keEMACOPB50MHz = 0x00, |
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132 | keEMACOPB66MHz = 0x08, |
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133 | keEMACOPB83MHz = 0x10, |
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134 | keEMACOPB100MHz = 0x18, |
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135 | keEMACOPBGt100 = 0x20, |
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136 | |
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137 | /* 405EX-specific bits in MAL0_CFG */ |
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138 | keMALRdMaxBurst4 = 0, |
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139 | keMALRdMaxBurst8 = 0x00100000, |
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140 | keMALRdMaxBurst16 = 0x00200000, |
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141 | keMALRdMaxBurst32 = 0x00300000, |
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142 | |
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143 | keMALWrLowPriority = 0, |
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144 | keMALWrMedLowPriority = 0x00040000, |
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145 | keMALWrMedHiPriority = 0x00080000, |
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146 | keMALWrHighPriority = 0x000C0000, |
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147 | |
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148 | keMALWrMaxBurst4 = 0, |
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149 | keMALWrMaxBurst8 = 0x00010000, |
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150 | keMALWrMaxBurst16 = 0x00020000, |
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151 | keMALWrMaxBurst32 = 0x00030000, |
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152 | |
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153 | /* 405EX-specific STA bits */ |
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154 | keSTARun = 0x8000, |
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155 | keSTADirectRd = 0x1000, |
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156 | keSTADirectWr = 0x0800, |
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157 | keSTAIndirAddr = 0x2000, |
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158 | keSTAIndirRd = 0x3000, |
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159 | keSTAIndirWr = 0x2800 |
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160 | }; |
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161 | |
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162 | typedef struct GPIORegisters { |
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163 | uint32_t OR; |
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164 | uint32_t GPIO_TCR; /* Note that TCR is defined as a DCR name */ |
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165 | uint32_t OSRL; |
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166 | uint32_t OSRH; |
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167 | uint32_t TSRL; |
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168 | uint32_t TSRH; |
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169 | uint32_t ODR; |
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170 | uint32_t IR; |
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171 | uint32_t RR1; |
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172 | uint32_t RR2; |
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173 | uint32_t RR3; |
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174 | uint32_t unknown; |
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175 | uint32_t ISR1L; |
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176 | uint32_t ISR1H; |
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177 | uint32_t ISR2L; |
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178 | uint32_t ISR2H; |
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179 | uint32_t ISR3L; |
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180 | uint32_t ISR3H; |
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181 | } GPIORegisters; |
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182 | |
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183 | enum { GPIOAddress = 0xEF600800 }; |
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184 | |
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185 | typedef struct RGMIIRegisters { |
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186 | uint32_t FER; |
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187 | uint32_t SSR; |
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188 | } RGMIIRegisters; |
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189 | |
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190 | enum { RGMIIAddress = 0xEF600B00 }; |
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191 | |
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