source: rtems/bsps/powerpc/include/ppc4xx/ppc405ex.h @ 495f836

Last change on this file since 495f836 was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 4.1 KB
RevLine 
[3c6fe2e]1/*
2
3Constants for manipulating system registers of PPC 405EX in C
4
[359e537]5Michael Hamel ADInstruments May 2008
[3c6fe2e]6
7*/
8
9#include <libcpu/powerpc-utility.h>
10/* Indirect access to Clocking/Power-On registers */
11#define CPR0_DCR_BASE   0x0C
12#define cprcfga         (CPR0_DCR_BASE+0x0)
13#define cprcfgd         (CPR0_DCR_BASE+0x1)
14
15#define mtcpr(reg, d)                                   \
16  do {                                                  \
17    PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg);       \
18    PPC_SET_DEVICE_CONTROL_REGISTER(cprcfgd,d);         \
19  } while (0)
20
21#define mfcpr(reg, d)                                   \
22  do {                                                  \
23    PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg);       \
24    d = PPC_DEVICE_CONTROL_REGISTER(cprcfgd);           \
25  } while (0)
26
27
28/* Indirect access to System registers */
29#define SDR_DCR_BASE    0x0E
30#define sdrcfga         (SDR_DCR_BASE+0x0)
31#define sdrcfgd         (SDR_DCR_BASE+0x1)
32
33#define mtsdr(reg, d)                                   \
34  do {                                                  \
35    PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg);       \
36    PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfgd,d);         \
37  } while (0)
38
39#define mfsdr(reg, d)                                   \
40    do {                                                \
41      PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg);     \
42      d = PPC_DEVICE_CONTROL_REGISTER(sdrcfgd);         \
43    } while (0)
44
45/* Indirect access to EBC registers */
46#define EBC_DCR_BASE    0x12
47#define ebccfga         (EBC_DCR_BASE+0x0)
48#define ebccfgd         (EBC_DCR_BASE+0x1)
49
50#define mtebc(reg, d)                                   \
51  do {                                                  \
52    PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg);       \
53    PPC_SET_DEVICE_CONTROL_REGISTER(ebccfgd,d);         \
54  } while (0)
55
56#define mfebc(reg, d)                                   \
57  do {                                                  \
58    PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg);       \
59    d = PPC_DEVICE_CONTROL_REGISTER(ebccfgd);           \
60  } while (0)
61
62/* EBC DCRs */
63enum {
64        /*
65        EBC0_B0CR       =       0,
66        EBC0_B1CR       =       1,
67        EBC0_B2CR       =       2,
68        EBC0_B3CR       =       3,
69        EBC0_B0AP       =       0x10,
70        EBC0_B1AP       =       0x11,
71        EBC0_B2AP       =       0x12,
72        EBC0_B3AP       =       0x13,
73        EBC0_BEAR       =       0x20,
74        EBC0_BESR       =       0x21,
75        EBC0_CFG        =       0x23,
76        */
77        EBC0_CID        =       0x24
78};
79
80enum {
[502609c8]81        SDR0_PINSTP = 0x40,
[3c6fe2e]82        SDR0_UART0      = 0x120,
83        SDR0_UART1  = 0x121,
84        SDR0_C405       = 0x180,
[502609c8]85        SDR0_SRST0  = 0x200,
[3c6fe2e]86        SDR0_MALTBL = 0x280,
87        SDR0_MALRBL = 0x2A0,
88        SDR0_MALTBS = 0x2C0,
[502609c8]89        SDR0_MALRBS = 0x2E0,
90        SDR0_PFC2   = 0x4102,
91        SDR0_MFR    = 0x4300,
92        SDR0_EMAC0RXST = 0x4301,
93        SDR0_HSF    = 0x4400
[3c6fe2e]94};
95
[502609c8]96enum {
97        CPR0_CLKUPD = 0x20,
98        CPR0_PLLC = 0x40,
99        CPR0_PLLD = 0x60,
100        CPR0_CPUD = 0x80,
101        CPR0_PLBD = 0xA0,
102        CPR0_OPBD = 0xC0,
103        CPR0_PERD = 0xE0,
104        CPR0_AHBD = 0x100,
105        CPR0_ICFG = 0x140
106};
[3c6fe2e]107
108/* Memory-mapped registers */
109
110
111/*======================= Ethernet =================== */
112
113enum {
[502609c8]114        EMAC0EXAddress = 0xEF600900,
115        EMAC1EXAddress = 0xEF600A00,
116       
117        /* 405EX-specific bits in EMAC_MR1 */
118        keEMAC1000Mbps = 0x00800000,
119        keEMAC16KRxFIFO = 0x00280000,
120        keEMAC8KRxFIFO  = 0x00200000,
121        keEMAC4KRxFIFO  = 0x00180000,
122        keEMAC2KRxFIFO  = 0x00100000,
123        keEMAC1KRxFIFO  = 0x00080000,
124        keEMAC16KTxFIFO = 0x00050000,
125        keEMAC8KTxFIFO  = 0x00040000,
126        keEMAC4KTxFIFO  = 0x00030000,
127        keEMAC2KTxFIFO  = 0x00020000,
128        keEMAC1KTxFIFO  = 0x00010000,
129        keEMACJumbo         = 0x00000800,
130        keEMACIPHYAddr4 = 0x180,
131        keEMACOPB50MHz  = 0x00,
132        keEMACOPB66MHz  = 0x08,
133        keEMACOPB83MHz  = 0x10,
134        keEMACOPB100MHz = 0x18,
135        keEMACOPBGt100  = 0x20,
136       
137        /* 405EX-specific bits in MAL0_CFG */
138        keMALRdMaxBurst4  = 0,
139        keMALRdMaxBurst8  = 0x00100000,
140        keMALRdMaxBurst16 = 0x00200000,
141        keMALRdMaxBurst32 = 0x00300000,
142       
143        keMALWrLowPriority    = 0,
144        keMALWrMedLowPriority = 0x00040000,
145        keMALWrMedHiPriority  = 0x00080000,
146        keMALWrHighPriority   = 0x000C0000,
147
148        keMALWrMaxBurst4  = 0,
149        keMALWrMaxBurst8  = 0x00010000,
150        keMALWrMaxBurst16 = 0x00020000,
151        keMALWrMaxBurst32 = 0x00030000,
152       
153        /* 405EX-specific STA bits */
154        keSTARun          = 0x8000,
155        keSTADirectRd = 0x1000,
156        keSTADirectWr = 0x0800,
157        keSTAIndirAddr = 0x2000,
158        keSTAIndirRd  = 0x3000,
159        keSTAIndirWr  = 0x2800
[3c6fe2e]160};
161
162typedef struct GPIORegisters {
163        uint32_t OR;
164        uint32_t GPIO_TCR;              /* Note that TCR is defined as a DCR name */
165        uint32_t OSRL;
166        uint32_t OSRH;
167        uint32_t TSRL;
168        uint32_t TSRH;
169        uint32_t ODR;
170        uint32_t IR;
171        uint32_t RR1;
172        uint32_t RR2;
173        uint32_t RR3;
174        uint32_t unknown;
175        uint32_t ISR1L;
176        uint32_t ISR1H;
177        uint32_t ISR2L;
178        uint32_t ISR2H;
179        uint32_t ISR3L;
180        uint32_t ISR3H;
181} GPIORegisters;
182
183enum { GPIOAddress = 0xEF600800 };
184
[502609c8]185typedef struct RGMIIRegisters {
186        uint32_t FER;
187        uint32_t SSR;
188} RGMIIRegisters;
189
190enum { RGMIIAddress = 0xEF600B00 };
191
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