source: rtems/bsps/powerpc/include/mpc83xx/mpc83xx.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 69.0 KB
Line 
1#ifndef _MPC83XX_MPC83XX_H
2#define _MPC83XX_MPC83XX_H
3
4#include <bspopts.h>
5
6#if MPC83XX_CHIP_TYPE == 8343
7#define M83xx_HAS_PCI      TRUE
8#define M83xx_HAS_USB1     TRUE
9#elif MPC83XX_CHIP_TYPE == 8347
10#define M83xx_HAS_PCI      TRUE
11#define M83xx_HAS_USB1     TRUE
12#define M83xx_HAS_USB2     TRUE
13#elif MPC83XX_CHIP_TYPE == 8349
14#define M83xx_HAS_PCI      TRUE
15#define M83xx_HAS_WIDE_PCI TRUE
16#define M83xx_HAS_USB1     TRUE
17#define M83xx_HAS_USB2     TRUE
18#elif MPC83XX_CHIP_TYPE == 8360
19#define M83xx_HAS_PCI      TRUE
20#define M83xx_HAS_QE       TRUE
21#endif
22
23#if !defined(ASM)
24
25#include <rtems.h>
26#include <bsp/tsec.h>
27
28/* Offset Register Access Reset Section/Page */
29/* System Configuration Registers */
30typedef struct m83xxSysConRegisters_ {
31  volatile uint32_t immrbar;              /* 0x0_00000 Internal memory map base address register R/W 0xFF40_0000 5.2.4.1/5-5 */
32  uint8_t reserved0_0004[0x00008-0x00004];/* 0x0_0004 Reserved, should be cleared */
33  volatile uint32_t altcbar;              /* 0x0_0008 Alternate configuration base address register R/W 0x0000_0000 5.2.4.2/5-7 */
34  uint8_t reserved0_000C[0x00020-0x0000C];/* 0x0_000C--0x0_001C Reserved, should be cleared */
35  volatile uint32_t lblawbar0;            /* 0x0_0020 LBC local access window 0 base address register R/W 0x0000_00001 5.2.4.3/5-7 */
36  volatile uint32_t lblawar0;             /* 0x0_0024 LBC local access window 0 attribute register R/W 0x0000_00002 5.2.4.4/5-8 */
37  volatile uint32_t lblawbar1;            /* 0x0_0028 LBC local access window 1 base address register R/W 0x0000_0000 5.2.4.3/5-7 */
38  volatile uint32_t lblawar1;             /* 0x0_002C LBC local access window 1 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */
39  volatile uint32_t lblawbar2;            /* 0x0_0030 LBC local access window 2 base address register R/W 0x0000_0000 5.2.4.3/5-7 */
40  volatile uint32_t lblawar2;             /* 0x0_0034 LBC local access window 2 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */
41  volatile uint32_t lblawbar3;            /* 0x0_0038 LBC local access window 3 base address register R/W 0x0000_0000 5.2.4.3/5-7 */
42  volatile uint32_t lblawar3;             /* 0x0_003C LBC local access window 3 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */
43  uint8_t reserved0_0040[0x00060-0x00040];/* 0x0_0040--0x0_005C  Reserved, should be cleared    */
44  volatile uint32_t pcilawbar0;           /* 0x0_0060 PCI local access window0 base address register R/W 0x0000_00003 5.2.4.5/5-9 */
45  volatile uint32_t pcilawar0;            /* 0x0_0064 PCI local access window0 attribute register R/W 0x0000_00004 5.2.4.6/5-10 */
46  volatile uint32_t pcilawbar1;           /* 0x0_0068 PCI local access window1 base address register R/W 0x0000_0000 5.2.4.5/5-9 */
47  volatile uint32_t pcilawar1;            /* 0x0_006C PCI local access window1 attribute register R/W 0x0000_0000 5.2.4.6/5-10 */
48  uint8_t reserved0_0070[0x000A0-0x00070];/* 0x0_0070--0x0_009C  Reserved, should be cleared    */
49  volatile uint32_t ddrlawbar0;           /* 0x0_00A0 DDR local access window0 base address register R/W 0x0000_00005 5.2.4.7/5-12 */
50  volatile uint32_t ddrlawar0;            /* 0x0_00A4 DDR local access window0 attribute register R/W 0x0000_00006 5.2.4.8/5-13 */
51  volatile uint32_t ddrlawbar1;           /* 0x0_00A8 DDR local access window1 base address register R/W 0x0000_0000 5.2.4.7/5-12 */
52  volatile uint32_t ddrlawar1;            /* 0x0_00AC DDR local access window1 attribute register R/W 0x0000_0000 5.2.4.8/5-13 */
53  uint8_t reserved0_00B0[0x00100-0x000B0];/* 0x0_00B0--0x0_0100  Reserved, should be cleared    */
54  volatile uint32_t sgprl;                /* 0x0_0100 general purpose register low (SGPRL) R/W 0x0000_0000 5.3.2.1/5-17 */
55  volatile uint32_t sgprh;                /* 0x0_0104 general purpose register high (SGPRH) R/W 0x0000_0000 5.3.2.2/5-17 */
56  volatile uint32_t spridr;               /* 0x0_0108 part and revision ID register (SPRIDR) R 0x0000_0000 5.3.2.3/5-18 */
57  uint8_t reserved0_010C[0x00110-0x0010C];/* 0x0_010C--0x0_0110  Reserved, should be cleared    */
58  volatile uint32_t spcr;                 /* 0x0_0110 priority configuration register (SPCR) R/W 0x0000_0000 5.3.2.4/5-19 */
59  volatile uint32_t sicrl;                /* 0x0_0114 I/O configuration register low (SICRL) R/W 0x0000_0000 5.3.2.5/5-21 */
60  volatile uint32_t sicrh;                /* 0x0_0118 I/O configuration register high (SICRH) R/W 0x0000_00007 5.3.2.6/5-24 */
61  uint8_t reserved0_011C[0x00128-0x0011C];/* 0x0_011C--0x0_0128  Reserved    */
62  volatile uint32_t ddrcdr;               /* 0x0_0128 control driver register (DDRCDR) R/W 0x7304_0001 5.3.2.8/5-28 */
63  volatile uint32_t ddrdsr;               /* 0x0_012C debug status register (DDRDSR) R 0x3300_0000 5.3.2.9/5-30 */
64  uint8_t reserved0_0130[0x00150-0x00130];/* 0x0_0130--0x0_015C  Reserved    */
65  volatile uint32_t gpr_1;                /* 0x0_0150 General Purpose Register 1 (GPR_1) */
66  uint8_t reserved0_0154[0x00200-0x00154];/* 0x0_0154--0x0_01FC  Reserved    */
67} m83xxSysConRegisters_t;
68#define M83xx_SYSCON_SPCR_TBEN (1 << (31-9))
69
70/* Watchdog Timer (WDT) Registers */
71typedef struct m83xxWDTRegisters_ {
72  uint8_t reserved0_0200[0x00204-0x00200];/* 0x0_0200  Reserved, should be cleared    */
73  volatile uint32_t swcrr;                /* 0x0_0204 System watchdog control register R/W 0x0000_0007 5.4.4.1/5-33 */
74  volatile uint32_t swcnr;                /* 0x0_0208 System watchdog count register R 0x0000_FFFF 5.4.4.2/5-34 */
75  uint8_t reserved0_020C[(0x0020E)-0x0020C];/* 0x0_020C  Reserved, should be cleared    */
76  volatile uint16_t swsrr;                /* 0x0_020E System watchdog service register R/W 0x0000_0000 5.4.4.3/5-34 */
77} m83xxWDTRegisters_t;
78
79/* Real Time Clock Module Registers (RTC) */
80typedef struct m83xxRTCRegisters_ {
81  volatile uint32_t rtcnr;                /* 0x0_0300 Real time counter control register R/W 0x0000_0000 5.5.5.1/5-40 */
82  volatile uint32_t rtldr;                /* 0x0_0304 Real time counter load register R/W 0x0000_0000 5.5.5.2/5-41 */
83  volatile uint32_t rtpsr;                /* 0x0_0308 Real time counter prescale register R/W 0x0000_0000 5.5.5.3/5-41 */
84  volatile uint32_t rtctr;                /* 0x0_030C Real time counter register R 0x0000_0000 5.5.5.4/5-42 */
85  volatile uint32_t rtevr;                /* 0x0_0310 Real time counter event register R/W 0x0000_0000 5.5.5.5/5-42 */
86  volatile uint32_t rtalr;                /* 0x0_0314 Real time counter alarm register R/W 0xFFFF_FFFF 5.5.5.6/5-43 */
87  uint8_t reserved0_0314[0x00320-0x00318];/* 0x0_0318--0x0_031F Reserved; should be cleared */
88} m83xxRTCRegisters_t;
89
90  /* Periodic Interval Timer (PIT) Registers */
91typedef struct m83xxPITRegisters_ {
92  volatile uint32_t ptcnr;                 /* 0x0_0400 Periodic interval timer control register R/W 0x0000_0000 5.6.5.1/5-47 */
93  volatile uint32_t ptldr;                 /* 0x0_0404 Periodic interval timer load register R/W 0x0000_0000 5.6.5.2/5-48 */
94  volatile uint32_t ptpsr;                 /* 0x0_0408 Periodic interval timer prescale register R/W 0x0000_0000 5.6.5.3/5-49 */
95  volatile uint32_t ptctr;                 /* 0x0_040C Periodic interval timer counter register R 0x0000_0000 5.6.5.4/5-49 */
96  volatile uint32_t ptevr;                 /* 0x0_0410 Periodic interval timer event register R/W 0x0000_0000 5.6.5.5/5-50 */
97  uint8_t reserved0_0414[0x00500-0x00414]; /* 0x0_0414--0x0_041F Reserved, should be cleared    */
98} m83xxPITRegisters_t;
99
100  /* Global Timers Module 1/2 */
101#define M83xxGTIdx(n)  (n&3)
102#define M83xxGTLowIdx(n)  (n&1)
103#define M83xxGTHighIdx(n) (((n)>>1)&1)
104#define M83xxGTModIdx(n)  (((n)>>2)&1)
105
106#define M83xxGTIdxCnt  (4)
107#define M83xxGTLowCnt  (2)
108#define M83xxGTHighCnt (2)
109#define M83xxGTModCnt  (2)
110
111typedef struct m83xxGTMRegisters_ {
112  struct {
113    volatile uint8_t  reg;                     /* 0x0_0500 Timer 1+2/3+4 global timers configuration register R/W 0x00 5.7.5.1/5-57 */
114    uint8_t reserved0_0501[0x00504-0x00501];   /* 0x0_0501--0x0_0503 Reserved, should be cleared */
115  } gtcfr[M83xxGTHighCnt];
116  uint8_t reserved0_0508[0x00510-0x00508];     /* 0x0_0508--0x0_050f Reserved, should be cleared */
117  struct {
118    volatile uint16_t gtmdr[M83xxGTLowCnt];    /* 0x0_0510 Timer 1/2 global timers mode register R/W 0x0000 5.7.5.2/5-60 */
119    volatile uint16_t gtrfr[M83xxGTLowCnt];    /* 0x0_0514 Timer 1/2 global timers reference register R/W 0x0000 5.7.5.3/5-62 */
120    volatile uint16_t gtcpr[M83xxGTLowCnt];    /* 0x0_0518 Timer 1/2 global timers capture register R/W 0x0000 5.7.5.4/5-62 */
121    volatile uint16_t gtcnr[M83xxGTLowCnt];    /* 0x0_051C Timer 1/2 global timers counter register R/W 0x0000 5.7.5.5/5-63 */
122  } gt_tim_regs[M83xxGTHighCnt];
123  volatile uint16_t gtevr[M83xxGTIdxCnt];      /* 0x0_0530 Timer 1-4 global timers event register Special 0x0000 5.7.5.6/5-63 */
124  volatile uint16_t gtpsr[M83xxGTIdxCnt];      /* 0x0_0538 Timer 1-4 global timers prescale register R/W 0x0003 5.7.5.7/5-64 */
125  uint8_t reserved0_0540[0x00600-0x00540];     /* 0x0_0540--0x0_05fc Reserved */
126} m83xxGTMRegisters_t;
127
128  /* Integrated Programmable Interrupt Controller (IPIC) */
129typedef struct m83xxIPICRegisters_ {
130  volatile uint32_t sicfr;                 /* 0x0_0700 System global interrupt configuration register R/W 0x0000_0000 8.5.1/8-8 */
131  volatile uint32_t sivcr;                 /* 0x0_0704 System global interrupt vector register R 0x0000_0000 8.5.2/8-9 */
132  volatile uint32_t sipnr[2];              /* 0x0_0708 System internal interrupt pending register H/L R 0x0000_0000 8.5.3/8-11 */
133  volatile uint32_t siprr[4];              /* 0x0_0710 System internal interrupt group A-D priority register R/W 0x0530_9770 8.5.4/8-14 */
134  volatile uint32_t simsr[2];              /* 0x0_0720 System internal interrupt mask register H/L R/W 0x0000_0000 8.5.6/8-15 */
135  uint8_t reserved0_0728[0x0072C-0x00728]; /* 0x0_072C--0x0_0728 Reserved, should be cleared */
136  volatile uint32_t sepnr;                 /* 0x0_072C System external interrupt pending register R/W Special 8.5.8/8-18 */
137  volatile uint32_t smprr[2];              /* 0x0_0730 System mixed interrupt group A/B priority register R/W 0x0530_9770 8.5.9/8-18 */
138  volatile uint32_t semsr;                 /* 0x0_0738 System external interrupt mask register R/W 0x0000_0000 8.5.11/8-20 */
139  volatile uint32_t secnr;                 /* 0x0_073C System external interrupt control register R/W 0x0000_0000 8.5.12/8-21 */
140  volatile uint32_t sersr;                 /* 0x0_0740 System error status register R/W 0x0000_0000 8.5.13/8-22 */
141  volatile uint32_t sermr;                 /* 0x0_0744 System error mask register R/W $ 8.5.14/8-23 */
142  volatile uint32_t sercr;                 /* 0x0_0748 System error control register R/W 0x0000_0000 8.5.15/8-24 */
143  uint8_t reserved0_074C[0x00750-0x0074C]; /* 0x0_074C--0x0_074F Reserved, should be cleared */
144  volatile uint32_t sifcr[2];              /* 0x0_0750 System internal interrupt force register H/L R/W 0x0000_0000 8.5.16/8-25 */
145  volatile uint32_t sefcr;                 /* 0x0_0758 System external interrupt force register R/W 0x0000_0000 8.5.17/8-26 */
146  volatile uint32_t serfr;                 /* 0x0_075C System error force register R/W 0x0000_0000 8.5.18/8-26 */
147  volatile uint32_t scvcr;                 /* 0x0_0760 System critical interrupt vector register R 0x0000_0000 8.5.19/8-27 */
148  volatile uint32_t smvcr;                 /* 0x0_0764 System management interrupt vector register R 0x0000_0000 8.5.20/8-27 */
149  uint8_t reserved0_0760[0x00800-0x00768]; /* 0x0_0768--0x0_07FF Reserved, should be cleared */
150} m83xxIPICRegisters_t;
151
152/* get vector number from vector register content */
153#define MPC83xx_VCR_TO_VEC(regval) ((regval) & 0x7f)
154
155
156  /* System Arbiter Registers */
157typedef struct m83xxARBRegisters_ {
158  volatile uint32_t acr;                   /* 0x0_0800 Arbiter configuration register R/W 0x0000_0000 6.2.1/6-2 */
159  volatile uint32_t atr;                   /* 0x0_0804 Arbiter timers register R/W 0x00FF_00FF 6.2.2/6-4 */
160  uint8_t reserved0_0808[0x0080C-0x00808]; /* 0x0_0808 Reserved, should be cleared R 0x0000_0000  */
161  volatile uint32_t aer;                   /* 0x0_080C Arbiter event register R/W 0x0000_0000 6.2.3/6-5 */
162  volatile uint32_t aidr;                  /* 0x0_0810 Arbiter interrupt definition register R/W 0x0000_0000 6.2.4/6-6 */
163  volatile uint32_t amr;                   /* 0x0_0814 Arbiter mask register R/W 0x0000_0000 6.2.5/6-7 */
164  volatile uint32_t aeatr;                 /* 0x0_0818 Arbiter event attributes register R 0x0000_0000 6.2.6/6-7 */
165  volatile uint32_t aeadr;                 /* 0x0_081C Arbiter event address register R 0x0000_0000 6.2.7/6-9 */
166  volatile uint32_t aerr;                  /* 0x0_0820 Arbiter event response register R/W 0x0000_0000 6.2.8/6-10 */
167  uint8_t reserved0_0824[0x00900-0x00824]; /* 0x0_0824--0x0_08FF Reserved, should be cleared */
168} m83xxARBRegisters_t;
169
170  /* Reset Module */
171typedef struct m83xxRESRegisters_ {
172  volatile uint32_t rcwlr;                 /* 0x0_0900 Reset configuration word low register R 0x0000_0000 4.5.1.1/4-32 */
173  volatile uint32_t rcwhr;                 /* 0x0_0904 Reset configuration word high register R 0x0000_0000 4.5.1.2/4-32 */
174  uint8_t reserved0_0908[0x00910-0x00908]; /* 0x0_0908--0x0_090C Reserved, should be cleared */
175  volatile uint32_t rsr;                   /* 0x0_0910 Reset status register R/W 0x0000_0000 4.5.1.3/4-33 */
176  volatile uint32_t rmr;                   /* 0x0_0914 Reset mode register R/W 0x0000_0000 4.5.1.4/4-34 */
177  volatile uint32_t rpr;                   /* 0x0_0918 Reset protection register R/W 0x0000_0000 4.5.1.5/4-35 */
178  volatile uint32_t rcr;                   /* 0x0_091C Reset control register R/W 0x0000_0000 4.5.1.6/4-36 */
179  volatile uint32_t rcer;                  /* 0x0_0920 Reset control enable register R/W 0x0000_0000 4.5.1.7/4-36 */
180  uint8_t reserved0_0924[0x00A00-0x00924]; /* 0x0_0924--0x0_09FC Reserved, should be cleared */
181} m83xxRESRegisters_t;
182
183  /* Clock Module */
184typedef struct m83xxCLKRegisters_ {
185  volatile uint32_t spmr; /* 0x0_0A00 System PLL mode register R 0x0000_0000 4.5.2.1/4-37 */
186  volatile uint32_t occr; /* 0x0_0A04 Output clock control register R/W 0x0000_0000 4.5.2.2/4-38 */
187  volatile uint32_t sccr; /* 0x0_0A08 System clock control register R/W 0xFFFF_FFFF 4.5.2.3/4-40 */
188  uint8_t reserved0_0A08[0x00B00-0x00A0C]; /* 0x0_0A0C--0x0_0AFC Reserved, should be cleared */
189} m83xxCLKRegisters_t;
190  /* Power Management Control Module */
191typedef struct m83xxPMCRegisters_ {
192  volatile uint32_t pmccr; /* 0x0_0B00 Power management controller configuration register R/W 0x0000_0000 5.8.3.1/5-69 */
193  volatile uint32_t pmcer; /* 0x0_0B04 Power management controller event register R/W 0x0000_0000 5.8.3.2/5-70 */
194  volatile uint32_t pmcmr; /* 0x0_0B08 Power management controller mask register R/W 0x0000_0000 5.8.3.3/5-71 */
195  uint8_t reserved0_0B10[0x00C00-0x00B0C]; /* 0x0_0B0C--0x0_0BFC Reserved, should be cleared */
196} m83xxPMCRegisters_t;
197  /* GPIO1 Registers */
198typedef struct m83xxGPIORegisters_ {
199  volatile uint32_t gpdir; /* 0x0_0C00 GPIO1/2 direction register R/W 0x0000_0000 21.3.1/21-3 */
200  volatile uint32_t gpdr;  /* 0x0_0C04 GPIO1/2 open drain register R/W 0x0000_0000 21.3.2/21-4 */
201  volatile uint32_t gpdat; /* 0x0_0C08 GPIO1/2 data register R/W 0x0000_0000 21.3.3/21-4 */
202  volatile uint32_t gpier; /* 0x0_0C0C GPIO1/2 interrupt event register R/W Undefined 21.3.4/21-5 */
203  volatile uint32_t gpimr; /* 0x0_0C10 GPIO1/2 interrupt mask register R/W 0x0000_0000 21.3.5/21-5 */
204  volatile uint32_t gpicr; /* 0x0_0C14 GPIO1/2 external interrupt control register R/W 0x0000_0000 21.3.6/21-6 */
205  uint8_t reserved0_0C1C[0x00D00-0x00C18]; /* 0x0_0C18--0x0_0CFF Reserved, should be cleared */
206} m83xxGPIORegisters_t;
207
208  /* DLL */
209typedef struct m83xxDLLRegisters_ {
210  uint8_t reserved0_1000[0x01010-0x01000]; /* 0x0_1000--0x0_100F Reserved, should be cleared */
211  volatile uint32_t mckenr;                /* 0x0_1010 MCK enable register (MCKENR) R/W 0xFC00_0000 4.5.3/4-41 */
212  uint8_t reserved0_1014[0x01100-0x01014]; /* 0x0_1014--0x0_10FF Reserved, should be cleared */
213  volatile uint32_t reserved0_1100;        /* 0x0_1100 Reserved. Reset value should be preserved. R/W 0x0500_0280  */
214  volatile uint32_t reserved0_1104;        /* 0x0_1104 Reserved. Reset value should be preserved. R/W 0x8004_0810  */
215  volatile uint32_t dllovr;                /* 0x0_1108 DLL override register (DLLOVR) R/W 0x0000_0000 22.4.1/22-4 */
216  volatile uint32_t dllsr;                 /* 0x0_110C DLL status register (DLLSR) R 0x0000_0000 22.4.2/22-4 */
217  volatile uint32_t dllck;                 /* 0x0_1110 DLL clock register (DLLCK) R/W 0xFC00_0000 22.4.3/22-5 */
218  uint8_t reserved0_1110[0x01200-0x01114]; /* 0x0_1114--0x0_11FF Reserved, should be cleared */
219} m83xxDLLRegisters_t;
220
221  /* DDR Memory Controller Memory Map */
222typedef struct m83xxDDRRegisters_ {
223  volatile uint32_t cs0_bnds;              /* 0x0_2000 Chip select 0 memory bounds R/W 0x0000_0000 9.4.1.1/9-10 */
224  uint8_t reserved0_2004[0x02008-0x02004]; /* 0x0_2004--0x0_2008 Reserved, should be cleared */
225  volatile uint32_t cs1_bnds;              /* 0x0_2008 Chip select 1 memory bounds R/W 0x0000_0000 */
226  uint8_t reserved0_200C[0x02010-0x0200C]; /* 0x0_200C--0x0_2010 Reserved, should be cleared */
227  volatile uint32_t cs2_bnds;              /* 0x0_2010 Chip select 2 memory bounds R/W 0x0000_0000 */
228  uint8_t reserved0_2014[0x02018-0x02014]; /* 0x0_2014--0x0_2018 Reserved, should be cleared */
229  volatile uint32_t cs3_bnds;              /* 0x0_2018 Chip select 3 memory bounds R/W 0x0000_0000 */
230  uint8_t reserved0_201C[0x02080-0x0201C]; /* 0x0_201C--0x0_207F Reserved, should be cleared */
231  volatile uint32_t cs0_config;            /* 0x0_2080 Chip select 0 configuration R/W 0x0000_0000 9.4.1.2/9-11 */
232  volatile uint32_t cs1_config;            /* 0x0_2084 Chip select 1 configuration R/W 0x0000_0000 */
233  volatile uint32_t cs2_config;            /* 0x0_2088 Chip select 2 configuration R/W 0x0000_0000 */
234  volatile uint32_t cs3_config;            /* 0x0_208C Chip select 3 configuration R/W 0x0000_0000 */
235  uint8_t reserved0_2090[0x02100-0x02090]; /* 0x0_2090--0x0_2100 Reserved, should be cleared */
236  volatile uint32_t timing_cfg_3;          /* 0x0_2100 DDR SDRAM timing configuration 3 R/W 0x0000_0000 9.4.1.3/9-13 */
237  volatile uint32_t timing_cfg_0;          /* 0x0_2104 DDR SDRAM timing configuration 0 R/W 0x0011_0105 9.4.1.4/9-14 */
238  volatile uint32_t timing_cfg_1;          /* 0x0_2108 DDR SDRAM timing configuration 1 R/W 0x0000_0000 9.4.1.5/9-16 */
239  volatile uint32_t timing_cfg_2;          /* 0x0_210C DDR SDRAM timing configuration 2 R/W 0x0000_0000 9.4.1.6/9-18 */
240  volatile uint32_t ddr_sdram_cfg;         /* 0x0_2110 DDR SDRAM control configuration R/W 0x0200_0000 9.4.1.7/9-20 */
241  volatile uint32_t ddr_sdram_cfg_2;       /* 0x0_2114 DDR SDRAM control configuration 2 R/W 0x0000_0000 9.4.1.8/9-22 */
242  volatile uint32_t ddr_sdram_mode;        /* 0x0;_2118 DDR SDRAM mode configuration R/W 0x0000_0000 9.4.1.9/9-24 */
243  volatile uint32_t ddr_sdram_mode_2;      /* 0x0_211C DDR SDRAM mode configuration 2 R/W 0x0000_0000 9.4.1.10/9-24 */
244  volatile uint32_t ddr_sdram_md_cntl;     /* 0x0_2120 DDR SDRAM mode control R/W 0x0000_0000 9.4.1.11/9-25 */
245  volatile uint32_t ddr_sdram_interval;    /* 0x0_2124 DDR SDRAM interval configuration R/W 0x0000_0000 9.4.1.12/9-27 */
246  volatile uint32_t ddr_data_init;         /* 0x0_2128 DDR SDRAM data initialization R/W 0x0000_0000 9.4.1.13/9-28 */
247  uint8_t reserved0_212C[0x02130-0x0212C]; /* 0x0_212C Reserved  $ $ */
248  volatile uint32_t ddr_sdram_clk_cntl;    /* 0x0_2130 DDR SDRAM clock control R/W 0x0200_0000 9.4.1.14/9-28 */
249  uint8_t reserved0_2134[0x02148-0x02134]; /* 0x0_2140 Reserved  $ $ */
250  volatile uint32_t ddr_init_address;      /* 0x0_2148 DDR training initialization address R/W 0x0000_0000 9.4.1.15/9-29 */
251  uint8_t reserved0_214C[0x02BF8-0x0214C]; /* 0x0_214C Reserved  $ $ */
252  volatile uint32_t ddr_ip_rev1;           /* 0x0_2BF8 DDR IP block revision 1 R 0x0002_0200 9.4.1.16/9-30 */
253  volatile uint32_t ddr_ip_rev2;           /* 0x0_2BFC DDR IP block revision 2 R 0x0000_0000 9.4.1.17/9-30 */
254  uint8_t reserved0_2C00[0x02E00-0x02C00]; /* 0x0_2C00 Reserved  $ $ */
255  volatile uint32_t data_err_inject_hi;    /* 0x0_2E00 Memory data path error injection mask high R/W 0x0000_0000 9.4.1.18/9-31 */
256  volatile uint32_t data_err_inject_lo;    /* 0x0_2E04 Memory data path error injection mask low R/W 0x0000_0000 9.4.1.19/9-31 */
257  volatile uint32_t ecc_err_inject;        /* 0x0_2E08 Memory data path error injection mask ECC R/W 0x0000_0000 9.4.1.20/9-32 */
258  uint8_t reserved0_2E0C[0x02E20-0x02E0C]; /* 0x0_2E0C Reserved  $ $ */
259  volatile uint32_t capture_data_hi;       /* 0x0_2E20 Memory data path read capture high R/W 0x0000_0000 9.4.1.21/9-32 */
260  volatile uint32_t capture_data_lo;       /* 0x0_2E24 Memory data path read capture low R/W 0x0000_0000 9.4.1.22/9-33 */
261  volatile uint32_t capture_ecc;           /* 0x0_2E28 Memory data path read capture ECC R/W 0x0000_0000 9.4.1.23/9-33 */
262  uint8_t reserved0_2E2C[0x02E40-0x02E2C]; /* 0x0_2E2C Reserved  $ $ */
263  volatile uint32_t err_detect;            /* 0x0_2E40 Memory error detect w1c 0x0000_0000 9.4.1.24/9-33 */
264  volatile uint32_t err_disable;           /* 0x0_2E44 Memory error disable R/W 0x0000_0000 9.4.1.25/9-34 */
265  volatile uint32_t err_int_en;            /* 0x0_2E48 Memory error interrupt enable R/W 0x0000_0000 9.4.1.26/9-35 */
266  volatile uint32_t capture_attributes;    /* 0x0_2E4C Memory error attributes capture R/W 0x0000_0000 9.4.1.27/9-36 */
267  volatile uint32_t capture_address;       /* 0x0_2E50 Memory error address capture R/W 0x0000_0000 9.4.1.28/9-37 */
268  uint8_t reserved0_2E54[0x02E58-0x02E54]; /* 0x0_2E54 Reserved  $ $ */
269  volatile uint32_t err_sbe;               /* 0x0_2E58 Single-Bit ECC memory error management R/W 0x0000_0000 9.4.1.29/9-37 */
270  uint8_t reserved0_2E5C[0x2F00-0x2E5C];
271} m83xxDDRRegisters_t;
272
273  /* I2C Controller */
274typedef struct m83xxI2CRegisters_ {
275  volatile uint8_t i2cadr;  /* 0x0_3000 I2C1 address register R/W 0x00 17.3.1.1/17-5 */
276  uint8_t reserved0_3001[0x03004-0x03001];
277  volatile uint8_t i2cfdr; /* 0x0_3004 I2C1 frequency divider register R/W 0x00 17.3.1.2/17-5 */
278  uint8_t reserved0_3005[0x03008-0x03005];
279  volatile uint8_t i2ccr; /* 0x0_3008 I2C1 control register R/W 0x00 17.3.1.3/17-6 */
280  uint8_t reserved0_3009[0x0300C-0x03009];
281  volatile uint8_t i2csr; /* 0x0_300C I2C1 status register R/W 0x81 17.3.1.4/17-8 */
282  uint8_t reserved0_300D[0x03010-0x0300D];
283  volatile uint8_t i2cdr; /* 0x0_3010 I2C1 data register R/W 0x00 17.3.1.5/17-9 */
284  uint8_t reserved0_3011[0x03014-0x03011];
285  volatile uint8_t i2cdfsrr; /* 0x0_3014 I2C1 digital filter sampling rate register R/W 0x0001_0000 17.3.1.6/17-10 */
286  uint8_t reserved0_3015[0x03018-0x03015];
287  uint8_t reserved0_3018[0x03100-0x03018]; /* 0x0_3018-30FF Reserved, should be cleared */
288} m83xxI2CRegisters_t;
289
290  /* DUART */
291typedef struct m83xxDUARTRegisters_ {
292  union {
293    volatile uint8_t urbr;                /* 0x0_4500 ULCR[DLAB] = 0 UART1 receiver buffer register R 0x00 18.3.1.1/18-6 */
294    volatile uint8_t uthr;                /* 0x0_4500 ULCR[DLAB] = 0 UART1 transmitter holding register W 0x00 18.3.1.2/18-6 */
295    volatile uint8_t udlb;                /* 0x0_4500 ULCR[DLAB] = 1 UART1 divisor least significant byte register R/W 0x00 18.3.1.3/18-7 */
296  } urbr_uthr_udlb;
297  union {
298    volatile uint8_t uier;                /* 0x0_4501 ULCR[DLAB] = 0 UART1 interrupt enable register R/W 0x00 18.3.1.4/18-8 */
299    volatile uint8_t udmb;                /* 0x0_4501 ULCR[DLAB] = 1 UART1 divisor most significant byte register R/W 0x00 18.3.1.3/18-7 */
300  } uier_udmb;
301  union {
302    volatile uint8_t uiir;                /* 0x0_4502 ULCR[DLAB] = 0 UART1 interrupt ID register R 0x01 18.3.1.5/18-9 */
303    volatile uint8_t ufcr;                /* 0x0_4502 ULCR[DLAB] = 0 UART1 FIFO control register W 0x00 18.3.1.6/18-10 */
304    volatile uint8_t uafr;                /* 0x0_4502 ULCR[DLAB] = 1 UART1 alternate function register R/W 0x00 18.3.1.12/18-16 */
305  } uiir_ufcr_uafr;
306  volatile uint8_t ulcr;                  /* 0x0_4503 ULCR[DLAB] = x UART1 line control register R/W 0x00 18.3.1.7/18-11 */
307  volatile uint8_t umcr;                  /* 0x0_4504 ULCR[DLAB] = x UART1 MODEM control register R/W 0x00 18.3.1.8/18-13 */
308  volatile uint8_t ulsr;                  /* 0x0_4505 ULCR[DLAB] = x UART1 line status register R 0x60 18.3.1.9/18-14 */
309  volatile uint8_t umsr;                  /* 0x0_4506 ULCR[DLAB] = x UART1 MODEM status register R 0x00 18.3.1.10/18-15 */
310  volatile uint8_t uscr;                  /* 0x0_4507 ULCR[DLAB] = x UART1 scratch register R/W 0x00 18.3.1.11/18-16 */
311  uint8_t reserved0_4508[0x04510-0x04508];/* 0x0_4508-450F Reserved */
312  volatile uint8_t udsr;                  /* 0x0_4510 ULCR[DLAB] = x UART1 DMA status register R 0x01 18.3.1.13/18-17 */
313  uint8_t reserved0_4511[0x04600-0x04511];/* 0x0_4511-45FF Reserved */
314} m83xxDUARTRegisters_t;
315
316  /* Local Bus Controller (LBC) Registers */
317typedef struct m83xxLBCRegisters_ {
318  struct {
319    volatile uint32_t br;                 /* 0x0_5000 Base register 0 ,R/W 0x0000_RR01 10.3.1.1/10-11 */
320    volatile uint32_t optionsr;                 /* 0x0_5004 Options register 0 R/W 0x0000_0FF7 10.3.1.2/10-12 */
321  } bor[8];
322  uint8_t reserved0_5040[0x05068-0x05040];/* 0x0_5040-5067 Reserved */
323  volatile uint32_t mar;                  /* 0x0_5068 UPM address register R/W 0x0000_0000 10.3.1.3/10-18 */
324  uint8_t reserved0_506C[0x05070-0x0506C];/* 0x0_506C-506F Reserved */
325  volatile uint32_t mamr;                 /* 0x0_5070 UPMA mode register R/W 0x0000_0000 10.3.1.4/10-19 */
326  volatile uint32_t mbmr;                 /* 0x0_5074 UPMB mode register R/W 0x0000_0000 10.3.1.4/10-19 */
327  volatile uint32_t mcmr;                 /* 0x0_5078 UPMC mode register R/W 0x0000_0000 10.3.1.4/10-19 */
328  uint8_t reserved0_507C[0x05084-0x0507C];/* 0x0_507C-5083 Reserved */
329  volatile uint32_t mrtpr;                /* 0x0_5084 Memory refresh timer prescaler register R/W 0x0000_0000 10.3.1.5/10-21 */
330  volatile uint32_t mdr;                  /* 0x0_5088 UPM data register R/W 0x0000_0000 10.3.1.6/10-22 */
331  uint8_t reserved0_508C[0x05094-0x0508C];/* 0x0_508C-5093 Reserved */
332  volatile uint32_t lsdmr;                /* 0x0_5094 SDRAM mode register R/W 0x0000_0000 10.3.1.7/10-22 */
333  uint8_t reserved0_5098[0x050A0-0x05098];/* 0x0_5098-509F Reserved */
334  volatile uint32_t lurt;                 /* 0x0_50A0 UPM refresh timer R/W 0x0000_0000 10.3.1.8/10-24 */
335  volatile uint32_t lsrt;                 /* 0x0_50A4 SDRAM refresh timer R/W 0x0000_0000 10.3.1.9/10-25 */
336  uint8_t reserved0_50A8[0x050B0-0x050A8];/* 0x0_50A8-50AF Reserved */
337  volatile uint32_t ltesr;                /* 0x0_50B0 Transfer error status register Read/ bit-reset 0x0000_0000 10.3.1.10/10-26 */
338  volatile uint32_t ltedr;                /* 0x0_50B4 Transfer error check disable register R/W 0x0000_0000 10.3.1.11/10-27 */
339  volatile uint32_t lteir;                /* 0x0_50B8 Transfer error interrupt enable register R/W 0x0000_0000 10.3.1.12/10-27 */
340  volatile uint32_t lteatr;               /* 0x0_50BC Transfer error attributes register R/W 0x0000_0000 10.3.1.13/10-28 */
341  volatile uint32_t ltear;                /* 0x0_50C0 Transfer error address register R/W 0x0000_0000 10.3.1.14/10-29 */
342  uint8_t reserved0_50C4[0x050D0-0x050C4];/* 0x0_50C4-50CF Reserved */
343  volatile uint32_t lbcr;                 /* 0x0_50D0 Local bus configuration register R/W 0x0000_0000 10.3.1.15/10-29 */
344  volatile uint32_t lcrr;                 /* 0x0_50D4 Clock ratio register R/W 0x8000_0008 10.3.1.16/10-30 */
345  uint8_t reserved0_50D8[0x05100-0x050D8];/* 0x0_50D8-50FF Reserved */
346} m83xxLBCRegisters_t;
347
348  /* Serial Peripheral Interface (SPI) */
349typedef struct m83xxSPIRegisters_ {
350  uint8_t reserved0_7000[0x07020-0x07000];/* 0x0_7000-7020 Reserved, should be cleared */
351  volatile uint32_t spmode;               /* 0x0_7020 SPI mode register R/W 0x0000_0000 19.4.1.1/19-9 */
352  volatile uint32_t spie;                 /* 0x0_7024 SPI event register R/W 0x0000_0000 19.4.1.2/19-11 */
353  volatile uint32_t spim;                 /* 0x0_7028 SPI mask register R/W 0x0000_0000 19.4.1.3/19-13 */
354  volatile uint32_t spcom;                /* 0x0_702C SPI command register R/W 0x0000_0000 19.4.1.4/19-14 */
355  volatile uint32_t spitd;                /* 0x0_7030 SPI transmit register R/W 0x0000_0000 19.4.1.5/19-14 */
356  volatile uint32_t spird;                /* 0x0_7034 SPI receive register R 0xFFFF_FFFF 19.4.1.6/19-15 */
357  uint8_t reserved0_7038[0x07100-0x07038];/* 0x0_7038-70FF Reserved */
358} m83xxSPIRegisters_t;
359                                              /* SPIMODE register fields    */
360#define  MPC83XX_SPIMODE_LOOP   (1   << (31- 1)) /* loopback                */
361#define  MPC83XX_SPIMODE_CI     (1   << (31- 2)) /* clock invert            */
362#define  MPC83XX_SPIMODE_CP     (1   << (31- 3)) /* clock phase             */
363#define  MPC83XX_SPIMODE_DIV16  (1   << (31- 4)) /* divide by 16            */
364#define  MPC83XX_SPIMODE_REV    (1   << (31- 5)) /* LSB first               */
365#define  MPC83XX_SPIMODE_M_S    (1   << (31- 6)) /* master/slave            */
366#define  MPC83XX_SPIMODE_EN     (1   << (31- 7)) /* enable                  */
367#define  MPC83XX_SPIMODE_LEN(n) ((n) << (31-11)) /* length code             */
368#define  MPC83XX_SPIMODE_PM(n)  ((n) << (31-15)) /* prescaler               */
369#define  MPC83XX_SPIMODE_OD     (1   << (31-19)) /* open drain              */
370
371                                               /* SPCOM  register fields    */
372#define  MPC83XX_SPCOM_LST    (1   << (31- 9))  /* last transfer            */
373
374                                            /* SPIE/M register fields     */
375#define  MPC83XX_SPIE_LT     (1 << (31-17)) /* last character transmitted */
376#define  MPC83XX_SPIE_DNR    (1 << (31-18)) /* data not ready             */
377#define  MPC83XX_SPIE_OV     (1 << (31-19)) /* overrun                    */
378#define  MPC83XX_SPIE_UN     (1 << (31-20)) /* unterrun                   */
379#define  MPC83XX_SPIE_MME    (1 << (31-21)) /* multi-master error         */
380#define  MPC83XX_SPIE_NE     (1 << (31-22)) /* not empty                  */
381#define  MPC83XX_SPIE_NF     (1 << (31-23)) /* not full                   */
382
383typedef struct m83xxDMARegisters_ {
384  /* DMA Registers */
385  uint8_t reserved0_8000[0x08030-0x08000];/* 0x0_8000-0x0_802f Reserved */
386  volatile uint32_t omisr;                /* 0x0_8030 Outbound message interrupt status register Special 0x0000_0000 12.4.1/12-4 */
387  volatile uint32_t omimr;                /* 0x0_8034 Outbound message interrupt mask register R/W 0x0000_0000 12.4.2/12-6 */
388  uint8_t reserved0_8038[0x08050-0x08038];/* 0x0_8038-0x0_804f Reserved */
389  volatile uint32_t imr0;                 /* 0x0_8050 Inbound message register 0 R/W 0x0000_0000 12.4.3/12-7 */
390  volatile uint32_t imr1;                 /* 0x0_8054 Inbound message register 1 R/W 0x0000_0000 12.4.3/12-7 */
391  volatile uint32_t omr0;                 /* 0x0_8058 Outbound message register 0 R/W 0x0000_0000 12.4.4/12-7 */
392  volatile uint32_t omr1;                 /* 0x0_805C Outbound message register 1 R/W 0x0000_0000 12.4.4/12-7 */
393  volatile uint32_t odr;                  /* 0x0_8060 Outbound doorbell register R/W 0x0000_0000 12.4.5/12-8 */
394  uint8_t reserved0_8064[0x08068-0x08064];/* 0x0_8064-0x0_8067 Reserved */
395  volatile uint32_t idr;                  /* 0x0_8068 Inbound doorbell register R/W 0x0000_0000 12.4.5/12-8 */
396  uint8_t reserved0_806C[0x08080-0x0806C];/* 0x0_806C-0x0_807F Reserved */
397  volatile uint32_t imisr;                /* 0x0_8080 Inbound message interrupt status register R/W 0x0000_0000 12.4.6/12-9 */
398  volatile uint32_t imimr;                /* 0x0_8084 Inbound message interrupt mask register R/W 0x0000_0000 12.4.7/12-11 */
399  uint8_t reserved0_8088[0x080A8-0x08088];/* 0x0_8088-0x0_80A7 Reserved */
400  struct m83xxDMAChannelRegisters_ {
401    uint8_t reserved0_80A8[0x08100-0x080A8];/* 0x0_80A8-0x0_80FF Reserved */
402    volatile uint32_t dmamr0;               /* 0x0_8100 DMA 0 mode register R/W 0x0000_0000 12.4.8.1/12-12 */
403    volatile uint32_t dmasr0;               /* 0x0_8104 DMA 0 status register R/W 0x0000_0000 12.4.8.2/12-14 */
404    volatile uint32_t dmacdar0;             /* 0x0_8108 DMA 0 current descriptor address register R/W 0x0000_0000 12.4.8.3/12-15 */
405    uint8_t reserved0_810C[0x08110-0x0810C];/* 0x0_810C-0x0_810F Reserved */
406    volatile uint32_t dmasar0;              /* 0x0_8110 DMA 0 source address register R/W 0x0000_0000 12.4.8.4/12-16 */
407    uint8_t reserved0_8114[0x08118-0x08114];/* 0x0_8114-0x0_8117 Reserved */
408    volatile uint32_t dmadar0;              /* 0x0_8118 DMA 0 destination address register R/W 0x0000_0000 12.4.8.5/12-16 */
409    uint8_t reserved0_811C[0x08120-0x0811C];/* 0x0_8120-0x0_811C Reserved */
410    volatile uint32_t dmabcr0;              /* 0x0_8120 DMA 0 byte count register R/W 0x0000_0000 12.4.8.6/12-17 */
411    volatile uint32_t dmandar0;             /* 0x0_8124 DMA 0 next descriptor address register R/W 0x0000_0000 12.4.8.7/12-17 */
412  }chan[4];
413  volatile uint32_t dmagsr;                 /* 0x0_82A8 DMA general status register R 0x0000_0000 12.4.8.8/12-18 */
414  uint8_t reserved0_82AC[0x082FF-0x082AC];  /* 0x0_82AC-0x0_82FF Reserved, should be cleared */
415} m83xxDMARegisters_t;
416
417/* Registers in DMA section use little-endian byte order */
418
419/* DMA mode register */
420#define MPC83XX_DMAMR_DRCNT_1               (5 << 24)
421#define MPC83XX_DMAMR_DRCNT_2               (6 << 24)
422#define MPC83XX_DMAMR_DRCNT_4               (7 << 24)
423#define MPC83XX_DMAMR_DRCNT_8               (8 << 24)
424#define MPC83XX_DMAMR_DRCNT_16              (9 << 24)
425#define MPC83XX_DMAMR_DRCNT_32              (0xA << 24)
426
427#define MPC83XX_DMAMR_BWC_1                 (0 << 21)
428#define MPC83XX_DMAMR_BWC_2                 (1 << 21)
429#define MPC83XX_DMAMR_BWC_4                 (2 << 21)
430#define MPC83XX_DMAMR_BWC_8                 (3 << 21)
431#define MPC83XX_DMAMR_BWC_16                (4 << 21)
432
433#define MPC83XX_DMAMR_DMSEN                 (1 << 20)
434#define MPC83XX_DMAMR_IRQS                  (1 << 19)
435#define MPC83XX_DMAMR_EMSEN                 (1 << 18)
436
437#define MPC83XX_DMAMR_DAHTS_1               (0 << 16)
438#define MPC83XX_DMAMR_DAHTS_2               (1 << 16)
439#define MPC83XX_DMAMR_DAHTS_4               (2 << 16)
440#define MPC83XX_DMAMR_DAHTS_8               (3 << 16)
441
442#define MPC83XX_DMAMR_SAHTS_1               (0 << 14)
443#define MPC83XX_DMAMR_SAHTS_2               (1 << 14)
444#define MPC83XX_DMAMR_SAHTS_4               (2 << 14)
445#define MPC83XX_DMAMR_SAHTS_8               (3 << 14)
446
447#define MPC83XX_DMAMR_DAHE                  (1 << 13)
448#define MPC83XX_DMAMR_SAHE                  (1 << 12)
449
450#define MPC83XX_DMAMR_PRC_PCI_READ          (0 << 10)
451#define MPC83XX_DMAMR_PRC_PCI_READ_LINE     (1 << 10)
452#define MPC83XX_DMAMR_PRC_PCI_READ_MULTIPLE (2 << 10)
453
454#define MPC83XX_DMAMR_EOIIE                 (1 <<  7)
455#define MPC83XX_DMAMR_TEM                   (1 <<  3)
456#define MPC83XX_DMAMR_CTM                   (1 <<  2)
457#define MPC83XX_DMAMR_CC                    (1 <<  1)
458#define MPC83XX_DMAMR_CS                    (1 <<  0)
459
460/* DMA status register */
461#define MPC83XX_DMASR_TE                    (1 << 7)
462#define MPC83XX_DMASR_CB                    (1 << 2)
463#define MPC83XX_DMASR_EOSI                  (1 << 1)
464#define MPC83XX_DMASR_EOCDI                 (1 << 0)
465
466/* DMA current descriptor address register */
467#define MPC83XX_DMACDAR_SNEN                (1 << 4)
468#define MPC83XX_DMACDAR_EOSIE               (1 << 3)
469
470/* DMA next descriptor address register */
471#define MPC83XX_DMANDAR_NSNEN               (1 << 4)
472#define MPC83XX_DMANDAR_NEOSIE              (1 << 3)
473#define MPC83XX_DMANDAR_EOTD                (1 << 0)
474
475
476typedef struct m83xxPCICfgRegisters_ {
477  /* PCI1 Software Configuration Registers */
478  volatile uint32_t config_address;         /* 0x0_8300 PCI1 CONFIG_ADDRESS W  13.3.1.1/13-16 */
479  volatile uint32_t config_data;            /* 0x0_8304 PCI1 CONFIG_DATA R/W  13.3.1.2/13-18 */
480  volatile uint32_t int_ack;                /* 0x0_8308 PCI1 INT_ACK R  13.3.1.3/13-18 */
481  uint8_t reserved0_830C[0x08380-0x0830C];  /* 0x0_830C-0x0_837F Reserved */
482} m83xxPCICfgRegisters_t;
483
484typedef struct m83xxPCIIosRegisters_ {
485  /* Sequencer (IOS) */
486  volatile uint32_t potar0;               /* 0x0_8400 PCI outbound translation address register 0 R/W 0x0000_0000 11.4.1/11-3 */
487  uint8_t reserved0_8404[0x08408-0x08404];/* 0x0_8404 Reserved */
488  volatile uint32_t pobar0;               /* 0x0_8408 PCI outbound base address register 0 R/W 0x0000_0000 11.4.2/11-3 */
489  uint8_t reserved0_840C[0x08410-0x0840C];/* 0x0_840C Reserved */
490  volatile uint32_t pocmr0;               /* 0x0_8410 PCI outbound comparison mask register 0 R/W 0x0000_0000 11.4.3/11-4 */
491  uint8_t reserved0_8414[0x08418-0x08414];/* 0x0_8414 Reserved */
492  volatile uint32_t potar1;               /* 0x0_8418 PCI outbound translation address register 1 R/W 0x0000_0000 11.4.1/11-3 */
493  uint8_t reserved0_841C[0x08420-0x0841C];/* 0x0_841C Reserved */
494  volatile uint32_t pobar1;               /* 0x0_8420 PCI outbound base address register 1 R/W 0x0000_0000 11.4.2/11-3 */
495  uint8_t reserved0_8424[0x08428-0x08424];/* 0x0_8424 Reserved */
496  volatile uint32_t pocmr1;               /* 0x0_8428 PCI outbound comparison mask register 1 R/W 0x0000_0000 11.4.3/11-4 */
497  uint8_t reserved0_842C[0x08430-0x0842C];/* 0x0_842C Reserved */
498  volatile uint32_t potar2;               /* 0x0_8430 PCI outbound translation address register 2 R/W 0x0000_0000 11.4.1/11-3 */
499  uint8_t reserved0_8434[0x08438-0x08434];/* 0x0_8434 Reserved */
500  volatile uint32_t pobar2;               /* 0x0_8438 PCI outbound base address register 2 R/W 0x0000_0000 11.4.2/11-3 */
501  uint8_t reserved0_843C[0x08440-0x0843C];/* 0x0_843C Reserved */
502  volatile uint32_t pocmr2;               /* 0x0_8440 PCI outbound comparison mask register 2 R/W 0x0000_0000 11.4.3/11-4 */
503  uint8_t reserved0_8444[0x08448-0x08444];/* 0x0_8444 Reserved */
504  volatile uint32_t potar3;               /* 0x0_8448 PCI outbound translation address register 3 R/W 0x0000_0000 11.4.1/11-3 */
505  uint8_t reserved0_844C[0x08450-0x0844C];/* 0x0_844C Reserved */
506  volatile uint32_t pobar3;               /* 0x0_8450 PCI outbound base address register 3 R/W 0x0000_0000 11.4.2/11-3 */
507  uint8_t reserved0_8454[0x08458-0x08454];/* 0x0_8454 Reserved */
508  volatile uint32_t pocmr3;               /* 0x0_8458 PCI outbound comparison mask register 3 R/W 0x0000_0000 11.4.3/11-4 */
509  uint8_t reserved0_845C[0x08460-0x0845C];/* 0x0_845C Reserved */
510  volatile uint32_t potar4;               /* 0x0_8460 PCI outbound translation address register 4 R/W 0x0000_0000 11.4.1/11-3 */
511  uint8_t reserved0_8464[0x08468-0x08464];/* 0x0_8464 Reserved */
512  volatile uint32_t pobar4;               /* 0x0_8468 PCI outbound base address register 4 R/W 0x0000_0000 11.4.2/11-3 */
513  uint8_t reserved0_846C[0x08470-0x0846C];/* 0x0_846C Reserved */
514  volatile uint32_t pocmr4;               /* 0x0_8470 PCI outbound comparison mask register 4 R/W 0x0000_0000 11.4.3/11-4 */
515  uint8_t reserved0_8474[0x08478-0x08474];/* 0x0_8474 Reserved */
516  volatile uint32_t potar5;               /* 0x0_8478 PCI outbound translation address register 5 R/W 0x0000_0000 11.4.1/11-3 */
517  uint8_t reserved0_847C[0x08480-0x0847C];/* 0x0_847C Reserved */
518  volatile uint32_t pobar5;               /* 0x0_8480 PCI outbound base address register 5 R/W 0x0000_0000 11.4.2/11-3 */
519  uint8_t reserved0_8484[0x08488-0x08484];/* 0x0_8484 Reserved */
520  volatile uint32_t pocmr5;               /* 0x0_8488 PCI outbound comparison mask register 5 R/W 0x0000_0000 11.4.3/11-4 */
521  uint8_t reserved0_848C[0x084F0-0x0848C];/* 0x0_848C Reserved */
522  volatile uint32_t pmcr;                 /* 0x0_84F0 Power management control register R/W 0x0000_0000 11.4.4/11-5 */
523  uint8_t reserved0_84F4[0x084F8-0x084F4];/* 0x0_84F4 Reserved */
524  volatile uint32_t dtcr;                 /* 0x0_84F8 Discard timer control register R/W 0x0000_0000 11.4.5/11-6 */
525  uint8_t reserved0_84FC[0x08500-0x084FC];/* 0x0_84FC Reserved */
526} m83xxPCIIosRegisters_t;
527
528typedef struct m83xxPCICtrlRegisters_ {
529  /* PCI1 Error Management Registers */
530  volatile uint32_t pci_esr;              /* 0x0_8500 PCI error status register R / w1c 0x0000_0000 13.3.2.1/13-18 */
531  volatile uint32_t pci_ecdr;             /* 0x0_8504 PCI error capture disable register R/W 0x0000_0000 13.3.2.2/13-19 */
532  volatile uint32_t pci_eer;              /* 0x0_8508 PCI error enable register R/W 0x0000_0000 13.3.2.3/13-20 */
533  volatile uint32_t pci_eatcr;            /* 0x0_850C PCI error attributes capture register R/W 0x0000_0000 13.3.2.4/13-21 */
534  volatile uint32_t pci_eacr;             /* 0x0_8510 PCI error address capture register R 0x0000_0000 13.3.2.5/13-23 */
535  volatile uint32_t pci_eeacr;            /* 0x0_8514 PCI error extended address capture register R 0x0000_0000 13.3.2.6/13-23 */
536  volatile uint32_t pci_edlcr;            /* 0x0_8518 PCI error data low capture register R 0x0000_0000 13.3.2.7/13-24 */
537  volatile uint32_t pci_edhcr;            /* 0x0_851C PCI error data high capture register R 0x0000_0000 13.3.2.8/13-24 */
538  /* PCI1 Control and Status Registers */
539  volatile uint32_t pci_gcr;              /* 0x0_8520 PCI general control register R/W 0x0000_0000 13.3.2.9/13-24 */
540  volatile uint32_t pci_ecr;              /* 0x0_8524 PCI error control register R/W 0x0000_0000 13.3.2.10/13-25 */
541  volatile uint32_t pci_gsr;              /* 0x0_8528 PCI general status register R 0x0000_0000 13.3.2.11/13-26 */
542  uint8_t reserved0_852C[0x08538-0x0852C];/* 0x0_852C Reserved */
543  /* PCI1 Inbound ATU Registers */
544  volatile uint32_t pitar2;               /* 0x0_8538 PCI inbound translation address register 2 R/W 0x0000_0000 13.3.2.12/13-26 */
545  uint8_t reserved0_853C[0x08540-0x0853C];/* 0x0_853C Reserved, should be cleared  $ $ */
546  volatile uint32_t pibar2;               /* 0x0_8540 PCI inbound base address register 2 R/W 0x0000_0000 13.3.2.13/13-27 */
547  volatile uint32_t piebar2;              /* 0x0_8544 PCI inbound extended base address register 2 R/W 0x0000_0000 13.3.2.14/13-27 */
548  volatile uint32_t piwar2;               /* 0x0_8548 PCI inbound window attributes register 2 R/W 0x0000_0000 13.3.2.15/13-28 */
549  uint8_t reserved0_854C[0x08550-0x0854C];/* 0x0_854C Reserved */
550  volatile uint32_t pitar1;               /* 0x0_8550 PCI inbound translation address register 1 R/W 0x0000_0000 13.3.2.12/13-26 */
551  uint8_t reserved0_8550[0x08558-0x08554];/* 0x0_8554 Reserved, should be cleared  $ $ */
552  volatile uint32_t pibar1;               /* 0x0_8558 PCI inbound base address register 1 R/W 0x0000_0000 13.3.2.13/13-27 */
553  volatile uint32_t piebar1;              /* 0x0_855C PCI inbound extended base address register 1 R/W 0x0000_0000 13.3.2.14/13-27 */
554  volatile uint32_t piwar1;               /* 0x0_8560 PCI inbound window attributes register 1 R/W 0x0000_0000 13.3.2.15/13-28 */
555  uint8_t reserved0_8564[0x08568-0x08564];/* 0x0_8564 Reserved */
556  volatile uint32_t pitar0;               /* 0x0_8568 PCI inbound translation address register 0 R/W 0x0000_0000 13.3.2.12/13-26 */
557  uint8_t reserved0_856c[0x08570-0x0856c];/* 0x0_856C Reserved, should be cleared  $ $ */
558  volatile uint32_t pibar0;               /* 0x0_8570 PCI inbound base address register 0 R/W 0x0000_0000 13.3.2.13/13-27 */
559  uint8_t reserved0_8574[0x08578-0x08574];/* 0x0_8574 Reserved */
560  volatile uint32_t piwar0;               /* 0x0_8578 PCI inbound window attributes register 0 R/W 0x0000_0000 13.3.2.14/13-27 */
561  uint8_t reserved0_857c[0x08580-0x0857c];/* 0x0_857C Reserved, should be cleared  $ $ */
562  uint8_t reserved0_8580[0x08600-0x08580];/* 0x0_8580 Reserved */
563} m83xxPCICtrlRegisters_t;
564
565typedef struct m83xxUSB_MPHRegisters_ {
566  /* USB MPH Controller Registers */
567  uint8_t reserved0x2_2000[0x22100-0x22000]; /* 0x2_2000--0x2_20FF Reserved, should be cleared */
568  volatile uint16_t caplength;               /* 0x2_2100 Capability register length R 0x40 16.3.1.1/16-19 */
569  volatile uint16_t hciversion;              /* 0x2_2102 Host interface version number R 0x0100 16.3.1.2/16-19 */
570  volatile uint32_t hcsparams;               /* 0x2_2104 Host crtl. structural parameters R 0x0121_0012 16.3.1.3/16-20 */
571  volatile uint32_t hccparams;               /* 0x2_2108 Host crtl. capability parameters R 0x0000_0006 16.3.1.4/16-21 */
572  uint8_t reserved0x2_210C[0x22140-0x2210C]; /* Reserved  */
573  volatile uint32_t usbcmd;                  /* 0x2_2140 USB command R/W 0x0008_nBn0 16.3.2.1/16-23 */
574  volatile uint32_t usbsts;                  /* 0x2_2144 USB status R/W 0x0000_0000 16.3.2.2/16-26 */
575  volatile uint32_t usbintr;                 /* 0x2_2148 USB interrupt enable R/W 0x0000_0000 16.3.2.3/16-28 */
576  volatile uint32_t frindex;                 /* 0x2_214C USB frame index R/W 0x0000_nnnn 16.3.2.4/16-30 */
577  uint8_t reserved0x2_2150[0x22154-0x22150]; /* Reserved  */
578  volatile uint32_t periodiclistbase;        /* 0x2_2154 Frame list base address R/W 0xnnnn_0000 16.3.2.6/16-31 */
579  volatile uint32_t asynclistaddr;           /* 0x2_2158 Next asynchronous list addr R/W 0x0000_0000 16.3.2.8/16-32 */
580  volatile uint32_t asyncttsts;              /* 0x2_215C  Asynchronous buffer status for embedded TT TBD 0x0000_0000 16.3.2.10/16-34 */
581  volatile uint32_t burstsize;               /* 0x2_2160 Programmable burst size R/W 0x000_1010 16.3.2.11/16-34 */
582  volatile uint32_t txfilltuning;            /* 0x2_2164 Host TT transmit pre-buffer packet tuning R/W 0x0002_0000 16.3.2.12/16-35 */
583  volatile uint32_t txttfilltuning;          /* 0x2_2168 Host TT transmit pre-buffer packet tuning R/W 0x0000_0000 16.3.2.13/16-37 */
584  uint8_t reserved0x2_216c[0x22170-0x2216c]; /* Reserved  */
585  volatile uint32_t viewport;                /* 0x2_2170 ULPI ULPI Register Access R/W 0x0000_0000 16.3.2.14/16-37 */
586  uint8_t reserved0x2_2174[0x22180-0x22174]; /* Reserved  */
587  volatile uint32_t configflag;              /* 0x2_2180 Configured flag register R 0x0000_0001 16.3.2.15/16-39 */
588  volatile uint32_t portsc1;                 /* 0x2_2184 Port status/control 1 R/W 0x8C00_0001 16.3.2.16/16-39 */
589  volatile uint32_t portsc2;                 /* 0x2_2188 Port status/control 2 R/W 0x8C00_0001 16.3.2.16/16-39 */
590  uint8_t reserved0x2_218c[0x221A8-0x2218c]; /* Reserved  */
591  volatile uint32_t usbmode;                 /* 0x2_21A8 USB device mode R/W 0x0000_0003 16.3.2.18/16-47 */
592  uint8_t reserved0x2_21AC[0x22400-0x221AC]; /* Reserved  */
593  volatile uint32_t snoop1;                  /* 0x2_2400 Snoop 1 R/W 0x0000_0000 16.3.2.26/16-53 */
594  volatile uint32_t snoop2;                  /* 0x2_2404 Snoop 2 R/W 0x0000_0000 16.3.2.26/16-53 */
595  volatile uint32_t age_cnt_thresh;          /* 0x2_2408 Age count threshold R/W 0x0000_0000 16.3.2.27/16-54 */
596  volatile uint32_t si_ctrl;                 /* 0x2_240C System interface control R/W 0x0000_0000 16.3.2.28/16-56 */
597  volatile uint32_t pri_ctrl;                /* 0x2_2410 Priority control R/W 0x0000_0000 16.3.2.29/16-56 */
598  uint8_t reserved0x2_2414[0x22500-0x22414]; /* Reserved  */
599  volatile uint32_t control;                 /* 0x2_2500 Control R/W 0x0000_0000 16.3.2.30/16-57 */
600  uint8_t reserved0x2_2504[0x23000-0x22504]; /* 0x2_2504--0x2_2FFF Reserved, should be cleared */
601} m83xxUSB_MPHRegisters_t;
602
603typedef struct m83xxUSB_DRRegisters_ {
604  /* USB DR Controller Registers */
605  uint8_t reserved0x2_3000[0x23100-0x23000]; /* 0x2_3000--0x2_30FF Reserved, should be cleared */
606  volatile uint16_t caplength;               /* 0x2_3100 Capability register length R 0x40 16.3.1.1/16-19 */
607  volatile uint16_t hciversion;              /* 0x2_3102 Host interface version number R 0x0100 16.3.1.2/16-19 */
608  volatile uint32_t hcsparams;               /* 0x2_3104 Host crtl. structural parameters R 0x0111_0011 16.3.1.3/16-20 */
609  volatile uint32_t hccparams;               /* 0x2_3108 Host crtl. capability parameters R 0x0000_0006 16.3.1.4/16-21 */
610  uint8_t reserved0x2_310c[0x23120-0x2310C]; /* 0x2_310c--0x2_311f Reserved */
611  volatile uint32_t dciversion;              /* 0x2_3120 Device interface version number R 0x0001 16.3.1.5/16-22 */
612  volatile uint32_t dccparams;               /* 0x2_3124 Device controller parameters R 0x0000_0186 16.3.1.6/16-22 */
613  uint8_t reserved0x2_3128[0x23140-0x23128]; /* 0x2_3128--0x2_313f Reserved */
614  volatile uint32_t usbcmd;                  /* 0x2_3140 USB command R/W 0x0008_nBn0 16.3.2.1/16-23 */
615  volatile uint32_t usbsts;                  /* 0x2_3144 USB status R/W 0x0000_0000 16.3.2.2/16-26 */
616  volatile uint32_t usbintr;                 /* 0x2_3148 USB interrupt enable R/W 0x0000_0000 16.3.2.3/16-28 */
617  volatile uint32_t frindex;                 /* 0x2_314C USB frame index R/W 0x0000_nnnn 16.3.2.4/16-30 */
618  uint8_t reserved0x2_3150[0x23154-0x23150]; /* 0x2_3150--0x2_3153 Reserved */
619  union {
620    volatile uint32_t periodiclistbase;      /* 0x2_3154 Frame list base address R/W 0xnnnn_0000 16.3.2.6/16-31 */
621    volatile uint32_t deviceaddr;            /* 0x2_3154 USB device address R/W 0x0000_0000 16.3.2.7/16-32 */
622  } perbase_devaddr;
623  union {
624    volatile uint32_t asynclistaddr;         /* 0x2_3158 Next asynchronous list addr (host mode) R/W 0x0000_0000 16.3.2.8/16-32 */
625    volatile uint32_t addr;                  /* 0x2_3158 ENDPOINT Address at endpoint list (device mode) R/W 0x0000_0000 16.3.2.9/16-33 */
626  } async_addr;
627  uint8_t reserved0x2_315c[0x23160-0x2315c]; /* 0x2_315c--0x2_315f Reserved */
628  volatile uint32_t burstsize;               /* 0x2_3160 Programmable burst size R/W 0x0000_1010 16.3.2.11/16-34 */
629  volatile uint32_t txfilltuning;            /* 0x2_3164 Host TT transmit pre-buffer packet tuning R/W 0x0002_0000 16.3.2.12/16-35 */
630  uint8_t reserved0x2_3168[0x23170-0x23168]; /* 0x2_3168--0x2_316f Reserved */
631  volatile uint32_t viewport;                /* 0x2_3170 ULPI ULPI Register Access R/W 0x0000_0000 16.3.2.14/16-37 */
632  uint8_t reserved0x2_3174[0x23180-0x23174]; /* 0x2_3174--0x2_317F Reserved */
633  volatile uint32_t configflag;              /* 0x2_3180 Configured flag register R 0x0000_0001 16.3.2.15/16-39 */
634  volatile uint32_t portsc1;                 /* 0x2_3184 Port status/control R/W 0x9C00_0000 16.3.2.16/16-39 */
635  uint8_t reserved0x2_3188[0x231A4-0x23188]; /* 0x2_3188--0x2_31A3 Reserved */
636  volatile uint32_t otgsc;                   /* 0x2_31A4 On-the-Go status and control R/W 0x0000_0001 16.3.2.17/16-44 */
637  volatile uint32_t usbmode;                 /* 0x2_31A8 USB device mode R/W 0x0000_0000 16.3.2.18/16-47 */
638  volatile uint32_t endptsetupstat;          /* 0x2_31AC Endpoint setup status R/W 0x0000_0000 16.3.2.19/16-48 */
639  volatile uint32_t endpointprime;           /* 0x2_31B0 Endpoint initialization R/W 0x0000_0000 16.3.2.20/16-48 */
640  volatile uint32_t endptflush;              /* 0x2_31B4 Endpoint de-initialize R/W 0x0000_0000 16.3.2.21/16-49 */
641  volatile uint32_t endptstatus;             /* 0x2_31B8 Endpoint status R 0x0000_0000 16.3.2.22/16-50 */
642  volatile uint32_t endptcomplete;           /* 0x2_31BC Endpoint complete R/W 0x0000_0000 16.3.2.23/16-50 */
643  volatile uint32_t endptctrl[6];            /* 0x2_31C0 Endpoint control 0 R/W 0x0080_0080 16.3.2.24/16-51 */
644  uint8_t reserved0x2_31D8[0x23400-0x231D8]; /* 0x2_31D8--0x2_33ff Reserved */
645  volatile uint32_t snoop1;                  /* 0x2_3400 Snoop 1 R/W 0x0000_0000 16.3.2.26/16-53 */
646  volatile uint32_t snoop2;                  /* 0x2_3404 Snoop 2 R/W 0x0000_0000 16.3.2.26/16-53 */
647  volatile uint32_t age_cnt_thresh;          /* 0x2_3408 Age count threshold R/W 0x0000_0000 16.3.2.27/16-54 */
648  volatile uint32_t pri_ctrl;                /* 0x2_340C Priority control R/W 0x0000_0000 16.3.2.29/16-56 */
649  volatile uint32_t si_ctrl;                 /* 0x2_3410 System interface control R/W 0x0000_0000 16.3.2.28/16-56 */
650  uint8_t reserved0x2_3414[0x23500-0x23414]; /* 0x2_3414--0x2_34ff Reserved */
651  volatile uint32_t control;                 /* 0x2_3500 Control R/W 0x0000_0000 16.3.2.30/16-57 */
652  uint8_t reserved0x2_3504[0x24000-0x23504]; /* 0x2_3504--0x2_3FFF Reserved, should be cleared */
653} m83xxUSB_DRRegisters_t;
654
655#if 0 /* FIXME: to be formatted soon */
656  /* Security Engine Address Map Registers */
657  /* Controller Registers */
658  volatile uint32_t reserved;## /* 0x3_0000--0x3_0FFF Reserved, should be cleared */
659  volatile uint32_t imr; /* 0x3_1008 Interrupt mask register R/W 0x0000_0000_0000_0000 14.7.2.1/14-94 */
660  volatile uint32_t isr; /* 0x3_1010 Interrupt status register R 0x0000_0000_0000_0000 14.7.2.2/14-96 */
661  volatile uint32_t icr; /* 0x3_1018 Interrupt clear register W 0x0000_0000_0000_0000 14.7.2.3/14-96 */
662  volatile uint32_t id; /* 0x3_1020 Identification register R 0x0000_0000_0000_00400x 14.7.2.4/14-98 */
663  volatile uint32_t euasr; /* 0x3_1028 EU assignment status register R 0xF0F0_F0F0_00FF_F0F0 14.7.2/14-93 */
664  volatile uint32_t mcr; /* 0x3_1030 Master control register R/W 0000_0000_0000_0000 14.7.2.5/14-98 */
665  /* Channel 1 */
666  volatile uint32_t cccr1; /* 0x3_1108 Crypto-channel 1 configuration register R/W 0x0000_0000_0000_0000 14.6.1.1/14-82 */
667  volatile uint32_t ccpsr1; /* 0x3_1110 Crypto-channel 1 pointer status register R 0x0000_0000_0000_0007 14.6.1.2/14-85 */
668  volatile uint32_t cdpr1; /* 0x3_1140 Crypto-channel 1 current descriptor pointer register R 0x0000_0000_0000_0000 14.6.1.3/14-90 */
669  volatile uint32_t */
6700x3_1180--0x3_11BF
671  DBn /*   volatile; uint32_t ff1, /* 0x3_1148 Crypto-channel 1 fetch FIFO address register W 0x0000_0000_0000_0000 14.6.1.4/14-90 Crypto-channel 1 descriptor buffers [0–7] R 0x0000_0000_0000_0000 14.6.1.5/14-91 */
672  /* Channel 2-4: FIXME: same layout as channel 1*/
673  /* Data Encryption Standard Execution Unit (DEU) */
674  volatile uint32_t deumr; /* 0x3_2000 DEU mode register R/W 0x0000_0000_0000_0000 14.5.2.1/14-35 */
675  volatile uint32_t deuksr; /* 0x3_2008 DEU key size register R/W 0x0000_0000_0000_0000 14.5.2.2/14-36 */
676  volatile uint32_t deudsr; /* 0x3_2010 DEU data size register R/W 0x0000_0000_0000_0000 14.5.2.3/14-36 */
677  volatile uint32_t deurcr; /* 0x3_2018 DEU reset control register R/W 0x0000_0000_0000_0000 14.5.2.4/14-37 */
678  volatile uint32_t deusr; /* 0x3_2028 DEU status register R 0x0000_0000_0000_0000 14.5.2.5/14-37 */
679  volatile uint32_t deuisr; /* 0x3_2030 DEU interrupt status register R 0x0000_0000_0000_0000 14.5.2.6/14-38 */
680  volatile uint32_t deuicr; /* 0x3_2038 DEU interrupt control register R/W 0x0000_0000_0000_3000 14.5.2.7/14-40 */
681  volatile uint32_t deueug; /* 0x3_2050 DEU EU-Go register W 0x0000_0000_0000_0000 14.5.2.8/14-41 */
682  volatile uint32_t deuiv; /* 0x3_2100 DEU initialization vector register R/W 0x0000_0000_0000_0000 14.5.2.9/14-42 */
683  volatile uint32_t deuk1; /* 0x3_2400 DEU key 1 register W $ 14.5.2.10/14-42 */
684  volatile uint32_t deuk2; /* 0x3_2408 DEU key 2 register W $ 14.5.2.10/14-42 */
685  volatile uint32_t deuk3; /* 0x3_2410 DEU key 3 register W $ 14.5.2.10/14-42 */
6860x3_2800--0x3_2FFF
687DEU FIFO R/W 0x0000_0000_0000_0000 14.5.2.11/14-42
688  /* Advanced Encryption Standard Execution Unit (AESU) */
689  volatile uint32_t aesumr; /* 0x3_4000 AESU mode register R/W 0x0000_0000_0000_0000 14.5.6.1/14-68 */
690  volatile uint32_t aesuksr; /* 0x3_4008 AESU key size register R/W 0x0000_0000_0000_0000 14.5.6.2/14-71 */
691  volatile uint32_t aesudsr; /* 0x3_4010 AESU data size register R/W 0x0000_0000_0000_0000 14.5.6.3/14-71 */
692  volatile uint32_t aesurcr; /* 0x3_4018 AESU reset control register R/W 0x0000_0000_0000_0000 14.5.6.4/14-72 */
693  volatile uint32_t aesusr; /* 0x3_4028 AESU status register R 0x0000_0000_0000_0000 14.5.6.5/14-73 */
694  volatile uint32_t aesuisr; /* 0x3_4030 AESU interrupt status register R 0x0000_0000_0000_0000 14.5.6.6/14-74 */
695  volatile uint32_t aesuicr; /* 0x3_4038 AESU interrupt control register R/W 0x0000_0000_0000_1000 14.5.6.7/14-75 */
696  volatile uint32_t aesuemr; /* 0x3_4050 AESU end-of-message register W 0x0000_0000_0000_0000 14.5.6.8/14-76 */
6970x3_4100 AESU context memory registers R/W 0x0000_0000_0000_0000 14.5.6.9/14-77
6980x3_4400--0x3_4408
699AESU key memory R/W 0x0000_0000_0000_0000 14.5.6.9.5/14-81
7000x3_4800--0x3_4FFF
701AESU FIFO R/W 0x0000_0000_0000_0000 14.5.6.9.6/14-81
702  /* Message Digest Execution Unit (MDEU) */
703  volatile uint32_t mdeumr; /* 0x3_6000 MDEU mode register R/W 0x0000_0000_0000_0000 14.5.4.1/14-51 */
704  volatile uint32_t mdeuksr; /* 0x3_6008 MDEU key size register R/W 0x0000_0000_0000_0000 14.5.4.3/14-55 */
705  volatile uint32_t mdeudsr; /* 0x3_6010 MDEU data size register R/W 0x0000_0000_0000_0000 14.5.4.4/14-56 */
706  volatile uint32_t mdeurcr; /* 0x3_6018 MDEU reset control register R/W 0x0000_0000_0000_0000 14.5.4.5/14-56 */
707  volatile uint32_t mdeusr; /* 0x3_6028 MDEU status register R 0x0000_0000_0000_0000 14.5.4.6/14-57 */
708  volatile uint32_t mdeuisr; /* 0x3_6030 MDEU interrupt status register R 0x0000_0000_0000_0000 14.5.4.7/14-58 */
709  volatile uint32_t mdeuicr; /* 0x3_6038 MDEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.4.8/14-59 */
710  volatile uint32_t mdeueug; /* 0x3_6050 MDEU EU-Go register W 0x0000_0000_0000_0000 14.5.4.10/14-61 */
7110x3_6100--0x3_6120
712MDEU context memory registers R/W 0x0000_0000_0000_0000 14.5.4.11/14-61
7130x3_6400--0x3_647F
714MDEU key memory W 0x0000_0000_0000_0000 14.5.4.12/14-62
7150x3_6800--0x3_6FFF
716MDEU FIFO W 0x0000_0000_0000_0000 14.5.4.13/14-63
717  /* ARC Four Execution Unit (AFEU) */
718  volatile uint32_t afeumr; /* 0x3_8000 AFEU mode register R/W 0x0000_0000_0000_0000 14.5.3.1/14-43 */
719  volatile uint32_t afeuksr; /* 0x3_8008 AFEU key size register R/W 0x0000_0000_0000_0000 14.5.3.3/14-44 */
720  volatile uint32_t afeudsr; /* 0x3_8010 AFEU data size register R/W 0x0000_0000_0000_0000 14.5.3.4/14-45 */
721  volatile uint32_t afeurcr; /* 0x3_8018 AFEU reset control register R/W 0x0000_0000_0000_0000 14.5.3.5/14-46 */
722  volatile uint32_t afeusr; /* 0x3_8028 AFEU status register R 0x0000_0000_0000_0000 14.5.3.6/14-46 */
723  volatile uint32_t afeuisr; /* 0x3_8030 AFEU interrupt status register R 0x0000_0000_0000_0000 14.5.3.7/14-47 */
724  volatile uint32_t afeuicr; /* 0x3_8038 AFEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.3.8/14-49 */
725  volatile uint32_t afeuemr; /* 0x3_8050 AFEU end of message register W 0x0000_0000_0000_0000 14.5.3.9/14-50 */
7260x3_8100--0x3_81FF
727AFEU context memory registers R/W 0x0000_0000_0000_0000 14.5.3.10.1/14-50
7280x3_8200 AFEU context memory pointers R/W 0x0000_0000_0000_0000 14.5.3.10.2/14-51
729  volatile uint32_t afeuk0; /* 0x3_8400 AFEU key register 0 W $ 14.5.3.11/14-51 */
730  volatile uint32_t afeuk1; /* 0x3_848 AFEU key register 1 W $ 14.5.3.11/14-51 */
7310x3_8800--0x3_8FFF
732AFEU FIFO R/W 0x0000_0000_0000_0000 14.5.3.11.1/14-51
733  /* Random Number Generator (RNG) */
734  volatile uint32_t rngmr; /* 0x3_A000 RNG mode register R/W 0x0000_0000_0000_0000 14.5.5.1/14-63 */
735  volatile uint32_t rngdsr; /* 0x3_A010 RNG data size register R/W 0x0000_0000_0000_0000 14.5.5.2/14-64 */
736  volatile uint32_t rngrcr; /* 0x3_A018 RNG reset control register R/W 0x0000_0000_0000_0000 14.5.5.3/14-65 */
737  volatile uint32_t rngsr; /* 0x3_A028 RNG status register R 0x0000_0000_0000_0000 14.5.5.4/14-65 */
738  volatile uint32_t rngisr; /* 0x3_A030 RNG interrupt status register R 0x0000_0000 */
739_0000_0000
74014.5.5.5/14-66
741  volatile uint32_t rngicr; /* 0x3_A038 RNG interrupt control register R/W 0x0000_0000 */
742_0000_1000
74314.5.5.6/14-67
744  volatile uint32_t rngeug; /* 0x3_A050 RNG EU-Go register W 0x0000_0000 */
745_0000_0000
74614.5.5.7/14-68
7470x3_A800--0x3_AFFF
748RNG FIFO R 0x0000_0000
749_0000_0000
75014.5.5.8/14-68
751  /* Public Key Execution Unit (PKEU) */
752  volatile uint32_t pkeumr; /* 0x3_C000 PKEU mode register R/W 0x0000_0000_0000_0000 14.5.1.1/14-26 */
753  volatile uint32_t pkeuksr; /* 0x3_C008 PKEU key size register R/W 0x0000_0000_0000_0000 14.5.1.2/14-28 */
754  volatile uint32_t pkeudsr; /* 0x3_C010 PKEU data size register R/W 0x0000_0000_0000_0000 14.5.1.3/14-28 */
755  volatile uint32_t pkeurcr; /* 0x3_C018 PKEU reset control register R/W 0x0000_0000_0000_0000 14.5.1.5/14-29 */
756  volatile uint32_t pkeusr; /* 0x3_C028 PKEU status register R 0x0000_0000_0000_0000 14.5.1.6/14-30 */
757  volatile uint32_t pkeuisr; /* 0x3_C030 PKEU interrupt status register R 0x0000_0000_0000_0000 14.5.1.7/14-31 */
758  volatile uint32_t pkeuicr; /* 0x3_C038 PKEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.1.8/14-32 */
759  volatile uint32_t pkeuabs; /* 0x3_C040 PKEU AB size register R/W 0x0000_0000_0000_0000 14.5.1.3/14-28 */
760  volatile uint32_t pkeueug; /* 0x3_C050 PKEU EU-Go W 0x0000_0000_0000_0000 14.5.1.9/14-33 */
7610x3_C200--0x3_C23F
762PKEU parameter memory A0 R/W 0x0000_0000_0000_0000 14.5.1.10/14-34
7630x3_C240--0x3_C27F
764PKEU parameter memory A1 R/W 0x0000_0000_0000_0000
7650x3_C280--0x3_C2BF
766PKEU parameter memory A2 R/W 0x0000_0000_0000_0000
7670x3_C2C0--0x3_C2FF
768PKEU parameter memory A3 R/W 0x0000_0000_0000_0000
7690x3_C300--0x3_C33F
770PKEU parameter memory B0 R/W 0x0000_0000_0000_0000
7710x3_C340--0x3_C37F
772PKEU parameter memory B1 R/W 0x0000_0000_0000_0000
7730x3_C380--0x3_C3BF
774PKEU parameter memory B2 R/W 0x0000_0000_0000_0000
7750x3_C3C0--0x3_C3FF
776PKEU parameter memory B3 R/W 0x0000_0000_0000_0000
7770x3_C400--0x3_C4FF
778PKEU parameter memory E W 0x0000_0000_0000_0000
7790x3_C800--0x3_C8FF
780PKEU parameter memory N R/W 0x0000_0000_0000_0000
781#endif
782
783typedef struct m83xxRegisters_ {
784  m83xxSysConRegisters_t  syscon;
785  m83xxWDTRegisters_t     wdt;
786  uint8_t                 reserved0_0210[0x0300-0x0210];
787  m83xxRTCRegisters_t     rtc;
788  uint8_t                 reserved0_0320[0x0400-0x0320];
789  m83xxPITRegisters_t     pit;
790  m83xxGTMRegisters_t     gtm[M83xxGTModCnt];
791  m83xxIPICRegisters_t    ipic;
792  m83xxARBRegisters_t     arb;
793  m83xxRESRegisters_t     res;
794  m83xxCLKRegisters_t     clk;
795  m83xxPMCRegisters_t     pmc;
796  m83xxGPIORegisters_t    gpio[2];
797  uint8_t                 reserved0_0E00[0x1000-0x0E00];
798  m83xxDLLRegisters_t     dll;
799  uint8_t                 reserved0_1200[0x2000-0x1200];
800  m83xxDDRRegisters_t     ddr;
801  uint8_t                 reserved0_2F00[0x3000-0x2F00];
802  m83xxI2CRegisters_t     i2c[2];
803  uint8_t                 reserved0_3200[0x4000-0x3200];
804  uint8_t                 reserved0_4000[0x4500-0x4000];
805  m83xxDUARTRegisters_t   duart[2];
806  uint8_t                 reserved0_4700[0x5000-0x4700];
807  m83xxLBCRegisters_t     lbc;
808  uint8_t                 reserved0_5100[0x7000-0x5100];
809  m83xxSPIRegisters_t     spi;
810  uint8_t                 reserved0_7100[0x8000-0x7100];
811  m83xxDMARegisters_t     dma;
812  m83xxPCICfgRegisters_t  pcicfg[2];
813  m83xxPCIIosRegisters_t  pciios;
814  m83xxPCICtrlRegisters_t pcictrl[2];
815  uint8_t                 reserved0_8700[0x22000-0x8700];
816  m83xxUSB_MPHRegisters_t usb_mph;
817  m83xxUSB_DRRegisters_t  usb_dr;
818  volatile tsec_registers tsec[TSEC_COUNT];
819} m83xxRegisters_t;
820
821extern m83xxRegisters_t mpc83xx;
822
823static inline void mpc83xx_reset(void)
824{
825  _ISR_Set_level( 0 );
826
827  /* Set Reset Protection Register (RPR) to "RSTE" */
828  mpc83xx.res.rpr = 0x52535445;
829
830  /*
831   * Wait for Control Register Enabled in the
832   * Reset Control Enable Register (RCER).
833   */
834  while (mpc83xx.res.rcer != 0x00000001) {
835    /* Wait */
836  }
837
838  /* Set Software Hard Reset in the Reset Control Register (RCR) */
839  mpc83xx.res.rcr = 0x00000002;
840}
841
842#endif /* !defined ASM */
843/*
844 * some definitions used in assembler startup
845 */
846/*
847 * default address of IMMRBAR
848 */
849#define IMMRBAR_DEFAULT 0xFF400000
850/*
851 * offsets of some registers
852 */
853#define LBLAWBAR0_OFF  0x00020
854#define LBLAWAR0_OFF   0x00024
855#define LBLAWBAR1_OFF  0x00028
856#define LBLAWAR1_OFF   0x0002C
857#define LBLAWBAR2_OFF  0x00030
858#define LBLAWAR2_OFF   0x00034
859#define LBLAWBAR3_OFF  0x00038
860#define LBLAWAR3_OFF   0x0003C
861#define PCILAWBAR0_OFF 0x00060
862#define PCILAWAR0_OFF  0x00064
863#define PCILAWBAR1_OFF 0x00068
864#define PCILAWAR1_OFF  0x0006C
865#define DDRLAWBAR0_OFF 0x000A0
866#define DDRLAWAR0_OFF  0x000A4
867#define DDRLAWBAR1_OFF 0x000A8
868#define DDRLAWAR1_OFF  0x000AC
869
870#define BR0_OFF  0x05000
871#define OR0_OFF  0x05004
872#define BR1_OFF  0x05008
873#define OR1_OFF  0x0500C
874#define BR2_OFF  0x05010
875#define OR2_OFF  0x05014
876#define BR3_OFF  0x05018
877#define OR3_OFF  0x0501C
878#define BR4_OFF  0x05020
879#define OR4_OFF  0x05024
880#define BR5_OFF  0x05028
881#define OR5_OFF  0x0502C
882#define BR6_OFF  0x05030
883#define OR6_OFF  0x05034
884#define BR7_OFF  0x05038
885#define OR7_OFF  0x0503C
886
887#define MRPTR_OFF                    0x05084
888#define LSDMR_OFF                    0x05094
889#define LSRT_OFF                     0x050A4
890#define LCRR_OFF                     0x050d4
891
892
893#define CS0_BNDS_OFF       0x02000
894#define CS1_BNDS_OFF       0x02008
895#define CS2_BNDS_OFF       0x02010
896#define CS3_BNDS_OFF       0x02018
897#define CS0_CONFIG_OFF     0x02080
898#define CS1_CONFIG_OFF     0x02084
899#define CS2_CONFIG_OFF     0x02088
900#define CS3_CONFIG_OFF     0x0208C
901#define TIMING_CFG_3_OFF   0x02100
902#define TIMING_CFG_0_OFF   0x02104
903#define TIMING_CFG_1_OFF   0x02108
904#define TIMING_CFG_2_OFF   0x0210C
905#define DDR_SDRAM_CFG_OFF            0x02110
906#define DDR_SDRAM_CFG_2_OFF          0x02114
907#define DDR_SDRAM_MODE_OFF           0x02118
908#define DDR_SDRAM_MODE_2_OFF         0x0211C
909#define DDR_SDRAM_MD_CNTL_OFF        0x02120
910#define DDR_SDRAM_INTERVAL_OFF       0x02124
911#define DDR_SDRAM_DATA_INIT_OFF      0x02128
912#define DDRCDR_OFF                   0x0012C
913#define DDR_SDRAM_CLK_CNTL_OFF       0x02130
914#define DDR_SDRAM_INIT_ADDR_OFF      0x02148
915#define DDR_ERR_DISABLE_OFF          0x02E44
916
917/*
918 * some bits in DDR_SDRAM_CFG register
919 */
920#define DDR_SDRAM_CFG_MEM_EN (1 << (31- 0))     /* enable memory        */
921/*
922 * bits in DDR_SDRAM_CFG_2 register
923 */
924#define DDR_SDRAM_CFG_2_D_FRC_SR (1 << (31- 0)) /* force self refresh        */
925#define DDR_SDRAM_CFG_2_D_SR_IE  (1 << (31- 1)) /* self refresh interrupt en */
926#define DDR_SDRAM_CFG_2_D_DLL_RST_DIS  (1 << (31- 2)) /* DLL reset disable   */
927#define DDR_SDRAM_CFG_2_D_DQS_CFG_DIF  (1 << (31- 5)) /* use diff. DQS       */
928#define DDR_SDRAM_CFG_2_D_INIT   (1 << (31-27)) /* Init DRAM with pattern    */
929
930/*
931 * bits in reset configuration words/registers
932 */
933                                           /* Local bus clocking mode */
934#define RCWLR_LBIUCM_1_1 (0 << (31- 0))    /* 1:1 */
935#define RCWLR_LBIUCM_2_1 (1 << (31- 0))    /* 2:1 */
936                                           /* DDR clocking mode      */
937#define RCWLR_DDRCM_1_1  (0 << (31- 1))    /* 1:1 */
938#define RCWLR_DDRCM_2_1  (1 << (31- 1))    /* 2:1 */
939                                          /* System PLL mult. factor */
940#define RCWLR_SPMF(n) (((n)&0xf)<<(31- 7))
941                                          /* Core PLL mult. factor   */
942#define RCWLR_COREPLL(n) (((n)&0xff)<<(31-15))
943
944/* for MPC8309: */
945#define RCWLR_CEVCOD_1_8 (2<<(31-25))     /* QUICC internal PLL divider 1:8 */
946#define RCWLR_CEVCOD_1_4 (1<<(31-25))     /* QUICC internal PLL divider 1:4 */
947#define RCWLR_CEVCOD_1_2 (0<<(31-25))     /* QUICC internal PLL divider 1:2 */
948                                          /* QUICC Engine PLL mult. factor */
949#define RCWLR_CEPDF_2     (1<<(31-26))    /* QUICC Engine divide PLL out by 2*/
950                                          /* QUICC Engine PLL mult. factor */
951#define RCWLR_CEPMF(n) (((n)&0x1f)<<(31-31))
952
953                                           /* PCI host mode          */
954#define RCWHR_PCI_AGENT  (0 << (31- 0))    /* agent mode             */
955#define RCWHR_PCI_HOST   (1 << (31- 0))    /* host mode              */
956
957#define RCWHR_PCI_32     (0 << (31- 1))    /* PCI bus width 32 bit   */
958#define RCWHR_PCI_64     (1 << (31- 1))    /* PCI bus width 64 bit   */
959
960#define RCWHR_PCI1ARB_DIS (0 << (31- 2))   /* PCI1 arbiter disabled */
961#define RCWHR_PCI1ARB_EN  (1 << (31- 2))   /* PCI1 arbiter enabled  */
962#define RCWHR_PCI2ARB_DIS (0 << (31- 3))   /* PCI2 arbiter disabled */
963#define RCWHR_PCI2ARB_EN  (1 << (31- 3))   /* PCI2 arbiter enabled  */
964
965#define RCWHR_CORE_DIS    (1 << (31- 4))   /* CPU core disabled     */
966#define RCWHR_CORE_EN     (0 << (31- 4))   /* CPU core enabled      */
967
968#define RCWHR_BMS_LOW     (0 << (31- 5))   /* Boot from low addr  0x00000100 */
969#define RCWHR_BMS_HIGH    (1 << (31- 5))   /* Boot from high addr 0xFFF00100 */
970
971#define RCWHR_BOOTSEQ_NONE (0 <<(31- 7))   /* Bootsequencer off              */
972#define RCWHR_BOOTSEQ_NORM (1 <<(31- 7))   /* Bootsequencer normal I2C       */
973#define RCWHR_BOOTSEQ_EXTD (2 <<(31- 7))   /* Bootsequencer extended I2C     */
974#define RCWHR_BOOTSEQ_RSRV (3 <<(31- 7))   /* Bootsequencer reserved         */
975
976#define RCWHR_SW_DIS      (0 << (31- 8))   /* Watchdog disabled     */
977#define RCWHR_SW_EN       (1 << (31- 8))   /* Watchdog enabled      */
978
979#define RCWHR_ROMLOC_DDR  (0 << (31-11))   /* Initial ROM location:DDR Ram   */
980#define RCWHR_ROMLOC_PCI1 (1 << (31-11))   /* Initial ROM location:PCI 1     */
981#define RCWHR_ROMLOC_PCI2 (2 << (31-11))   /* Initial ROM location:PCI 2     */
982#define RCWHR_ROMLOC_RSV1 (3 << (31-11))   /* Initial ROM location:Reserved  */
983#define RCWHR_ROMLOC_RSV2 (4 << (31-11))   /* Initial ROM location:Reserved  */
984#define RCWHR_ROMLOC_LB08 (5 << (31-11))   /* Initial ROM location:LBus  8bit*/
985#define RCWHR_ROMLOC_LB16 (6 << (31-11))   /* Initial ROM location:LBus 16bit*/
986#define RCWHR_ROMLOC_LB32 (7 << (31-11))   /* Initial ROM location:LBus 32bit*/
987
988#define RCWHR_TSEC1M_RGMII (0 << (31-17))  /* TSEC1 Mode: RGMII  */
989#define RCWHR_TSEC1M_RTBI  (1 << (31-17))  /* TSEC1 Mode: RTBI   */
990#define RCWHR_TSEC1M_GMII  (2 << (31-17))  /* TSEC1 Mode: GMII   */
991#define RCWHR_TSEC1M_TBI   (3 << (31-17))  /* TSEC1 Mode: TBI    */
992
993#define RCWHR_TSEC2M_RGMII (0 << (31-19))  /* TSEC2 Mode: RGMII  */
994#define RCWHR_TSEC2M_RTBI  (1 << (31-19))  /* TSEC2 Mode: RTBI   */
995#define RCWHR_TSEC2M_GMII  (2 << (31-19))  /* TSEC2 Mode: GMII   */
996#define RCWHR_TSEC2M_TBI   (3 << (31-19))  /* TSEC2 Mode: TBI    */
997
998#define RCWHR_ENDIAN_BIG  (0 << (31-28))   /* Big Endian Mode         */
999#define RCWHR_ENDIAN_LIT  (1 << (31-28))   /* True Little Endian Mode */
1000
1001#define RCWHR_LALE_NORM   (0 << (31-29))   /* normal LALE timing      */
1002#define RCWHR_LALE_EARLY  (1 << (31-29))   /* early LALE negation     */
1003
1004#define RCWHR_LDP_PAR     (0 << (31-30))   /* LDP0-3 are parity pins  */
1005#define RCWHR_LDP_SPC     (1 << (31-30))   /* LDP0-3 are special pins */
1006
1007/*
1008 * For MPC8309:
1009 */
1010#define RCWHR_RLEXT_LGCY  (0 << (31-13))  /* Boot ROM loc. extension: Legacy */
1011#define RCWHR_RLEXT_NAND  (1 << (31-13))  /* Boot ROM loc. extension: NAND Fl.*/
1012#define RCWHR_RLEXT_RSV2  (2 << (31-13))  /* Boot ROM loc. extension: resrvd */
1013#define RCWHR_RLEXT_RSV3  (3 << (31-13))  /* Boot ROM loc. extension: resrvd */
1014#endif /* _MPC83XX_MPC83XX_H */
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