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mpc8260.h @ abc2164

Last change on this file since abc2164 was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

The make preinstall step itself needs time and disk space.

Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.

There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.

The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.

An introduction of a new build system is difficult.

Include paths specified by the -B option are system headers. This may suppress warnings.

The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

cpukit/include

cpukit/score/cpu/@RTEMS_CPU@/include

cpukit/libnetworking

The new BSP include directories are:

bsps/include

bsps/@RTEMS_CPU@/include

bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

Property mode set to 100644

File size: 51.9 KB

Line
1	/* buggy version of CPU */
2	#define REV_0_2
3
4	/*
5	**************************************************************************
6	**************************************************************************
7
8	MOTOROLA MPC8260 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER
9	POWERQUICC II
10
11	HARDWARE DECLARATIONS
12
13
14	Submitted by:
15	Andy Dachs **
16	Surrey Satellite Technology Limited **
17	http://www.sstl.co.uk **
18	a.dachs@sstl.co.uk **
19
20	Based on previous submissions for other PPC variants by:
21
22	Submitted By:
23
24	W. Eric Norum
25	Saskatchewan Accelerator Laboratory
26	University of Saskatchewan
27	107 North Road
28	Saskatoon, Saskatchewan, CANADA
29	S7N 5C6
30
31	eric@skatter.usask.ca
32
33	Modified for use with the MPC860 (original code was for MC68360)
34	by
35	Jay Monkman
36	Frasca International, Inc.
37	906 E. Airport Rd.
38	Urbana, IL, 61801
39
40	jmonkman@frasca.com
41
42
43	**************************************************************************
44	**************************************************************************
45	*/
46
47	#ifndef _MPC8260_H
48	#define _MPC8260_H
49
50	#ifndef ASM
51	/*
52	Macros for SPRs
53	*/
54
55
56
57
58	/*
59	*************************************************************************
60	* REGISTER SUBBLOCKS *
61	*************************************************************************
62	*/
63
64
65	/*
66	* Memory controller registers
67	*/
68	typedef struct m8260MEMCRegisters_ {
69	uint32_t br;
70	uint32_t _or; /* or is a C++ keyword :( */
71	} m8260MEMCRegisters_t;
72
73
74	/*
75	* Fast Communication Controller Registers
76	*/
77	typedef struct m8260FCCRegisters_ {
78	uint32_t gfmr;
79	uint32_t fpsmr;
80	uint16_t ftodr;
81	uint8_t fcc_pad0[2];
82	uint16_t fdsr;
83	uint8_t fcc_pad1[2];
84	uint32_t fcce;
85	uint32_t fccm;
86	uint8_t fccs;
87	uint8_t fcc_pad2[3];
88	uint8_t ftirr_phy0; /* n/a on FCC3 */
89	uint8_t ftirr_phy1; /* n/a on FCC3 */
90	uint8_t ftirr_phy2; /* n/a on FCC3 */
91	uint8_t ftirr_phy3; /* n/a on FCC3 */
92	} m8260FCCRegisters_t;
93
94
95	/*
96	* Serial Communications Controller registers
97	*/
98	typedef struct m8260SCCRegisters_ {
99	uint32_t gsmr_l;
100	uint32_t gsmr_h;
101	uint16_t psmr;
102	uint8_t scc_pad0[2];
103	uint16_t todr;
104	uint16_t dsr;
105	uint16_t scce;
106	uint8_t scc_pad2[2];
107	uint16_t sccm;
108	uint8_t scc_pad3[1];
109	uint8_t sccs;
110	uint8_t scc_pad1[8];
111	} m8260SCCRegisters_t;
112
113	/*
114	* Serial Management Controller registers
115	*/
116	typedef struct m8260SMCRegisters_ {
117	uint8_t smc_pad0[2];
118	uint16_t smcmr;
119	uint8_t smc_pad2[2];
120	uint8_t smce;
121	uint8_t smc_pad3[3];
122	uint8_t smcm;
123	uint8_t smc_pad1[5];
124	} m8260SMCRegisters_t;
125
126
127	/*
128	* Serial Interface With Time Slot Assigner Registers
129	*/
130	typedef struct m8260SIRegisters_ {
131	uint16_t siamr;
132	uint16_t sibmr;
133	uint16_t sicmr;
134	uint16_t sidmr;
135	uint8_t sigmr;
136	uint8_t si_pad0[1];
137	uint8_t sicmdr;
138	uint8_t si_pad1[1];
139	uint8_t sistr;
140	uint8_t si_pad2[1];
141	uint16_t sirsr;
142	} m8260SIRegisters_t;
143
144
145	/*
146	* Multi Channel Controller registers
147	*/
148	typedef struct m8260MCCRegisters_ {
149	uint16_t mcce;
150	uint8_t mcc_pad2[2];
151	uint16_t mccm;
152	uint16_t mcc_pad0;
153	uint8_t mccf;
154	uint8_t mcc_pad1[7];
155	} m8260MCCRegisters_t;
156
157
158	/*
159	*************************************************************************
160	* RISC Timers *
161	*************************************************************************
162	*/
163	/*
164	typedef struct m8260TimerParms_ {
165	uint16_t tm_base;
166	uint16_t _tm_ptr;
167	uint16_t _r_tmr;
168	uint16_t _r_tmv;
169	uint32_t tm_cmd;
170	uint32_t tm_cnt;
171	} m8260TimerParms_t;
172	*/
173
174	/*
175	* RISC Controller Configuration Register (RCCR)
176	* All other bits in this register are reserved.
177	*/
178	#define M8260_RCCR_TIME (1<<31) /* Enable timer */
179	#define M8260_RCCR_TIMEP(x) ((x)<<24) /* Timer period */
180	#define M8260_RCCR_DR1M (1<<23) /* IDMA Rqst 1 Mode */
181	#define M8260_RCCR_DR2M (1<<22) /* IDMA Rqst 2 Mode */
182	#define M8260_RCCR_DR1QP(x) ((x)<<20) /* IDMA1 Rqst Priority */
183	#define M8260_RCCR_EIE (1<<19) /* External Interrupt Enable */
184	#define M8260_RCCR_SCD (1<<18) /* Scheduler Configuration */
185	#define M8260_RCCR_DR2QP(x) ((x)<<16) /* IDMA2 Rqst Priority */
186	#define M8260_RCCR_ERAM(x) ((x)<<13) /* Enable RAM Microcode */
187	#define M8260_RCCR_EDM1 (1<<11) /* DRQ1 Edge detect mode */
188	#define M8260_RCCR_EDM2 (1<<10) /* DRQ2 Edge detect mode */
189	#define M8260_RCCR_EDM3 (1<<9) /* DRQ3 Edge detect mode */
190	#define M8260_RCCR_EDM4 (1<<8) /* DRQ4 Edge detect mode */
191	#define M8260_RCCR_DR3M (1<<7) /* IDMA Rqst 1 Mode */
192	#define M8260_RCCR_DR4M (1<<6) /* IDMA Rqst 2 Mode */
193	#define M8260_RCCR_DR3QP(x) ((x)<<4) /* IDMA3 Rqst Priority */
194	#define M8260_RCCR_DEM12 (1<<3) /* DONE1,2 Edge detect mode */
195	#define M8260_RCCR_DEM34 (1<<2) /* DONE3,4 Edge detect mode */
196	#define M8260_RCCR_DR4QP(x) (x) /* IDMA4 Rqst Priority */
197
198
199
200	/*
201	* Command register
202	* Set up this register before issuing a M8260_CR_OP_SET_TIMER command.
203	*/
204	#if 0
205	#define M8260_TM_CMD_V (1<<31) /* Set to enable timer */
206	#define M8260_TM_CMD_R (1<<30) /* Set for automatic restart */
207	#define M8260_TM_CMD_PWM (1<<29) /* Set for PWM operation */
208	#define M8260_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
209	#define M8260_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
210	#endif
211
212	/*
213	*************************************************************************
214	* DMA Controllers *
215	*************************************************************************
216	*/
217	typedef struct m8260IDMAparms_ {
218	uint16_t ibase;
219	uint16_t dcm;
220	uint16_t ibdptr;
221	uint16_t dpr_buf;
222	uint16_t _buf_inv;
223	uint16_t ssmax;
224	uint16_t _dpr_in_ptr;
225	uint16_t sts;
226	uint16_t _dpr_out_ptr;
227	uint16_t seob;
228	uint16_t deob;
229	uint16_t dts;
230	uint16_t _ret_add;
231	uint16_t reserved;
232	uint32_t _bd_cnt;
233	uint32_t _s_ptr;
234	uint32_t _d_ptr;
235	uint32_t istate;
236	} m8260IDMAparms_t;
237
238
239	/*
240	*************************************************************************
241	* Serial Communication Controllers *
242	*************************************************************************
243	*/
244
245
246	typedef struct m8260SCCparms_ {
247	uint16_t rbase;
248	uint16_t tbase;
249	uint8_t rfcr;
250	uint8_t tfcr;
251	uint16_t mrblr;
252	uint32_t _rstate;
253	uint32_t _pad0;
254	uint16_t _rbptr;
255	uint16_t _pad1;
256	uint32_t _pad2;
257	uint32_t _tstate;
258	uint32_t _pad3;
259	uint16_t _tbptr;
260	uint16_t _pad4;
261	uint32_t _pad5;
262	uint32_t _rcrc;
263	uint32_t _tcrc;
264	union {
265	struct {
266	uint32_t _res0;
267	uint32_t _res1;
268	uint16_t max_idl;
269	uint16_t idlc;
270	uint16_t brkcr;
271	uint16_t parec;
272	uint16_t frmec;
273	uint16_t nosec;
274	uint16_t brkec;
275	uint16_t brklen;
276	uint16_t uaddr[2];
277	uint16_t rtemp;
278	uint16_t toseq;
279	uint16_t character[8];
280	uint16_t rccm;
281	uint16_t rccr;
282	uint16_t rlbc;
283	} uart;
284	struct {
285	uint32_t _pad0;
286	uint32_t c_mask;
287	uint32_t c_pres;
288	uint16_t disfc;
289	uint16_t crcec;
290	uint16_t abtsc;
291	uint16_t nmarc;
292	uint16_t retrc;
293	uint16_t mflr;
294	uint16_t _max_cnt;
295	uint16_t rfthr;
296	uint16_t _rfcnt;
297	uint16_t hmask;
298	uint16_t haddr1;
299	uint16_t haddr2;
300	uint16_t haddr3;
301	uint16_t haddr4;
302	uint16_t _tmp;
303	uint16_t _tmp_mb;
304	} hdlc;
305	struct {
306	uint32_t _pad0;
307	uint32_t crcc;
308	uint16_t prcrc;
309	uint16_t ptcrc;
310	uint16_t parec;
311	uint16_t bsync;
312	uint16_t bdle;
313	uint16_t character[8];
314	uint16_t rccm;
315	} bisync;
316	struct {
317	uint32_t _crc_p;
318	uint32_t _crc_c;
319	} transparent;
320	struct {
321	uint32_t c_pres;
322	uint32_t c_mask;
323	uint32_t crcec;
324	uint32_t alec;
325	uint32_t disfc;
326	uint16_t pads;
327	uint16_t ret_lim;
328	uint16_t _ret_cnt;
329	uint16_t mflr;
330	uint16_t minflr;
331	uint16_t maxd1;
332	uint16_t maxd2;
333	uint16_t _maxd;
334	uint16_t _dma_cnt;
335	uint16_t _max_b;
336	uint16_t gaddr1;
337	uint16_t gaddr2;
338	uint16_t gaddr3;
339	uint16_t gaddr4;
340	uint32_t _tbuf0data0;
341	uint32_t _tbuf0data1;
342	uint32_t _tbuf0rba0;
343	uint32_t _tbuf0crc;
344	uint16_t _tbuf0bcnt;
345	uint16_t paddr_h;
346	uint16_t paddr_m;
347	uint16_t paddr_l;
348	uint16_t p_per;
349	uint16_t _rfbd_ptr;
350	uint16_t _tfbd_ptr;
351	uint16_t _tlbd_ptr;
352	uint32_t _tbuf1data0;
353	uint32_t _tbuf1data1;
354	uint32_t _tbuf1rba0;
355	uint32_t _tbuf1crc;
356	uint16_t _tbuf1bcnt;
357	uint16_t _tx_len;
358	uint16_t iaddr1;
359	uint16_t iaddr2;
360	uint16_t iaddr3;
361	uint16_t iaddr4;
362	uint16_t _boff_cnt;
363	uint16_t taddr_l;
364	uint16_t taddr_m;
365	uint16_t taddr_h;
366	} ethernet;
367	} un;
368	} m8260SCCparms_t;
369
370
371	/*
372	* Event and mask registers (SCCE, SCCM)
373	*/
374	#define M8260_SCCE_BRKE (1<<6)
375	#define M8260_SCCE_BRK (1<<5)
376	#define M8260_SCCE_TXE (1<<4)
377	#define M8260_SCCE_RXF (1<<3)
378	#define M8260_SCCE_BSY (1<<2)
379	#define M8260_SCCE_TX (1<<1)
380	#define M8260_SCCE_RX (1<<0)
381
382
383	/*
384	*************************************************************************
385	* Fast Serial Communication Controllers *
386	*************************************************************************
387	*/
388
389
390	typedef struct m8260FCCparms_ {
391	uint16_t riptr;
392	uint16_t tiptr;
393	uint16_t _pad0;
394	uint16_t mrblr;
395	uint32_t rstate;
396	uint32_t rbase;
397	uint16_t _rbdstat;
398	uint16_t _rbdlen;
399	uint32_t _rdptr;
400	uint32_t tstate;
401	uint32_t tbase;
402	uint16_t _tbdstat;
403	uint16_t _tbdlen;
404	uint32_t _tdptr;
405	uint32_t _rbptr;
406	uint32_t _tbptr;
407	uint32_t _rcrc;
408	uint32_t _pad1;
409	uint32_t _tcrc;
410
411	union {
412	struct {
413	uint32_t _pad0;
414	uint32_t _pad1;
415	uint32_t c_mask;
416	uint32_t c_pres;
417	uint16_t disfc;
418	uint16_t crcec;
419	uint16_t abtsc;
420	uint16_t nmarc;
421	uint32_t _max_cnt;
422	uint16_t mflr;
423	uint16_t rfthr;
424	uint16_t rfcnt;
425	uint16_t hmask;
426	uint16_t haddr1;
427	uint16_t haddr2;
428	uint16_t haddr3;
429	uint16_t haddr4;
430	uint16_t _ts_tmp;
431	uint16_t _tmp_mb;
432	} hdlc;
433	struct {
434	uint32_t _pad0;
435	uint32_t _pad1;
436	uint32_t c_mask;
437	uint32_t c_pres;
438	uint16_t disfc;
439	uint16_t crcec;
440	uint16_t abtsc;
441	uint16_t nmarc;
442	uint32_t _max_cnt;
443	uint16_t mflr;
444	uint16_t rfthr;
445	uint16_t rfcnt;
446	uint16_t hmask;
447	uint16_t haddr1;
448	uint16_t haddr2;
449	uint16_t haddr3;
450	uint16_t haddr4;
451	uint16_t _ts_tmp;
452	uint16_t _tmp_mb;
453	} transparent;
454	struct {
455	uint32_t _stat_buf;
456	uint32_t cam_ptr;
457	uint32_t c_mask;
458	uint32_t c_pres;
459	uint32_t crcec;
460	uint32_t alec;
461	uint32_t disfc;
462	uint16_t ret_lim;
463	uint16_t _ret_cnt;
464	uint16_t p_per;
465	uint16_t _boff_cnt;
466	uint32_t gaddr_h;
467	uint32_t gaddr_l;
468	uint16_t tfcstat;
469	uint16_t tfclen;
470	uint32_t tfcptr;
471	uint16_t mflr;
472	uint16_t paddr1_h;
473	uint16_t paddr1_m;
474	uint16_t paddr1_l;
475	uint16_t _ibd_cnt;
476	uint16_t _ibd_start;
477	uint16_t _ibd_end;
478	uint16_t _tx_len;
479	uint16_t _ibd_base;
480	uint32_t iaddr_h;
481	uint32_t iaddr_l;
482	uint16_t minflr;
483	uint16_t taddr_h;
484	uint16_t taddr_m;
485	uint16_t taddr_l;
486	uint16_t pad_ptr;
487	uint16_t _pad0;
488	uint16_t _cf_range;
489	uint16_t _max_b;
490	uint16_t maxd1;
491	uint16_t maxd2;
492	uint16_t _maxd;
493	uint16_t _dma_cnt;
494	uint32_t octc;
495	uint32_t colc;
496	uint32_t broc;
497	uint32_t mulc;
498	uint32_t uspc;
499	uint32_t frgc;
500	uint32_t ospc;
501	uint32_t jbrc;
502	uint32_t p64c;
503	uint32_t p65c;
504	uint32_t p128c;
505	uint32_t p256c;
506	uint32_t p512c;
507	uint32_t p1024c;
508	uint32_t _cam_buf;
509	uint32_t _pad1;
510	} ethernet;
511	} un;
512	} m8260FCCparms_t;
513
514
515	/*
516	* Receive and transmit function code register bits
517	* These apply to the function code registers of all devices, not just SCC.
518	*/
519	#define M8260_RFCR_BO(x) ((x)<<3)
520	#define M8260_RFCR_MOT (2<<3)
521	#define M8260_RFCR_LOCAL_BUS (2)
522	#define M8260_RFCR_60X_BUS (0)
523	#define M8260_TFCR_BO(x) ((x)<<3)
524	#define M8260_TFCR_MOT (2<<3)
525	#define M8260_TFCR_LOCAL_BUS (2)
526	#define M8260_TFCR_60X_BUS (0)
527
528	/*
529	*************************************************************************
530	* Serial Management Controllers *
531	*************************************************************************
532	*/
533	typedef struct m8260SMCparms_ {
534	uint16_t rbase;
535	uint16_t tbase;
536	uint8_t rfcr;
537	uint8_t tfcr;
538	uint16_t mrblr;
539	uint32_t _rstate;
540	uint32_t _pad0;
541	uint16_t _rbptr;
542	uint16_t _pad1;
543	uint32_t _pad2;
544	uint32_t _tstate;
545	uint32_t _pad3;
546	uint16_t _tbptr;
547	uint16_t _pad4;
548	uint32_t _pad5;
549	union {
550	struct {
551	uint16_t max_idl;
552	uint16_t _idlc;
553	uint16_t _brkln;
554	uint16_t brkec;
555	uint16_t brkcr;
556	uint16_t _r_mask;
557	} uart;
558	struct {
559	uint16_t _pad0[6];
560	} transparent;
561	} un;
562	uint32_t _pad6;
563	} m8260SMCparms_t;
564
565	/*
566	* Mode register
567	*/
568	#define M8260_SMCMR_CLEN(x) ((x)<<11) /* Character length */
569	#define M8260_SMCMR_2STOP (1<<10) /* 2 stop bits */
570	#define M8260_SMCMR_PARITY (1<<9) /* Enable parity */
571	#define M8260_SMCMR_EVEN (1<<8) /* Even parity */
572	#define M8260_SMCMR_SM_GCI (0<<4) /* GCI Mode */
573	#define M8260_SMCMR_SM_UART (2<<4) /* UART Mode */
574	#define M8260_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
575	#define M8260_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
576	#define M8260_SMCMR_DM_ECHO (2<<2) /* Echo mode */
577	#define M8260_SMCMR_TEN (1<<1) /* Enable transmitter */
578	#define M8260_SMCMR_REN (1<<0) /* Enable receiver */
579
580	/*
581	* Event and mask registers (SMCE, SMCM)
582	*/
583	#define M8260_SMCE_TXE (1<<4)
584	#define M8260_SMCE_BSY (1<<2)
585	#define M8260_SMCE_TX (1<<1)
586	#define M8260_SMCE_RX (1<<0)
587
588	/*
589	*************************************************************************
590	* Serial Peripheral Interface *
591	*************************************************************************
592	*/
593	typedef struct m8260SPIparms_ {
594	uint16_t rbase;
595	uint16_t tbase;
596	uint8_t rfcr;
597	uint8_t tfcr;
598	uint16_t mrblr;
599	uint32_t _rstate;
600	uint32_t _pad0;
601	uint16_t _rbptr;
602	uint16_t _pad1;
603	uint32_t _pad2;
604	uint32_t _tstate;
605	uint32_t _pad3;
606	uint16_t _tbptr;
607	uint16_t _pad4;
608	uint32_t _pad5;
609	} m8260SPIparms_t;
610
611	/*
612	* Mode register (SPMODE)
613	*/
614	#define M8260_SPMODE_LOOP (1<<14) /* Local loopback mode */
615	#define M8260_SPMODE_CI (1<<13) /* Clock invert */
616	#define M8260_SPMODE_CP (1<<12) /* Clock phase */
617	#define M8260_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
618	#define M8260_SPMODE_REV (1<<10) /* Reverse data */
619	#define M8260_SPMODE_MASTER (1<<9) /* SPI is master */
620	#define M8260_SPMODE_EN (1<<8) /* Enable SPI */
621	#define M8260_SPMODE_CLEN(x) ((x)<<4) /* Character length */
622	#define M8260_SPMODE_PM(x) (x) /* Prescaler modulus */
623
624	/*
625	* Mode register (SPCOM)
626	*/
627	#define M8260_SPCOM_STR (1<<7) /* Start transmit */
628
629	/*
630	* Event and mask registers (SPIE, SPIM)
631	*/
632	#define M8260_SPIE_MME (1<<5) /* Multi-master error */
633	#define M8260_SPIE_TXE (1<<4) /* Tx error */
634	#define M8260_SPIE_BSY (1<<2) /* Busy condition*/
635	#define M8260_SPIE_TXB (1<<1) /* Tx buffer */
636	#define M8260_SPIE_RXB (1<<0) /* Rx buffer */
637
638	/*
639	*************************************************************************
640	* SDMA (SCC, SMC, SPI) Buffer Descriptors *
641	*************************************************************************
642	*/
643	typedef struct m8260BufferDescriptor_ {
644	uint16_t status;
645	uint16_t length;
646	volatile void *buffer;
647	} m8260BufferDescriptor_t;
648
649	/*
650	* Bits in receive buffer descriptor status word
651	*/
652	#define M8260_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
653	#define M8260_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
654	#define M8260_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
655	#define M8260_BD_LAST (1<<11) /* Ethernet, SPI */
656	#define M8260_BD_CONTROL_CHAR (1<<11) /* SCC UART */
657	#define M8260_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
658	#define M8260_BD_ADDRESS (1<<10) /* SCC UART */
659	#define M8260_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
660	#define M8260_BD_MISS (1<<8) /* Ethernet */
661	#define M8260_BD_IDLE (1<<8) /* SCC UART, SMC UART */
662	#define M8260_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
663	#define M8260_BD_LONG (1<<5) /* Ethernet, SCC HDLC */
664	#define M8260_BD_BREAK (1<<5) /* SCC UART, SMC UART */
665	#define M8260_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */
666	#define M8260_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
667	#define M8260_BD_SHORT (1<<3) /* Ethernet */
668	#define M8260_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
669	#define M8260_BD_ABORT (1<<3) /* SCC HDLC */
670	#define M8260_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */
671	#define M8260_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
672	#define M8260_BD_COLLISION (1<<0) /* Ethernet */
673	#define M8260_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */
674	#define M8260_BD_MASTER_ERROR (1<<0) /* SPI */
675
676	#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
677	#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
678	#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
679	#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */
680	#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */
681	#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
682	#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */
683	#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
684	#define M8xx_BD_MISS (1<<8) /* Ethernet */
685	#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */
686	#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
687	#define M8xx_BD_LONG (1<<5) /* Ethernet, SCC HDLC */
688	#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */
689	#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */
690	#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
691	#define M8xx_BD_SHORT (1<<3) /* Ethernet */
692	#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
693	#define M8xx_BD_ABORT (1<<3) /* SCC HDLC */
694	#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */
695	#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
696	#define M8xx_BD_COLLISION (1<<0) /* Ethernet */
697	#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */
698	#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */
699
700	/*
701	* Bits in transmit buffer descriptor status word
702	* Many bits have the same meaning as those in receiver buffer descriptors.
703	*/
704	#define M8260_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
705	#define M8260_BD_PAD (1<<14) /* Ethernet */
706	#define M8260_BD_CTS_REPORT (1<<11) /* SCC UART */
707	#define M8260_BD_TX_CRC (1<<10) /* Ethernet */
708	#define M8260_BD_DEFER (1<<9) /* Ethernet */
709	#define M8260_BD_HEARTBEAT (1<<8) /* Ethernet */
710	#define M8260_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
711	#define M8260_BD_LATE_COLLISION (1<<7) /* Ethernet */
712	#define M8260_BD_NO_STOP_BIT (1<<7) /* SCC UART */
713	#define M8260_BD_RETRY_LIMIT (1<<6) /* Ethernet */
714	#define M8260_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
715	#define M8260_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */
716	#define M8260_BD_CARRIER_LOST (1<<0) /* Ethernet */
717	#define M8260_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */
718
719	#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
720	#define M8xx_BD_PAD (1<<14) /* Ethernet */
721	#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */
722	#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */
723	#define M8xx_BD_DEFER (1<<9) /* Ethernet */
724	#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */
725	#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
726	#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */
727	#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */
728	#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */
729	#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
730	#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */
731	#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */
732	#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */
733
734	/*
735	*************************************************************************
736	* IDMA Buffer Descriptors *
737	*************************************************************************
738	*/
739	typedef struct m8260IDMABufferDescriptor_ {
740	uint16_t status;
741	uint8_t dfcr;
742	uint8_t sfcr;
743	uint32_t length;
744	void *source;
745	void *destination;
746	} m8260IDMABufferDescriptor_t;
747
748	/*
749	*************************************************************************
750	* RISC Communication Processor Module Command Register (CR) *
751	*************************************************************************
752	*/
753	#define M8260_CR_RST (1<<31) /* Reset communication processor */
754
755	#define M8260_CR_FCC1 ((4<<26)\|(16<<21)) /* FCC1 page and code */
756	#define M8260_CR_FCC1_ATM ((4<<26)\|(14<<21)) /* FCC1 ATM mode page and code */
757	#define M8260_CR_FCC2 ((5<<26)\|(17<<21)) /* FCC2 page and code */
758	#define M8260_CR_FCC2_ATM ((5<<26)\|(14<<21)) /* FCC2 ATM mode page and code */
759	#define M8260_CR_FCC3 ((6<<26)\|(18<<21)) /* FCC3 page and code */
760	#define M8260_CR_SCC1 ((0<<26)\|(4<<21)) /* SCC1 page and code */
761	#define M8260_CR_SCC2 ((1<<26)\|(5<<21)) /* SCC2 page and code */
762	#define M8260_CR_SCC3 ((2<<26)\|(6<<21)) /* SCC3 page and code */
763	#define M8260_CR_SCC4 ((3<<26)\|(7<<21)) /* SCC4 page and code */
764	#define M8260_CR_SMC1 ((7<<26)\|(8<<21)) /* SMC1 page and code */
765	#define M8260_CR_SMC2 ((8<<26)\|(9<<21)) /* SMC2 page and code */
766	#define M8260_CR_RAND ((10<<26)\|(14<<21)) /* SMC2 page and code */
767	#define M8260_CR_SPI ((9<<26)\|(10<<21)) /* SPI page and code */
768	#define M8260_CR_I2C ((10<<26)\|(11<<21)) /* I2C page and code */
769	#define M8260_CR_TMR ((10<<26)\|(15<<21)) /* Timer page and code */
770	#define M8260_CR_MCC1 ((7<<26)\|(28<<21)) /* MCC1 page and code */
771	#define M8260_CR_MCC2 ((8<<26)\|(29<<21)) /* MCC2 page and code */
772	#define M8260_CR_IDMA1 ((7<<26)\|(20<<21)) /* IDMA1 page and code */
773	#define M8260_CR_IDMA2 ((8<<26)\|(21<<21)) /* IDMA2 page and code */
774	#define M8260_CR_IDMA3 ((9<<26)\|(22<<21)) /* IDMA3 page and code */
775	#define M8260_CR_IDMA4 ((10<<26)\|(23<<21)) /* IDMA4 page and code */
776
777	#define M8260_CR_FLG (1<<16) /* Command sempahore flag */
778
779	#define M8260_CR_MCC_CHAN(x) ((x)<<6) /* MCC channel number */
780	#define M8260_CR_FCC_HDLC (0<<6) /* FCC HDLC/Transparent protocol code */
781	#define M8260_CR_FCC_ATM (10<<6) /* FCC ATM protocol code */
782	#define M8260_CR_FCC_ETH (12<<6) /* FCC Ethernet protocol code */
783
784	#define M8260_CR_OP_INIT_RX_TX (0) /* FCC, SCC, SMC UART, SMC GCI, SPI, I2C, MCC */
785	#define M8260_CR_OP_INIT_RX (1) /* FCC, SCC, SMC UART, SPI, I2C, MCC */
786	#define M8260_CR_OP_INIT_TX (2) /* FCC, SCC, SMC UART, SPI, I2C, MCC */
787	#define M8260_CR_OP_INIT_HUNT (3) /* FCC, SCC, SMC UART */
788	#define M8260_CR_OP_STOP_TX (4) /* FCC, SCC, SMC UART, MCC */
789	#define M8260_CR_OP_GR_STOP_TX (5) /* FCC, SCC */
790	#define M8260_CR_OP_RESTART_TX (6) /* FCC, SCC, SMC UART */
791	#define M8260_CR_OP_CLOSE_RX_BD (7) /* FCC, SCC, SMC UART, SPI, I2C */
792	#define M8260_CR_OP_SET_GRP_ADDR (8) /* FCC, SCC */
793	#define M8260_CR_OP_SET_TIMER (8) /* Timer */
794	#define M8260_CR_OP_GCI_TIMEOUT (9) /* SMC GCI */
795	#define M8260_CR_OP_START_IDMA (9) /* IDMA */
796	#define M8260_CR_OP_STOP_RX (9) /* MCC */
797	#define M8260_CR_OP_ATM_TX (10) /* FCC */
798	#define M8260_CR_OP_RESET_BCS (10) /* SCC */
799	#define M8260_CR_OP_GCI_ABORT (10) /* SMC GCI */
800	#define M8260_CR_OP_STOP_IDMA (11) /* IDMA */
801	#define M8260_CR_OP_RANDOM (12) /* RAND */
802
803	/*
804	*************************************************************************
805	* System Protection Control Register (SYPCR) *
806	*************************************************************************
807	*/
808	#define M8260_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */
809	#define M8260_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
810	#define M8260_SYPCR_BME (1<<7) /* Bus monitor enable */
811	#define M8260_SYPCR_SWF (1<<3) /* Software watchdog freeze */
812	#define M8260_SYPCR_SWE (1<<2) /* Software watchdog enable */
813	#define M8260_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
814	#define M8260_SYPCR_SWP (1<<0) /* Software watchdog prescale */
815
816	/*
817	*************************************************************************
818	* Memory Control Registers *
819	*************************************************************************
820	*/
821	#define M8260_UPM_AMX_8col (0<<20) /* 8 column DRAM */
822	#define M8260_UPM_AMX_9col (1<<20) /* 9 column DRAM */
823	#define M8260_UPM_AMX_10col (2<<20) /* 10 column DRAM */
824	#define M8260_UPM_AMX_11col (3<<20) /* 11 column DRAM */
825	#define M8260_UPM_AMX_12col (4<<20) /* 12 column DRAM */
826	#define M8260_UPM_AMX_13col (5<<20) /* 13 column DRAM */
827	#define M8260_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */
828	#define M8260_MSR_WPER (1<<7) /* Write protection error */
829	#define M8260_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */
830	#define M8260_BR_BA(x) ((x)&0xffff8000) /* Base address */
831	#define M8260_BR_AT(x) ((x)<<12) /* Address type */
832	#define M8260_BR_PS8 (1<<10) /* 8 bit port */
833	#define M8260_BR_PS16 (2<<10) /* 16 bit port */
834	#define M8260_BR_PS32 (0<<10) /* 32 bit port */
835	#define M8260_BR_PARE (1<<9) /* Parity checking enable */
836	#define M8260_BR_WP (1<<8) /* Write protect */
837	#define M8260_BR_MS_GPCM (0<<6) /* GPCM */
838	#define M8260_BR_MS_UPMA (2<<6) /* UPM A */
839	#define M8260_BR_MS_UPMB (3<<6) /* UPM B */
840	#define M8260_MEMC_BR_V (1<<0) /* Base/Option register are valid */
841
842	#define M8260_MEMC_OR_32K 0xffff8000 /* Address range */
843	#define M8260_MEMC_OR_64K 0xffff0000
844	#define M8260_MEMC_OR_128K 0xfffe0000
845	#define M8260_MEMC_OR_256K 0xfffc0000
846	#define M8260_MEMC_OR_512K 0xfff80000
847	#define M8260_MEMC_OR_1M 0xfff00000
848	#define M8260_MEMC_OR_2M 0xffe00000
849	#define M8260_MEMC_OR_4M 0xffc00000
850	#define M8260_MEMC_OR_8M 0xff800000
851	#define M8260_MEMC_OR_16M 0xff000000
852	#define M8260_MEMC_OR_32M 0xfe000000
853	#define M8260_MEMC_OR_64M 0xfc000000
854	#define M8260_MEMC_OR_128 0xf8000000
855	#define M8260_MEMC_OR_256M 0xf0000000
856	#define M8260_MEMC_OR_512M 0xe0000000
857	#define M8260_MEMC_OR_1G 0xc0000000
858	#define M8260_MEMC_OR_2G 0x80000000
859	#define M8260_MEMC_OR_4G 0x00000000
860	#define M8260_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */
861	#define M8260_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */
862	#define M8260_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */
863	#define M8260_MEMC_OR_ACS_NORM (0<<9) /* CS asserted with addr lines /
864	#define M8260_MEMC_OR_ACS_QRTR (2<<9) /* CS asserted 1/4 after addr /
865	#define M8260_MEMC_OR_ACS_HALF (3<<9) /* CS asserted 1/2 after addr /
866	#define M8260_MEMC_OR_BI (1<8) /* Burst inhibit */
867	#define M8260_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */
868	#define M8260_MEMC_OR_SETA (1<<3) /* TA generated externally /
869	#define M8260_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */
870	#define M8260_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */
871
872	/*
873	*************************************************************************
874	* UPM Registers (MxMR) *
875	*************************************************************************
876	*/
877	#define M8260_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */
878	#define M8260_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */
879	#define M8260_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */
880	#define M8260_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */
881	#define M8260_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */
882	#define M8260_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */
883	#define M8260_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */
884	#define M8260_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */
885	/*
886	*************************************************************************
887	* Memory Command Register (MCR) *
888	*************************************************************************
889	*/
890	#define M8260_MEMC_MCR_WRITE (0<<30) /* WRITE command */
891	#define M8260_MEMC_MCR_READ (1<<30) /* READ command */
892	#define M8260_MEMC_MCR_RUN (2<<30) /* RUN command */
893	#define M8260_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */
894	#define M8260_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */
895	#define M8260_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */
896	#define M8260_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */
897	#define M8260_MEMC_MCR_MAD(x) (x) /* Machine address */
898
899
900
901	/*
902	*************************************************************************
903	* SI Mode Register (SIMODE) *
904	*************************************************************************
905	*/
906	#define M8260_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
907	#define M8260_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
908	#define M8260_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
909	#define M8260_SI_SMC2_BRG2 (1<<28)
910	#define M8260_SI_SMC2_BRG3 (2<<28)
911	#define M8260_SI_SMC2_BRG4 (3<<28)
912	#define M8260_SI_SMC2_CLK5 (0<<28)
913	#define M8260_SI_SMC2_CLK6 (1<<28)
914	#define M8260_SI_SMC2_CLK7 (2<<28)
915	#define M8260_SI_SMC2_CLK8 (3<<28)
916	#define M8260_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
917	#define M8260_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
918	#define M8260_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
919	#define M8260_SI_SMC1_BRG2 (1<<12)
920	#define M8260_SI_SMC1_BRG3 (2<<12)
921	#define M8260_SI_SMC1_BRG4 (3<<12)
922	#define M8260_SI_SMC1_CLK1 (0<<12)
923	#define M8260_SI_SMC1_CLK2 (1<<12)
924	#define M8260_SI_SMC1_CLK3 (2<<12)
925	#define M8260_SI_SMC1_CLK4 (3<<12)
926
927	/*
928	*************************************************************************
929	* SDMA Configuration Register (SDCR) *
930	*************************************************************************
931	*/
932	#define M8260_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */
933	#define M8260_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */
934
935	/*
936	*************************************************************************
937	* SDMA Status Register (SDSR) *
938	*************************************************************************
939	*/
940	#define M8260_SDSR_SBER (1<<7) /* SDMA Channel bus error */
941	#define M8260_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */
942	#define M8260_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */
943
944	/*
945	*************************************************************************
946	* Baud (sic) Rate Generators *
947	*************************************************************************
948	*/
949	#define M8260_BRG_RST (1<<17) /* Reset generator */
950	#define M8260_BRG_EN (1<<16) /* Enable generator */
951	#define M8260_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
952	#define M8260_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
953	#define M8260_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
954	#define M8260_BRG_ATB (1<<13) /* Autobaud */
955	#define M8260_BRG_115200 (21<<1) /* Assume 40 MHz clock */
956	#define M8260_BRG_57600 (32<<1)
957	#define M8260_BRG_38400 (64<<1)
958	#define M8260_BRG_19200 (129<<1)
959	#define M8260_BRG_9600 (259<<1)
960	#define M8260_BRG_4800 (520<<1)
961	#define M8260_BRG_2400 (1040<<1)
962	#define M8260_BRG_1200 (2082<<1)
963	#define M8260_BRG_600 ((259<<1) \| 1)
964	#define M8260_BRG_300 ((520<<1) \| 1)
965	#define M8260_BRG_150 ((1040<<1) \| 1)
966	#define M8260_BRG_75 ((2080<<1) \| 1)
967
968	#define M8xx_BRG_RST (1<<17) /* Reset generator */
969	#define M8xx_BRG_EN (1<<16) /* Enable generator */
970	#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
971
972	#define M8260_BRG1 (1<<7)
973	#define M8260_BRG2 (1<<6)
974	#define M8260_BRG3 (1<<5)
975	#define M8260_BRG4 (1<<4)
976	#define M8260_BRG5 (1<<3)
977	#define M8260_BRG6 (1<<2)
978	#define M8260_BRG7 (1<<1)
979	#define M8260_BRG8 (1<<0)
980
981
982
983	#define M8260_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */
984	#define M8260_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */
985	#define M8260_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */
986	#define M8260_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */
987	#define M8260_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */
988	#define M8260_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */
989	#define M8260_TGCR_STP1 (1<<1) /* Stop timer */
990	#define M8260_TGCR_STP2 (1<<5) /* Stop timer */
991	#define M8260_TGCR_STP3 (1<<9) /* Stop timer */
992	#define M8260_TGCR_STP4 (1<<13) /* Stop timer */
993	#define M8260_TGCR_RST1 (1<<0) /* Enable timer */
994	#define M8260_TGCR_RST2 (1<<4) /* Enable timer */
995	#define M8260_TGCR_RST3 (1<<8) /* Enable timer */
996	#define M8260_TGCR_RST4 (1<<12) /* Enable timer */
997	#define M8260_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */
998	#define M8260_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */
999
1000	#define M8260_TMR_PS(x) ((x)<<8) /* Timer prescaler */
1001	#define M8260_TMR_CE_RISE (1<<6) /* Capture on rising edge */
1002	#define M8260_TMR_CE_FALL (2<<6) /* Capture on falling edge */
1003	#define M8260_TMR_CE_ANY (3<<6) /* Capture on any edge */
1004	#define M8260_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */
1005	#define M8260_TMR_ORI (1<<4) /* Interrupt on reaching reference */
1006	#define M8260_TMR_RESTART (1<<3) /* Restart timer after reference */
1007	#define M8260_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */
1008	#define M8260_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */
1009	#define M8260_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */
1010	#define M8260_TMR_TGATE (1<<0) /* TGATE controls timer */
1011
1012	#ifdef REV_0_2
1013	#define M8260_PISCR_PS (1<<6) /* PIT Interrupt state */
1014	#else
1015	#define M8260_PISCR_PS (1<<7) /* PIT Interrupt state */
1016	#endif
1017	#define M8260_PISCR_PIE (1<<2) /* PIT interrupt enable */
1018	#define M8260_PISCR_PTF (1<<1) /* Stop timer when freeze asserted */
1019	#define M8260_PISCR_PTE (1<<0) /* PIT enable */
1020
1021	#if 0
1022	#define M8260_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */
1023	#define M8260_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */
1024	#define M8260_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */
1025	#define M8260_TBSCR_REFAE (1<<3) /* Enable ints for REFA */
1026	#define M8260_TBSCR_REFBE (1<<2) /* Enable ints for REFB */
1027	#define M8260_TBSCR_TBF (1<<1) /* TB stops on FREEZE */
1028	#define M8260_TBSCR_TBE (1<<0) /* enable TB and decrementer */
1029	#endif
1030
1031	#define M8260_TMCNTSC_SEC (1<<7) /* per second flag */
1032	#define M8260_TMCNTSC_ALR (1<<6) /* Alarm interrupt flag */
1033	#define M8260_TMCNTSC_SIE (1<<3) /* per second interrupt enable */
1034	#define M8260_TMCNTSC_ALE (1<<2) /* Alarm interrupt enable */
1035	#define M8260_TMCNTSC_TCF (1<<1) /* Time count frequency */
1036	#define M8260_TMCNTSC_TCE (1<<0) /* Time count enable */
1037
1038	#define M8260_SIMASK_PC0 (1<<31)
1039	#define M8260_SIMASK_PC1 (1<<30)
1040	#define M8260_SIMASK_PC2 (1<<29)
1041	#define M8260_SIMASK_PC3 (1<<28)
1042	#define M8260_SIMASK_PC4 (1<<27)
1043	#define M8260_SIMASK_PC5 (1<<26)
1044	#define M8260_SIMASK_PC6 (1<<25)
1045	#define M8260_SIMASK_PC7 (1<<24)
1046	#define M8260_SIMASK_PC8 (1<<23)
1047	#define M8260_SIMASK_PC9 (1<<22)
1048	#define M8260_SIMASK_PC10 (1<<21)
1049	#define M8260_SIMASK_PC11 (1<<20)
1050	#define M8260_SIMASK_PC12 (1<<19)
1051	#define M8260_SIMASK_PC13 (1<<18)
1052	#define M8260_SIMASK_PC14 (1<<17)
1053	#define M8260_SIMASK_PC15 (1<<16)
1054	#define M8260_SIMASK_IRQ1 (1<<14)
1055	#define M8260_SIMASK_IRQ2 (1<<13)
1056	#define M8260_SIMASK_IRQ3 (1<<12)
1057	#define M8260_SIMASK_IRQ4 (1<<11)
1058	#define M8260_SIMASK_IRQ5 (1<<10)
1059	#define M8260_SIMASK_IRQ6 (1<<9)
1060	#define M8260_SIMASK_IRQ7 (1<<8)
1061	#define M8260_SIMASK_TMCNT (1<<2)
1062	#define M8260_SIMASK_PIT (1<<1)
1063
1064	#define M8260_SIMASK_FCC1 (1<<31)
1065	#define M8260_SIMASK_FCC2 (1<<30)
1066	#define M8260_SIMASK_FCC3 (1<<29)
1067	#define M8260_SIMASK_MCC1 (1<<27)
1068	#define M8260_SIMASK_MCC2 (1<<26)
1069	#define M8260_SIMASK_SCC1 (1<<23)
1070	#define M8260_SIMASK_SCC2 (1<<22)
1071	#define M8260_SIMASK_SCC3 (1<<21)
1072	#define M8260_SIMASK_SCC4 (1<<20)
1073	#define M8260_SIMASK_I2C (1<<15)
1074	#define M8260_SIMASK_SPI (1<<14)
1075	#define M8260_SIMASK_RTT (1<<13)
1076	#define M8260_SIMASK_SMC1 (1<<12)
1077	#define M8260_SIMASK_SMC2 (1<<11)
1078	#define M8260_SIMASK_IDMA1 (1<<10)
1079	#define M8260_SIMASK_IDMA2 (1<<9)
1080	#define M8260_SIMASK_IDMA3 (1<<8)
1081	#define M8260_SIMASK_IDMA4 (1<<7)
1082	#define M8260_SIMASK_SDMA (1<<6)
1083	#define M8260_SIMASK_TIMER1 (1<<4)
1084	#define M8260_SIMASK_TIMER2 (1<<3)
1085	#define M8260_SIMASK_TIMER3 (1<<2)
1086	#define M8260_SIMASK_TIMER4 (1<<1)
1087
1088	#define M8260_SIUMCR_EARB (1<<31)
1089	#define M8260_SIUMCR_EARP0 (0<<28)
1090	#define M8260_SIUMCR_EARP1 (1<<28)
1091	#define M8260_SIUMCR_EARP2 (2<<28)
1092	#define M8260_SIUMCR_EARP3 (3<<28)
1093	#define M8260_SIUMCR_EARP4 (4<<28)
1094	#define M8260_SIUMCR_EARP5 (5<<28)
1095	#define M8260_SIUMCR_EARP6 (6<<28)
1096	#define M8260_SIUMCR_EARP7 (7<<28)
1097	#define M8260_SIUMCR_DSHW (1<<23)
1098	#define M8260_SIUMCR_DBGC0 (0<<21)
1099	#define M8260_SIUMCR_DBGC1 (1<<21)
1100	#define M8260_SIUMCR_DBGC2 (2<<21)
1101	#define M8260_SIUMCR_DBGC3 (3<<21)
1102	#define M8260_SIUMCR_DBPC0 (0<<19)
1103	#define M8260_SIUMCR_DBPC1 (1<<19)
1104	#define M8260_SIUMCR_DBPC2 (2<<19)
1105	#define M8260_SIUMCR_DBPC3 (3<<19)
1106	#define M8260_SIUMCR_FRC (1<<17)
1107	#define M8260_SIUMCR_DLK (1<<16)
1108	#define M8260_SIUMCR_PNCS (1<<15)
1109	#define M8260_SIUMCR_OPAR (1<<14)
1110	#define M8260_SIUMCR_DPC (1<<13)
1111	#define M8260_SIUMCR_MPRE (1<<12)
1112	#define M8260_SIUMCR_MLRC0 (0<<10)
1113	#define M8260_SIUMCR_MLRC1 (1<<10)
1114	#define M8260_SIUMCR_MLRC2 (2<<10)
1115	#define M8260_SIUMCR_MLRC3 (3<<10)
1116	#define M8260_SIUMCR_AEME (1<<9)
1117	#define M8260_SIUMCR_SEME (1<<8)
1118	#define M8260_SIUMCR_BSC (1<<7)
1119	#define M8260_SIUMCR_GB5E (1<<6)
1120	#define M8260_SIUMCR_B2DD (1<<5)
1121	#define M8260_SIUMCR_B3DD (1<<4)
1122
1123	/*
1124	*************************************************************************
1125	* MPC8260 DUAL-PORT RAM AND REGISTERS *
1126	*************************************************************************
1127	*/
1128	typedef struct m8260_ {
1129
1130	/*
1131	* CPM Dual-Port RAM
1132	*/
1133	uint8_t dpram1[16384]; /* 0x0000 - 0x3FFF BD/data/ucode */
1134	uint8_t cpm_pad0[16384]; /* 0x4000 - 0x7FFF Reserved */
1135
1136	m8260SCCparms_t scc1p;
1137	uint8_t pad_scc1[256-sizeof(m8260SCCparms_t)];
1138	m8260SCCparms_t scc2p;
1139	uint8_t pad_scc2[256-sizeof(m8260SCCparms_t)];
1140	m8260SCCparms_t scc3p;
1141	uint8_t pad_scc3[256-sizeof(m8260SCCparms_t)];
1142	m8260SCCparms_t scc4p;
1143	uint8_t pad_scc4[256-sizeof(m8260SCCparms_t)];
1144
1145	m8260FCCparms_t fcc1p;
1146	uint8_t pad_fcc1[256-sizeof(m8260FCCparms_t)];
1147	m8260FCCparms_t fcc2p;
1148	uint8_t pad_fcc2[256-sizeof(m8260FCCparms_t)];
1149	m8260FCCparms_t fcc3p;
1150	uint8_t pad_fcc3[256-sizeof(m8260FCCparms_t)];
1151
1152	uint8_t mcc1p[128];
1153	uint8_t pad_mcc1[124];
1154	uint16_t smc1_base;
1155	uint16_t idma1_base;
1156	uint8_t mcc2p[128];
1157	uint8_t pad_mcc2[124];
1158	uint16_t smc2_base;
1159	uint16_t idma2_base;
1160	uint8_t pad_spi[252];
1161	uint16_t spi_base;
1162	uint16_t idma3_base;
1163	uint8_t pad_risc[224];
1164	uint8_t risc_timers[16];
1165	uint16_t rev_num;
1166	uint16_t cpm_pad7;
1167	uint32_t cpm_pad8;
1168	uint16_t rand;
1169	uint16_t i2c_base;
1170	uint16_t idma4_base;
1171	uint8_t cpm_pad9[1282];
1172
1173	uint8_t cpm_pad1[8192]; /* 0x9000 - 0xAFFF Reserved */
1174
1175	m8260SMCparms_t smc1p;
1176	m8260SMCparms_t smc2p;
1177	uint8_t dpram3[4096-2*sizeof(m8260SMCparms_t)];
1178
1179	uint8_t cpm_pad2[16384]; /* 0xC000 - 0xFFFF Reserved */
1180
1181
1182	/*
1183	* General SIU Block
1184	*/
1185	uint32_t siumcr;
1186	uint32_t sypcr;
1187	uint8_t siu_pad0[6];
1188	uint16_t swsr;
1189	uint8_t siu_pad1[20];
1190	uint32_t bcr;
1191	uint8_t ppc_acr;
1192	uint8_t siu_pad4[3];
1193	uint32_t ppc_alrh;
1194	uint32_t ppc_alr1;
1195	uint8_t lcl_acr;
1196	uint8_t siu_pad5[3];
1197	uint32_t lcl_alrh;
1198	uint32_t lcl_alr1;
1199	uint32_t tescr1;
1200	uint32_t tescr2;
1201	uint32_t l_tescr1;
1202	uint32_t l_tescr2;
1203	uint32_t pdtea;
1204	uint8_t pdtem;
1205	uint8_t siu_pad2[3];
1206	uint32_t ldtea;
1207	uint8_t ldtem;
1208	uint8_t siu_pad3[163];
1209
1210
1211	/*
1212	* Memory Controller Block
1213	*/
1214	m8260MEMCRegisters_t memc[12];
1215	uint8_t mem_pad0[8];
1216	uint32_t mar;
1217	uint8_t mem_pad1[4];
1218	uint32_t mamr;
1219	uint32_t mbmr;
1220	uint32_t mcmr;
1221	uint32_t mdmr;
1222	uint8_t mem_pad2[4];
1223	uint16_t mptpr;
1224	uint8_t mem_pad5[2];
1225	uint32_t mdr;
1226	uint8_t mem_pad3[4];
1227	uint32_t psdmr;
1228	uint32_t lsdmr;
1229	uint8_t purt;
1230	uint8_t mem_pad6[3];
1231	uint8_t psrt;
1232	uint8_t mem_pad7[3];
1233	uint8_t lurt;
1234	uint8_t mem_pad8[3];
1235	uint8_t lsrt;
1236	uint8_t mem_pad9[3];
1237	uint32_t immr;
1238	uint8_t mem_pad4[84];
1239
1240
1241	/*
1242	* System integration timers
1243	*/
1244	uint8_t sit_pad0[32];
1245	uint16_t tmcntsc;
1246	uint8_t sit_pad6[2];
1247	uint32_t tmcnt;
1248	uint32_t tmcntsec;
1249	uint32_t tmcntal;
1250	uint8_t sit_pad2[16];
1251	uint16_t piscr;
1252	uint8_t sit_pad5[2];
1253	uint32_t pitc;
1254	uint32_t pitr;
1255	uint8_t sit_pad3[94];
1256	uint8_t sit_pad4[2390];
1257
1258
1259	/*
1260	* Interrupt Controller
1261	*/
1262	uint16_t sicr;
1263	uint8_t ict_pad1[2];
1264	uint32_t sivec;
1265	uint32_t sipnr_h;
1266	uint32_t sipnr_l;
1267	uint32_t siprr;
1268	uint32_t scprr_h;
1269	uint32_t scprr_l;
1270	uint32_t simr_h;
1271	uint32_t simr_l;
1272	uint32_t siexr;
1273	uint8_t ict_pad0[88];
1274
1275
1276	/*
1277	* Clocks and Reset
1278	*/
1279	uint32_t sccr;
1280	uint8_t clr_pad1[4];
1281	uint32_t scmr;
1282	uint8_t clr_pad2[4];
1283	uint32_t rsr;
1284	uint32_t rmr;
1285	uint8_t clr_pad0[104];
1286
1287
1288	/*
1289	* Input/ Output Port
1290	*/
1291	uint32_t pdira;
1292	uint32_t ppara;
1293	uint32_t psora;
1294	uint32_t podra;
1295	uint32_t pdata;
1296	uint8_t iop_pad0[12];
1297	uint32_t pdirb;
1298	uint32_t pparb;
1299	uint32_t psorb;
1300	uint32_t podrb;
1301	uint32_t pdatb;
1302	uint8_t iop_pad1[12];
1303	uint32_t pdirc;
1304	uint32_t pparc;
1305	uint32_t psorc;
1306	uint32_t podrc;
1307	uint32_t pdatc;
1308	uint8_t iop_pad2[12];
1309	uint32_t pdird;
1310	uint32_t ppard;
1311	uint32_t psord;
1312	uint32_t podrd;
1313	uint32_t pdatd;
1314	uint8_t iop_pad3[12];
1315
1316
1317	/*
1318	* CPM Timers
1319	*/
1320	uint8_t tgcr1;
1321	uint8_t cpt_pad0[3];
1322	uint8_t tgcr2;
1323	uint8_t cpt_pad1[11];
1324	uint16_t tmr1;
1325	uint16_t tmr2;
1326	uint16_t trr1;
1327	uint16_t trr2;
1328	uint16_t tcr1;
1329	uint16_t tcr2;
1330	uint16_t tcn1;
1331	uint16_t tcn2;
1332	uint16_t tmr3;
1333	uint16_t tmr4;
1334	uint16_t trr3;
1335	uint16_t trr4;
1336	uint16_t tcr3;
1337	uint16_t tcr4;
1338	uint16_t tcn3;
1339	uint16_t tcn4;
1340	uint16_t ter1;
1341	uint16_t ter2;
1342	uint16_t ter3;
1343	uint16_t ter4;
1344	uint8_t cpt_pad2[608];
1345
1346
1347	/*
1348	* DMA Block
1349	*/
1350	uint8_t sdsr;
1351	uint8_t dma_pad0[3];
1352	uint8_t sdmr;
1353	uint8_t dma_pad1[3];
1354
1355	uint8_t idsr1;
1356	uint8_t dma_pad2[3];
1357	uint8_t idmr1;
1358	uint8_t dma_pad3[3];
1359	uint8_t idsr2;
1360	uint8_t dma_pad4[3];
1361	uint8_t idmr2;
1362	uint8_t dma_pad5[3];
1363	uint8_t idsr3;
1364	uint8_t dma_pad6[3];
1365	uint8_t idmr3;
1366	uint8_t dma_pad7[3];
1367	uint8_t idsr4;
1368	uint8_t dma_pad8[3];
1369	uint8_t idmr4;
1370	uint8_t dma_pad9[707];
1371
1372
1373	/*
1374	* FCC Block
1375	*/
1376	m8260FCCRegisters_t fcc1;
1377	m8260FCCRegisters_t fcc2;
1378	m8260FCCRegisters_t fcc3;
1379
1380	uint8_t fcc_pad0[656];
1381
1382	/*
1383	* BRG 5-8 Block
1384	*/
1385	uint32_t brgc5;
1386	uint32_t brgc6;
1387	uint32_t brgc7;
1388	uint32_t brgc8;
1389	uint8_t brg_pad0[608];
1390
1391
1392	/*
1393	* I2C
1394	*/
1395	uint8_t i2mod;
1396	uint8_t i2m_pad0[3];
1397	uint8_t i2add;
1398	uint8_t i2m_pad1[3];
1399	uint8_t i2brg;
1400	uint8_t i2m_pad2[3];
1401	uint8_t i2com;
1402	uint8_t i2m_pad3[3];
1403	uint8_t i2cer;
1404	uint8_t i2m_pad4[3];
1405	uint8_t i2cmr;
1406	uint8_t i2m_pad5[331];
1407
1408
1409	/*
1410	* CPM Block
1411	*/
1412	uint32_t cpcr;
1413	uint32_t rccr;
1414	uint8_t cpm_pad3[14];
1415	uint16_t rter;
1416	uint8_t cpm_pad[2];
1417	uint16_t rtmr;
1418	uint16_t rtscr;
1419	uint8_t cpm_pad4[2];
1420	uint32_t rtsr;
1421	uint8_t cpm_pad5[12];
1422
1423
1424	/*
1425	* BRG 1-4 Block
1426	*/
1427	uint32_t brgc1;
1428	uint32_t brgc2;
1429	uint32_t brgc3;
1430	uint32_t brgc4;
1431
1432
1433	/*
1434	* SCC Block
1435	*/
1436	m8260SCCRegisters_t scc1;
1437	m8260SCCRegisters_t scc2;
1438	m8260SCCRegisters_t scc3;
1439	m8260SCCRegisters_t scc4;
1440
1441
1442	/*
1443	* SMC Block
1444	*/
1445	m8260SMCRegisters_t smc1;
1446	m8260SMCRegisters_t smc2;
1447
1448
1449	/*
1450	* SPI Block
1451	*/
1452	uint16_t spmode;
1453	uint8_t spi_pad0[4];
1454	uint8_t spie;
1455	uint8_t spi_pad1[3];
1456	uint8_t spim;
1457	uint8_t spi_pad2[2];
1458	uint8_t spcom;
1459	uint8_t spi_pad3[82];
1460
1461
1462	/*
1463	* CPM Mux Block
1464	*/
1465	uint8_t cmxsi1cr;
1466	uint8_t cmx_pad0[1];
1467	uint8_t cmxsi2cr;
1468	uint8_t cmx_pad1[1];
1469	uint32_t cmxfcr;
1470	uint32_t cmxscr;
1471	uint8_t cmxsmr;
1472	uint8_t cmx_pad2[1];
1473	uint16_t cmxuar;
1474	uint8_t cmx_pad3[16];
1475
1476
1477	/*
1478	* SI & MCC Blocks
1479	*/
1480	m8260SIRegisters_t si1;
1481	m8260MCCRegisters_t mcc1;
1482	m8260SIRegisters_t si2;
1483	m8260MCCRegisters_t mcc2;
1484
1485	uint8_t mcc_pad0[1152];
1486
1487	/*
1488	* SI1 RAM
1489	*/
1490	uint8_t si1txram[512];
1491	uint8_t ram_pad0[512];
1492	uint8_t si1rxram[512];
1493	uint8_t ram_pad1[512];
1494
1495
1496	/*
1497	* SI2 RAM
1498	*/
1499	uint8_t si2txram[512];
1500	uint8_t ram_pad2[512];
1501	uint8_t si2rxram[512];
1502	uint8_t ram_pad3[512];
1503
1504
1505	} m8260_t;
1506
1507	extern volatile m8260_t m8260;
1508	#endif /* ASM */
1509
1510	#endif /* _MPC8260_H */

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source: rtems/bsps/powerpc/include/mpc8260.h @ abc2164

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