Context Navigation

source: rtems/bsps/powerpc/include/mpc8260.h

Last change on this file was 753873e5, checked in by Joel Sherrill <joel@…>, on 03/22/22 at 20:03:30
Update Eric Norum contact info and start to normalize file headers
Property mode set to `100644`
File size: 51.4 KB

Line
1	/* buggy version of CPU */
2	#define REV_0_2
3
4	/*
5	**************************************************************************
6	**************************************************************************
7
8	MOTOROLA MPC8260 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER
9	POWERQUICC II
10
11	HARDWARE DECLARATIONS
12
13
14	Submitted by:
15	Andy Dachs **
16	Surrey Satellite Technology Limited **
17	http://www.sstl.co.uk **
18	a.dachs@sstl.co.uk **
19
20	Based on previous submissions for other PPC variants by:
21
22	Submitted By:
23
24	Eric Norum <eric.norum.ca>
25
26	Modified for use with the MPC860 (original code was for MC68360)
27	by
28	Jay Monkman
29	Frasca International, Inc.
30	906 E. Airport Rd.
31	Urbana, IL, 61801
32
33	jmonkman@frasca.com
34
35
36	**************************************************************************
37	**************************************************************************
38	*/
39
40	#ifndef _MPC8260_H
41	#define _MPC8260_H
42
43	#ifndef ASM
44	/*
45	Macros for SPRs
46	*/
47
48
49
50
51	/*
52	*************************************************************************
53	* REGISTER SUBBLOCKS *
54	*************************************************************************
55	*/
56
57
58	/*
59	* Memory controller registers
60	*/
61	typedef struct m8260MEMCRegisters_ {
62	uint32_t br;
63	uint32_t _or; /* or is a C++ keyword :( */
64	} m8260MEMCRegisters_t;
65
66
67	/*
68	* Fast Communication Controller Registers
69	*/
70	typedef struct m8260FCCRegisters_ {
71	uint32_t gfmr;
72	uint32_t fpsmr;
73	uint16_t ftodr;
74	uint8_t fcc_pad0[2];
75	uint16_t fdsr;
76	uint8_t fcc_pad1[2];
77	uint32_t fcce;
78	uint32_t fccm;
79	uint8_t fccs;
80	uint8_t fcc_pad2[3];
81	uint8_t ftirr_phy0; /* n/a on FCC3 */
82	uint8_t ftirr_phy1; /* n/a on FCC3 */
83	uint8_t ftirr_phy2; /* n/a on FCC3 */
84	uint8_t ftirr_phy3; /* n/a on FCC3 */
85	} m8260FCCRegisters_t;
86
87
88	/*
89	* Serial Communications Controller registers
90	*/
91	typedef struct m8260SCCRegisters_ {
92	uint32_t gsmr_l;
93	uint32_t gsmr_h;
94	uint16_t psmr;
95	uint8_t scc_pad0[2];
96	uint16_t todr;
97	uint16_t dsr;
98	uint16_t scce;
99	uint8_t scc_pad2[2];
100	uint16_t sccm;
101	uint8_t scc_pad3[1];
102	uint8_t sccs;
103	uint8_t scc_pad1[8];
104	} m8260SCCRegisters_t;
105
106	/*
107	* Serial Management Controller registers
108	*/
109	typedef struct m8260SMCRegisters_ {
110	uint8_t smc_pad0[2];
111	uint16_t smcmr;
112	uint8_t smc_pad2[2];
113	uint8_t smce;
114	uint8_t smc_pad3[3];
115	uint8_t smcm;
116	uint8_t smc_pad1[5];
117	} m8260SMCRegisters_t;
118
119
120	/*
121	* Serial Interface With Time Slot Assigner Registers
122	*/
123	typedef struct m8260SIRegisters_ {
124	uint16_t siamr;
125	uint16_t sibmr;
126	uint16_t sicmr;
127	uint16_t sidmr;
128	uint8_t sigmr;
129	uint8_t si_pad0[1];
130	uint8_t sicmdr;
131	uint8_t si_pad1[1];
132	uint8_t sistr;
133	uint8_t si_pad2[1];
134	uint16_t sirsr;
135	} m8260SIRegisters_t;
136
137
138	/*
139	* Multi Channel Controller registers
140	*/
141	typedef struct m8260MCCRegisters_ {
142	uint16_t mcce;
143	uint8_t mcc_pad2[2];
144	uint16_t mccm;
145	uint16_t mcc_pad0;
146	uint8_t mccf;
147	uint8_t mcc_pad1[7];
148	} m8260MCCRegisters_t;
149
150
151	/*
152	*************************************************************************
153	* RISC Timers *
154	*************************************************************************
155	*/
156	/*
157	typedef struct m8260TimerParms_ {
158	uint16_t tm_base;
159	uint16_t _tm_ptr;
160	uint16_t _r_tmr;
161	uint16_t _r_tmv;
162	uint32_t tm_cmd;
163	uint32_t tm_cnt;
164	} m8260TimerParms_t;
165	*/
166
167	/*
168	* RISC Controller Configuration Register (RCCR)
169	* All other bits in this register are reserved.
170	*/
171	#define M8260_RCCR_TIME (1<<31) /* Enable timer */
172	#define M8260_RCCR_TIMEP(x) ((x)<<24) /* Timer period */
173	#define M8260_RCCR_DR1M (1<<23) /* IDMA Rqst 1 Mode */
174	#define M8260_RCCR_DR2M (1<<22) /* IDMA Rqst 2 Mode */
175	#define M8260_RCCR_DR1QP(x) ((x)<<20) /* IDMA1 Rqst Priority */
176	#define M8260_RCCR_EIE (1<<19) /* External Interrupt Enable */
177	#define M8260_RCCR_SCD (1<<18) /* Scheduler Configuration */
178	#define M8260_RCCR_DR2QP(x) ((x)<<16) /* IDMA2 Rqst Priority */
179	#define M8260_RCCR_ERAM(x) ((x)<<13) /* Enable RAM Microcode */
180	#define M8260_RCCR_EDM1 (1<<11) /* DRQ1 Edge detect mode */
181	#define M8260_RCCR_EDM2 (1<<10) /* DRQ2 Edge detect mode */
182	#define M8260_RCCR_EDM3 (1<<9) /* DRQ3 Edge detect mode */
183	#define M8260_RCCR_EDM4 (1<<8) /* DRQ4 Edge detect mode */
184	#define M8260_RCCR_DR3M (1<<7) /* IDMA Rqst 1 Mode */
185	#define M8260_RCCR_DR4M (1<<6) /* IDMA Rqst 2 Mode */
186	#define M8260_RCCR_DR3QP(x) ((x)<<4) /* IDMA3 Rqst Priority */
187	#define M8260_RCCR_DEM12 (1<<3) /* DONE1,2 Edge detect mode */
188	#define M8260_RCCR_DEM34 (1<<2) /* DONE3,4 Edge detect mode */
189	#define M8260_RCCR_DR4QP(x) (x) /* IDMA4 Rqst Priority */
190
191
192
193	/*
194	* Command register
195	* Set up this register before issuing a M8260_CR_OP_SET_TIMER command.
196	*/
197	#if 0
198	#define M8260_TM_CMD_V (1<<31) /* Set to enable timer */
199	#define M8260_TM_CMD_R (1<<30) /* Set for automatic restart */
200	#define M8260_TM_CMD_PWM (1<<29) /* Set for PWM operation */
201	#define M8260_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
202	#define M8260_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
203	#endif
204
205	/*
206	*************************************************************************
207	* DMA Controllers *
208	*************************************************************************
209	*/
210	typedef struct m8260IDMAparms_ {
211	uint16_t ibase;
212	uint16_t dcm;
213	uint16_t ibdptr;
214	uint16_t dpr_buf;
215	uint16_t _buf_inv;
216	uint16_t ssmax;
217	uint16_t _dpr_in_ptr;
218	uint16_t sts;
219	uint16_t _dpr_out_ptr;
220	uint16_t seob;
221	uint16_t deob;
222	uint16_t dts;
223	uint16_t _ret_add;
224	uint16_t reserved;
225	uint32_t _bd_cnt;
226	uint32_t _s_ptr;
227	uint32_t _d_ptr;
228	uint32_t istate;
229	} m8260IDMAparms_t;
230
231
232	/*
233	*************************************************************************
234	* Serial Communication Controllers *
235	*************************************************************************
236	*/
237
238
239	typedef struct m8260SCCparms_ {
240	uint16_t rbase;
241	uint16_t tbase;
242	uint8_t rfcr;
243	uint8_t tfcr;
244	uint16_t mrblr;
245	uint32_t _rstate;
246	uint32_t _pad0;
247	uint16_t _rbptr;
248	uint16_t _pad1;
249	uint32_t _pad2;
250	uint32_t _tstate;
251	uint32_t _pad3;
252	uint16_t _tbptr;
253	uint16_t _pad4;
254	uint32_t _pad5;
255	uint32_t _rcrc;
256	uint32_t _tcrc;
257	union {
258	struct {
259	uint32_t _res0;
260	uint32_t _res1;
261	uint16_t max_idl;
262	uint16_t idlc;
263	uint16_t brkcr;
264	uint16_t parec;
265	uint16_t frmec;
266	uint16_t nosec;
267	uint16_t brkec;
268	uint16_t brklen;
269	uint16_t uaddr[2];
270	uint16_t rtemp;
271	uint16_t toseq;
272	uint16_t character[8];
273	uint16_t rccm;
274	uint16_t rccr;
275	uint16_t rlbc;
276	} uart;
277	struct {
278	uint32_t _pad0;
279	uint32_t c_mask;
280	uint32_t c_pres;
281	uint16_t disfc;
282	uint16_t crcec;
283	uint16_t abtsc;
284	uint16_t nmarc;
285	uint16_t retrc;
286	uint16_t mflr;
287	uint16_t _max_cnt;
288	uint16_t rfthr;
289	uint16_t _rfcnt;
290	uint16_t hmask;
291	uint16_t haddr1;
292	uint16_t haddr2;
293	uint16_t haddr3;
294	uint16_t haddr4;
295	uint16_t _tmp;
296	uint16_t _tmp_mb;
297	} hdlc;
298	struct {
299	uint32_t _pad0;
300	uint32_t crcc;
301	uint16_t prcrc;
302	uint16_t ptcrc;
303	uint16_t parec;
304	uint16_t bsync;
305	uint16_t bdle;
306	uint16_t character[8];
307	uint16_t rccm;
308	} bisync;
309	struct {
310	uint32_t _crc_p;
311	uint32_t _crc_c;
312	} transparent;
313	struct {
314	uint32_t c_pres;
315	uint32_t c_mask;
316	uint32_t crcec;
317	uint32_t alec;
318	uint32_t disfc;
319	uint16_t pads;
320	uint16_t ret_lim;
321	uint16_t _ret_cnt;
322	uint16_t mflr;
323	uint16_t minflr;
324	uint16_t maxd1;
325	uint16_t maxd2;
326	uint16_t _maxd;
327	uint16_t _dma_cnt;
328	uint16_t _max_b;
329	uint16_t gaddr1;
330	uint16_t gaddr2;
331	uint16_t gaddr3;
332	uint16_t gaddr4;
333	uint32_t _tbuf0data0;
334	uint32_t _tbuf0data1;
335	uint32_t _tbuf0rba0;
336	uint32_t _tbuf0crc;
337	uint16_t _tbuf0bcnt;
338	uint16_t paddr_h;
339	uint16_t paddr_m;
340	uint16_t paddr_l;
341	uint16_t p_per;
342	uint16_t _rfbd_ptr;
343	uint16_t _tfbd_ptr;
344	uint16_t _tlbd_ptr;
345	uint32_t _tbuf1data0;
346	uint32_t _tbuf1data1;
347	uint32_t _tbuf1rba0;
348	uint32_t _tbuf1crc;
349	uint16_t _tbuf1bcnt;
350	uint16_t _tx_len;
351	uint16_t iaddr1;
352	uint16_t iaddr2;
353	uint16_t iaddr3;
354	uint16_t iaddr4;
355	uint16_t _boff_cnt;
356	uint16_t taddr_l;
357	uint16_t taddr_m;
358	uint16_t taddr_h;
359	} ethernet;
360	} un;
361	} m8260SCCparms_t;
362
363
364	/*
365	* Event and mask registers (SCCE, SCCM)
366	*/
367	#define M8260_SCCE_BRKE (1<<6)
368	#define M8260_SCCE_BRK (1<<5)
369	#define M8260_SCCE_TXE (1<<4)
370	#define M8260_SCCE_RXF (1<<3)
371	#define M8260_SCCE_BSY (1<<2)
372	#define M8260_SCCE_TX (1<<1)
373	#define M8260_SCCE_RX (1<<0)
374
375
376	/*
377	*************************************************************************
378	* Fast Serial Communication Controllers *
379	*************************************************************************
380	*/
381
382
383	typedef struct m8260FCCparms_ {
384	uint16_t riptr;
385	uint16_t tiptr;
386	uint16_t _pad0;
387	uint16_t mrblr;
388	uint32_t rstate;
389	uint32_t rbase;
390	uint16_t _rbdstat;
391	uint16_t _rbdlen;
392	uint32_t _rdptr;
393	uint32_t tstate;
394	uint32_t tbase;
395	uint16_t _tbdstat;
396	uint16_t _tbdlen;
397	uint32_t _tdptr;
398	uint32_t _rbptr;
399	uint32_t _tbptr;
400	uint32_t _rcrc;
401	uint32_t _pad1;
402	uint32_t _tcrc;
403
404	union {
405	struct {
406	uint32_t _pad0;
407	uint32_t _pad1;
408	uint32_t c_mask;
409	uint32_t c_pres;
410	uint16_t disfc;
411	uint16_t crcec;
412	uint16_t abtsc;
413	uint16_t nmarc;
414	uint32_t _max_cnt;
415	uint16_t mflr;
416	uint16_t rfthr;
417	uint16_t rfcnt;
418	uint16_t hmask;
419	uint16_t haddr1;
420	uint16_t haddr2;
421	uint16_t haddr3;
422	uint16_t haddr4;
423	uint16_t _ts_tmp;
424	uint16_t _tmp_mb;
425	} hdlc;
426	struct {
427	uint32_t _pad0;
428	uint32_t _pad1;
429	uint32_t c_mask;
430	uint32_t c_pres;
431	uint16_t disfc;
432	uint16_t crcec;
433	uint16_t abtsc;
434	uint16_t nmarc;
435	uint32_t _max_cnt;
436	uint16_t mflr;
437	uint16_t rfthr;
438	uint16_t rfcnt;
439	uint16_t hmask;
440	uint16_t haddr1;
441	uint16_t haddr2;
442	uint16_t haddr3;
443	uint16_t haddr4;
444	uint16_t _ts_tmp;
445	uint16_t _tmp_mb;
446	} transparent;
447	struct {
448	uint32_t _stat_buf;
449	uint32_t cam_ptr;
450	uint32_t c_mask;
451	uint32_t c_pres;
452	uint32_t crcec;
453	uint32_t alec;
454	uint32_t disfc;
455	uint16_t ret_lim;
456	uint16_t _ret_cnt;
457	uint16_t p_per;
458	uint16_t _boff_cnt;
459	uint32_t gaddr_h;
460	uint32_t gaddr_l;
461	uint16_t tfcstat;
462	uint16_t tfclen;
463	uint32_t tfcptr;
464	uint16_t mflr;
465	uint16_t paddr1_h;
466	uint16_t paddr1_m;
467	uint16_t paddr1_l;
468	uint16_t _ibd_cnt;
469	uint16_t _ibd_start;
470	uint16_t _ibd_end;
471	uint16_t _tx_len;
472	uint16_t _ibd_base;
473	uint32_t iaddr_h;
474	uint32_t iaddr_l;
475	uint16_t minflr;
476	uint16_t taddr_h;
477	uint16_t taddr_m;
478	uint16_t taddr_l;
479	uint16_t pad_ptr;
480	uint16_t _pad0;
481	uint16_t _cf_range;
482	uint16_t _max_b;
483	uint16_t maxd1;
484	uint16_t maxd2;
485	uint16_t _maxd;
486	uint16_t _dma_cnt;
487	uint32_t octc;
488	uint32_t colc;
489	uint32_t broc;
490	uint32_t mulc;
491	uint32_t uspc;
492	uint32_t frgc;
493	uint32_t ospc;
494	uint32_t jbrc;
495	uint32_t p64c;
496	uint32_t p65c;
497	uint32_t p128c;
498	uint32_t p256c;
499	uint32_t p512c;
500	uint32_t p1024c;
501	uint32_t _cam_buf;
502	uint32_t _pad1;
503	} ethernet;
504	} un;
505	} m8260FCCparms_t;
506
507
508	/*
509	* Receive and transmit function code register bits
510	* These apply to the function code registers of all devices, not just SCC.
511	*/
512	#define M8260_RFCR_BO(x) ((x)<<3)
513	#define M8260_RFCR_MOT (2<<3)
514	#define M8260_RFCR_LOCAL_BUS (2)
515	#define M8260_RFCR_60X_BUS (0)
516	#define M8260_TFCR_BO(x) ((x)<<3)
517	#define M8260_TFCR_MOT (2<<3)
518	#define M8260_TFCR_LOCAL_BUS (2)
519	#define M8260_TFCR_60X_BUS (0)
520
521	/*
522	*************************************************************************
523	* Serial Management Controllers *
524	*************************************************************************
525	*/
526	typedef struct m8260SMCparms_ {
527	uint16_t rbase;
528	uint16_t tbase;
529	uint8_t rfcr;
530	uint8_t tfcr;
531	uint16_t mrblr;
532	uint32_t _rstate;
533	uint32_t _pad0;
534	uint16_t _rbptr;
535	uint16_t _pad1;
536	uint32_t _pad2;
537	uint32_t _tstate;
538	uint32_t _pad3;
539	uint16_t _tbptr;
540	uint16_t _pad4;
541	uint32_t _pad5;
542	union {
543	struct {
544	uint16_t max_idl;
545	uint16_t _idlc;
546	uint16_t _brkln;
547	uint16_t brkec;
548	uint16_t brkcr;
549	uint16_t _r_mask;
550	} uart;
551	struct {
552	uint16_t _pad0[6];
553	} transparent;
554	} un;
555	uint32_t _pad6;
556	} m8260SMCparms_t;
557
558	/*
559	* Mode register
560	*/
561	#define M8260_SMCMR_CLEN(x) ((x)<<11) /* Character length */
562	#define M8260_SMCMR_2STOP (1<<10) /* 2 stop bits */
563	#define M8260_SMCMR_PARITY (1<<9) /* Enable parity */
564	#define M8260_SMCMR_EVEN (1<<8) /* Even parity */
565	#define M8260_SMCMR_SM_GCI (0<<4) /* GCI Mode */
566	#define M8260_SMCMR_SM_UART (2<<4) /* UART Mode */
567	#define M8260_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
568	#define M8260_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
569	#define M8260_SMCMR_DM_ECHO (2<<2) /* Echo mode */
570	#define M8260_SMCMR_TEN (1<<1) /* Enable transmitter */
571	#define M8260_SMCMR_REN (1<<0) /* Enable receiver */
572
573	/*
574	* Event and mask registers (SMCE, SMCM)
575	*/
576	#define M8260_SMCE_TXE (1<<4)
577	#define M8260_SMCE_BSY (1<<2)
578	#define M8260_SMCE_TX (1<<1)
579	#define M8260_SMCE_RX (1<<0)
580
581	/*
582	*************************************************************************
583	* Serial Peripheral Interface *
584	*************************************************************************
585	*/
586	typedef struct m8260SPIparms_ {
587	uint16_t rbase;
588	uint16_t tbase;
589	uint8_t rfcr;
590	uint8_t tfcr;
591	uint16_t mrblr;
592	uint32_t _rstate;
593	uint32_t _pad0;
594	uint16_t _rbptr;
595	uint16_t _pad1;
596	uint32_t _pad2;
597	uint32_t _tstate;
598	uint32_t _pad3;
599	uint16_t _tbptr;
600	uint16_t _pad4;
601	uint32_t _pad5;
602	} m8260SPIparms_t;
603
604	/*
605	* Mode register (SPMODE)
606	*/
607	#define M8260_SPMODE_LOOP (1<<14) /* Local loopback mode */
608	#define M8260_SPMODE_CI (1<<13) /* Clock invert */
609	#define M8260_SPMODE_CP (1<<12) /* Clock phase */
610	#define M8260_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
611	#define M8260_SPMODE_REV (1<<10) /* Reverse data */
612	#define M8260_SPMODE_MASTER (1<<9) /* SPI is master */
613	#define M8260_SPMODE_EN (1<<8) /* Enable SPI */
614	#define M8260_SPMODE_CLEN(x) ((x)<<4) /* Character length */
615	#define M8260_SPMODE_PM(x) (x) /* Prescaler modulus */
616
617	/*
618	* Mode register (SPCOM)
619	*/
620	#define M8260_SPCOM_STR (1<<7) /* Start transmit */
621
622	/*
623	* Event and mask registers (SPIE, SPIM)
624	*/
625	#define M8260_SPIE_MME (1<<5) /* Multi-master error */
626	#define M8260_SPIE_TXE (1<<4) /* Tx error */
627	#define M8260_SPIE_BSY (1<<2) /* Busy condition*/
628	#define M8260_SPIE_TXB (1<<1) /* Tx buffer */
629	#define M8260_SPIE_RXB (1<<0) /* Rx buffer */
630
631	/*
632	*************************************************************************
633	* SDMA (SCC, SMC, SPI) Buffer Descriptors *
634	*************************************************************************
635	*/
636	typedef struct m8260BufferDescriptor_ {
637	uint16_t status;
638	uint16_t length;
639	volatile void *buffer;
640	} m8260BufferDescriptor_t;
641
642	/*
643	* Bits in receive buffer descriptor status word
644	*/
645	#define M8260_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
646	#define M8260_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
647	#define M8260_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
648	#define M8260_BD_LAST (1<<11) /* Ethernet, SPI */
649	#define M8260_BD_CONTROL_CHAR (1<<11) /* SCC UART */
650	#define M8260_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
651	#define M8260_BD_ADDRESS (1<<10) /* SCC UART */
652	#define M8260_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
653	#define M8260_BD_MISS (1<<8) /* Ethernet */
654	#define M8260_BD_IDLE (1<<8) /* SCC UART, SMC UART */
655	#define M8260_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
656	#define M8260_BD_LONG (1<<5) /* Ethernet, SCC HDLC */
657	#define M8260_BD_BREAK (1<<5) /* SCC UART, SMC UART */
658	#define M8260_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */
659	#define M8260_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
660	#define M8260_BD_SHORT (1<<3) /* Ethernet */
661	#define M8260_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
662	#define M8260_BD_ABORT (1<<3) /* SCC HDLC */
663	#define M8260_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */
664	#define M8260_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
665	#define M8260_BD_COLLISION (1<<0) /* Ethernet */
666	#define M8260_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */
667	#define M8260_BD_MASTER_ERROR (1<<0) /* SPI */
668
669	#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
670	#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
671	#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
672	#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */
673	#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */
674	#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
675	#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */
676	#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
677	#define M8xx_BD_MISS (1<<8) /* Ethernet */
678	#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */
679	#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
680	#define M8xx_BD_LONG (1<<5) /* Ethernet, SCC HDLC */
681	#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */
682	#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */
683	#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
684	#define M8xx_BD_SHORT (1<<3) /* Ethernet */
685	#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
686	#define M8xx_BD_ABORT (1<<3) /* SCC HDLC */
687	#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */
688	#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
689	#define M8xx_BD_COLLISION (1<<0) /* Ethernet */
690	#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */
691	#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */
692
693	/*
694	* Bits in transmit buffer descriptor status word
695	* Many bits have the same meaning as those in receiver buffer descriptors.
696	*/
697	#define M8260_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
698	#define M8260_BD_PAD (1<<14) /* Ethernet */
699	#define M8260_BD_CTS_REPORT (1<<11) /* SCC UART */
700	#define M8260_BD_TX_CRC (1<<10) /* Ethernet */
701	#define M8260_BD_DEFER (1<<9) /* Ethernet */
702	#define M8260_BD_HEARTBEAT (1<<8) /* Ethernet */
703	#define M8260_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
704	#define M8260_BD_LATE_COLLISION (1<<7) /* Ethernet */
705	#define M8260_BD_NO_STOP_BIT (1<<7) /* SCC UART */
706	#define M8260_BD_RETRY_LIMIT (1<<6) /* Ethernet */
707	#define M8260_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
708	#define M8260_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */
709	#define M8260_BD_CARRIER_LOST (1<<0) /* Ethernet */
710	#define M8260_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */
711
712	#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
713	#define M8xx_BD_PAD (1<<14) /* Ethernet */
714	#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */
715	#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */
716	#define M8xx_BD_DEFER (1<<9) /* Ethernet */
717	#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */
718	#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
719	#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */
720	#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */
721	#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */
722	#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
723	#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */
724	#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */
725	#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */
726
727	/*
728	*************************************************************************
729	* IDMA Buffer Descriptors *
730	*************************************************************************
731	*/
732	typedef struct m8260IDMABufferDescriptor_ {
733	uint16_t status;
734	uint8_t dfcr;
735	uint8_t sfcr;
736	uint32_t length;
737	void *source;
738	void *destination;
739	} m8260IDMABufferDescriptor_t;
740
741	/*
742	*************************************************************************
743	* RISC Communication Processor Module Command Register (CR) *
744	*************************************************************************
745	*/
746	#define M8260_CR_RST (1<<31) /* Reset communication processor */
747
748	#define M8260_CR_FCC1 ((4<<26)\|(16<<21)) /* FCC1 page and code */
749	#define M8260_CR_FCC1_ATM ((4<<26)\|(14<<21)) /* FCC1 ATM mode page and code */
750	#define M8260_CR_FCC2 ((5<<26)\|(17<<21)) /* FCC2 page and code */
751	#define M8260_CR_FCC2_ATM ((5<<26)\|(14<<21)) /* FCC2 ATM mode page and code */
752	#define M8260_CR_FCC3 ((6<<26)\|(18<<21)) /* FCC3 page and code */
753	#define M8260_CR_SCC1 ((0<<26)\|(4<<21)) /* SCC1 page and code */
754	#define M8260_CR_SCC2 ((1<<26)\|(5<<21)) /* SCC2 page and code */
755	#define M8260_CR_SCC3 ((2<<26)\|(6<<21)) /* SCC3 page and code */
756	#define M8260_CR_SCC4 ((3<<26)\|(7<<21)) /* SCC4 page and code */
757	#define M8260_CR_SMC1 ((7<<26)\|(8<<21)) /* SMC1 page and code */
758	#define M8260_CR_SMC2 ((8<<26)\|(9<<21)) /* SMC2 page and code */
759	#define M8260_CR_RAND ((10<<26)\|(14<<21)) /* SMC2 page and code */
760	#define M8260_CR_SPI ((9<<26)\|(10<<21)) /* SPI page and code */
761	#define M8260_CR_I2C ((10<<26)\|(11<<21)) /* I2C page and code */
762	#define M8260_CR_TMR ((10<<26)\|(15<<21)) /* Timer page and code */
763	#define M8260_CR_MCC1 ((7<<26)\|(28<<21)) /* MCC1 page and code */
764	#define M8260_CR_MCC2 ((8<<26)\|(29<<21)) /* MCC2 page and code */
765	#define M8260_CR_IDMA1 ((7<<26)\|(20<<21)) /* IDMA1 page and code */
766	#define M8260_CR_IDMA2 ((8<<26)\|(21<<21)) /* IDMA2 page and code */
767	#define M8260_CR_IDMA3 ((9<<26)\|(22<<21)) /* IDMA3 page and code */
768	#define M8260_CR_IDMA4 ((10<<26)\|(23<<21)) /* IDMA4 page and code */
769
770	#define M8260_CR_FLG (1<<16) /* Command sempahore flag */
771
772	#define M8260_CR_MCC_CHAN(x) ((x)<<6) /* MCC channel number */
773	#define M8260_CR_FCC_HDLC (0<<6) /* FCC HDLC/Transparent protocol code */
774	#define M8260_CR_FCC_ATM (10<<6) /* FCC ATM protocol code */
775	#define M8260_CR_FCC_ETH (12<<6) /* FCC Ethernet protocol code */
776
777	#define M8260_CR_OP_INIT_RX_TX (0) /* FCC, SCC, SMC UART, SMC GCI, SPI, I2C, MCC */
778	#define M8260_CR_OP_INIT_RX (1) /* FCC, SCC, SMC UART, SPI, I2C, MCC */
779	#define M8260_CR_OP_INIT_TX (2) /* FCC, SCC, SMC UART, SPI, I2C, MCC */
780	#define M8260_CR_OP_INIT_HUNT (3) /* FCC, SCC, SMC UART */
781	#define M8260_CR_OP_STOP_TX (4) /* FCC, SCC, SMC UART, MCC */
782	#define M8260_CR_OP_GR_STOP_TX (5) /* FCC, SCC */
783	#define M8260_CR_OP_RESTART_TX (6) /* FCC, SCC, SMC UART */
784	#define M8260_CR_OP_CLOSE_RX_BD (7) /* FCC, SCC, SMC UART, SPI, I2C */
785	#define M8260_CR_OP_SET_GRP_ADDR (8) /* FCC, SCC */
786	#define M8260_CR_OP_SET_TIMER (8) /* Timer */
787	#define M8260_CR_OP_GCI_TIMEOUT (9) /* SMC GCI */
788	#define M8260_CR_OP_START_IDMA (9) /* IDMA */
789	#define M8260_CR_OP_STOP_RX (9) /* MCC */
790	#define M8260_CR_OP_ATM_TX (10) /* FCC */
791	#define M8260_CR_OP_RESET_BCS (10) /* SCC */
792	#define M8260_CR_OP_GCI_ABORT (10) /* SMC GCI */
793	#define M8260_CR_OP_STOP_IDMA (11) /* IDMA */
794	#define M8260_CR_OP_RANDOM (12) /* RAND */
795
796	/*
797	*************************************************************************
798	* System Protection Control Register (SYPCR) *
799	*************************************************************************
800	*/
801	#define M8260_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */
802	#define M8260_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
803	#define M8260_SYPCR_BME (1<<7) /* Bus monitor enable */
804	#define M8260_SYPCR_SWF (1<<3) /* Software watchdog freeze */
805	#define M8260_SYPCR_SWE (1<<2) /* Software watchdog enable */
806	#define M8260_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
807	#define M8260_SYPCR_SWP (1<<0) /* Software watchdog prescale */
808
809	/*
810	*************************************************************************
811	* Memory Control Registers *
812	*************************************************************************
813	*/
814	#define M8260_UPM_AMX_8col (0<<20) /* 8 column DRAM */
815	#define M8260_UPM_AMX_9col (1<<20) /* 9 column DRAM */
816	#define M8260_UPM_AMX_10col (2<<20) /* 10 column DRAM */
817	#define M8260_UPM_AMX_11col (3<<20) /* 11 column DRAM */
818	#define M8260_UPM_AMX_12col (4<<20) /* 12 column DRAM */
819	#define M8260_UPM_AMX_13col (5<<20) /* 13 column DRAM */
820	#define M8260_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */
821	#define M8260_MSR_WPER (1<<7) /* Write protection error */
822	#define M8260_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */
823	#define M8260_BR_BA(x) ((x)&0xffff8000) /* Base address */
824	#define M8260_BR_AT(x) ((x)<<12) /* Address type */
825	#define M8260_BR_PS8 (1<<10) /* 8 bit port */
826	#define M8260_BR_PS16 (2<<10) /* 16 bit port */
827	#define M8260_BR_PS32 (0<<10) /* 32 bit port */
828	#define M8260_BR_PARE (1<<9) /* Parity checking enable */
829	#define M8260_BR_WP (1<<8) /* Write protect */
830	#define M8260_BR_MS_GPCM (0<<6) /* GPCM */
831	#define M8260_BR_MS_UPMA (2<<6) /* UPM A */
832	#define M8260_BR_MS_UPMB (3<<6) /* UPM B */
833	#define M8260_MEMC_BR_V (1<<0) /* Base/Option register are valid */
834
835	#define M8260_MEMC_OR_32K 0xffff8000 /* Address range */
836	#define M8260_MEMC_OR_64K 0xffff0000
837	#define M8260_MEMC_OR_128K 0xfffe0000
838	#define M8260_MEMC_OR_256K 0xfffc0000
839	#define M8260_MEMC_OR_512K 0xfff80000
840	#define M8260_MEMC_OR_1M 0xfff00000
841	#define M8260_MEMC_OR_2M 0xffe00000
842	#define M8260_MEMC_OR_4M 0xffc00000
843	#define M8260_MEMC_OR_8M 0xff800000
844	#define M8260_MEMC_OR_16M 0xff000000
845	#define M8260_MEMC_OR_32M 0xfe000000
846	#define M8260_MEMC_OR_64M 0xfc000000
847	#define M8260_MEMC_OR_128 0xf8000000
848	#define M8260_MEMC_OR_256M 0xf0000000
849	#define M8260_MEMC_OR_512M 0xe0000000
850	#define M8260_MEMC_OR_1G 0xc0000000
851	#define M8260_MEMC_OR_2G 0x80000000
852	#define M8260_MEMC_OR_4G 0x00000000
853	#define M8260_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */
854	#define M8260_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */
855	#define M8260_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */
856	#define M8260_MEMC_OR_ACS_NORM (0<<9) /* CS asserted with addr lines /
857	#define M8260_MEMC_OR_ACS_QRTR (2<<9) /* CS asserted 1/4 after addr /
858	#define M8260_MEMC_OR_ACS_HALF (3<<9) /* CS asserted 1/2 after addr /
859	#define M8260_MEMC_OR_BI (1<8) /* Burst inhibit */
860	#define M8260_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */
861	#define M8260_MEMC_OR_SETA (1<<3) /* TA generated externally /
862	#define M8260_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */
863	#define M8260_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */
864
865	/*
866	*************************************************************************
867	* UPM Registers (MxMR) *
868	*************************************************************************
869	*/
870	#define M8260_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */
871	#define M8260_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */
872	#define M8260_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */
873	#define M8260_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */
874	#define M8260_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */
875	#define M8260_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */
876	#define M8260_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */
877	#define M8260_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */
878	/*
879	*************************************************************************
880	* Memory Command Register (MCR) *
881	*************************************************************************
882	*/
883	#define M8260_MEMC_MCR_WRITE (0<<30) /* WRITE command */
884	#define M8260_MEMC_MCR_READ (1<<30) /* READ command */
885	#define M8260_MEMC_MCR_RUN (2<<30) /* RUN command */
886	#define M8260_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */
887	#define M8260_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */
888	#define M8260_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */
889	#define M8260_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */
890	#define M8260_MEMC_MCR_MAD(x) (x) /* Machine address */
891
892
893
894	/*
895	*************************************************************************
896	* SI Mode Register (SIMODE) *
897	*************************************************************************
898	*/
899	#define M8260_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
900	#define M8260_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
901	#define M8260_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
902	#define M8260_SI_SMC2_BRG2 (1<<28)
903	#define M8260_SI_SMC2_BRG3 (2<<28)
904	#define M8260_SI_SMC2_BRG4 (3<<28)
905	#define M8260_SI_SMC2_CLK5 (0<<28)
906	#define M8260_SI_SMC2_CLK6 (1<<28)
907	#define M8260_SI_SMC2_CLK7 (2<<28)
908	#define M8260_SI_SMC2_CLK8 (3<<28)
909	#define M8260_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
910	#define M8260_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
911	#define M8260_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
912	#define M8260_SI_SMC1_BRG2 (1<<12)
913	#define M8260_SI_SMC1_BRG3 (2<<12)
914	#define M8260_SI_SMC1_BRG4 (3<<12)
915	#define M8260_SI_SMC1_CLK1 (0<<12)
916	#define M8260_SI_SMC1_CLK2 (1<<12)
917	#define M8260_SI_SMC1_CLK3 (2<<12)
918	#define M8260_SI_SMC1_CLK4 (3<<12)
919
920	/*
921	*************************************************************************
922	* SDMA Configuration Register (SDCR) *
923	*************************************************************************
924	*/
925	#define M8260_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */
926	#define M8260_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */
927
928	/*
929	*************************************************************************
930	* SDMA Status Register (SDSR) *
931	*************************************************************************
932	*/
933	#define M8260_SDSR_SBER (1<<7) /* SDMA Channel bus error */
934	#define M8260_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */
935	#define M8260_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */
936
937	/*
938	*************************************************************************
939	* Baud (sic) Rate Generators *
940	*************************************************************************
941	*/
942	#define M8260_BRG_RST (1<<17) /* Reset generator */
943	#define M8260_BRG_EN (1<<16) /* Enable generator */
944	#define M8260_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
945	#define M8260_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
946	#define M8260_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
947	#define M8260_BRG_ATB (1<<13) /* Autobaud */
948	#define M8260_BRG_115200 (21<<1) /* Assume 40 MHz clock */
949	#define M8260_BRG_57600 (32<<1)
950	#define M8260_BRG_38400 (64<<1)
951	#define M8260_BRG_19200 (129<<1)
952	#define M8260_BRG_9600 (259<<1)
953	#define M8260_BRG_4800 (520<<1)
954	#define M8260_BRG_2400 (1040<<1)
955	#define M8260_BRG_1200 (2082<<1)
956	#define M8260_BRG_600 ((259<<1) \| 1)
957	#define M8260_BRG_300 ((520<<1) \| 1)
958	#define M8260_BRG_150 ((1040<<1) \| 1)
959	#define M8260_BRG_75 ((2080<<1) \| 1)
960
961	#define M8xx_BRG_RST (1<<17) /* Reset generator */
962	#define M8xx_BRG_EN (1<<16) /* Enable generator */
963	#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
964
965	#define M8260_BRG1 (1<<7)
966	#define M8260_BRG2 (1<<6)
967	#define M8260_BRG3 (1<<5)
968	#define M8260_BRG4 (1<<4)
969	#define M8260_BRG5 (1<<3)
970	#define M8260_BRG6 (1<<2)
971	#define M8260_BRG7 (1<<1)
972	#define M8260_BRG8 (1<<0)
973
974
975
976	#define M8260_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */
977	#define M8260_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */
978	#define M8260_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */
979	#define M8260_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */
980	#define M8260_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */
981	#define M8260_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */
982	#define M8260_TGCR_STP1 (1<<1) /* Stop timer */
983	#define M8260_TGCR_STP2 (1<<5) /* Stop timer */
984	#define M8260_TGCR_STP3 (1<<9) /* Stop timer */
985	#define M8260_TGCR_STP4 (1<<13) /* Stop timer */
986	#define M8260_TGCR_RST1 (1<<0) /* Enable timer */
987	#define M8260_TGCR_RST2 (1<<4) /* Enable timer */
988	#define M8260_TGCR_RST3 (1<<8) /* Enable timer */
989	#define M8260_TGCR_RST4 (1<<12) /* Enable timer */
990	#define M8260_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */
991	#define M8260_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */
992
993	#define M8260_TMR_PS(x) ((x)<<8) /* Timer prescaler */
994	#define M8260_TMR_CE_RISE (1<<6) /* Capture on rising edge */
995	#define M8260_TMR_CE_FALL (2<<6) /* Capture on falling edge */
996	#define M8260_TMR_CE_ANY (3<<6) /* Capture on any edge */
997	#define M8260_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */
998	#define M8260_TMR_ORI (1<<4) /* Interrupt on reaching reference */
999	#define M8260_TMR_RESTART (1<<3) /* Restart timer after reference */
1000	#define M8260_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */
1001	#define M8260_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */
1002	#define M8260_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */
1003	#define M8260_TMR_TGATE (1<<0) /* TGATE controls timer */
1004
1005	#ifdef REV_0_2
1006	#define M8260_PISCR_PS (1<<6) /* PIT Interrupt state */
1007	#else
1008	#define M8260_PISCR_PS (1<<7) /* PIT Interrupt state */
1009	#endif
1010	#define M8260_PISCR_PIE (1<<2) /* PIT interrupt enable */
1011	#define M8260_PISCR_PTF (1<<1) /* Stop timer when freeze asserted */
1012	#define M8260_PISCR_PTE (1<<0) /* PIT enable */
1013
1014	#if 0
1015	#define M8260_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */
1016	#define M8260_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */
1017	#define M8260_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */
1018	#define M8260_TBSCR_REFAE (1<<3) /* Enable ints for REFA */
1019	#define M8260_TBSCR_REFBE (1<<2) /* Enable ints for REFB */
1020	#define M8260_TBSCR_TBF (1<<1) /* TB stops on FREEZE */
1021	#define M8260_TBSCR_TBE (1<<0) /* enable TB and decrementer */
1022	#endif
1023
1024	#define M8260_TMCNTSC_SEC (1<<7) /* per second flag */
1025	#define M8260_TMCNTSC_ALR (1<<6) /* Alarm interrupt flag */
1026	#define M8260_TMCNTSC_SIE (1<<3) /* per second interrupt enable */
1027	#define M8260_TMCNTSC_ALE (1<<2) /* Alarm interrupt enable */
1028	#define M8260_TMCNTSC_TCF (1<<1) /* Time count frequency */
1029	#define M8260_TMCNTSC_TCE (1<<0) /* Time count enable */
1030
1031	#define M8260_SIMASK_PC0 (1<<31)
1032	#define M8260_SIMASK_PC1 (1<<30)
1033	#define M8260_SIMASK_PC2 (1<<29)
1034	#define M8260_SIMASK_PC3 (1<<28)
1035	#define M8260_SIMASK_PC4 (1<<27)
1036	#define M8260_SIMASK_PC5 (1<<26)
1037	#define M8260_SIMASK_PC6 (1<<25)
1038	#define M8260_SIMASK_PC7 (1<<24)
1039	#define M8260_SIMASK_PC8 (1<<23)
1040	#define M8260_SIMASK_PC9 (1<<22)
1041	#define M8260_SIMASK_PC10 (1<<21)
1042	#define M8260_SIMASK_PC11 (1<<20)
1043	#define M8260_SIMASK_PC12 (1<<19)
1044	#define M8260_SIMASK_PC13 (1<<18)
1045	#define M8260_SIMASK_PC14 (1<<17)
1046	#define M8260_SIMASK_PC15 (1<<16)
1047	#define M8260_SIMASK_IRQ1 (1<<14)
1048	#define M8260_SIMASK_IRQ2 (1<<13)
1049	#define M8260_SIMASK_IRQ3 (1<<12)
1050	#define M8260_SIMASK_IRQ4 (1<<11)
1051	#define M8260_SIMASK_IRQ5 (1<<10)
1052	#define M8260_SIMASK_IRQ6 (1<<9)
1053	#define M8260_SIMASK_IRQ7 (1<<8)
1054	#define M8260_SIMASK_TMCNT (1<<2)
1055	#define M8260_SIMASK_PIT (1<<1)
1056
1057	#define M8260_SIMASK_FCC1 (1<<31)
1058	#define M8260_SIMASK_FCC2 (1<<30)
1059	#define M8260_SIMASK_FCC3 (1<<29)
1060	#define M8260_SIMASK_MCC1 (1<<27)
1061	#define M8260_SIMASK_MCC2 (1<<26)
1062	#define M8260_SIMASK_SCC1 (1<<23)
1063	#define M8260_SIMASK_SCC2 (1<<22)
1064	#define M8260_SIMASK_SCC3 (1<<21)
1065	#define M8260_SIMASK_SCC4 (1<<20)
1066	#define M8260_SIMASK_I2C (1<<15)
1067	#define M8260_SIMASK_SPI (1<<14)
1068	#define M8260_SIMASK_RTT (1<<13)
1069	#define M8260_SIMASK_SMC1 (1<<12)
1070	#define M8260_SIMASK_SMC2 (1<<11)
1071	#define M8260_SIMASK_IDMA1 (1<<10)
1072	#define M8260_SIMASK_IDMA2 (1<<9)
1073	#define M8260_SIMASK_IDMA3 (1<<8)
1074	#define M8260_SIMASK_IDMA4 (1<<7)
1075	#define M8260_SIMASK_SDMA (1<<6)
1076	#define M8260_SIMASK_TIMER1 (1<<4)
1077	#define M8260_SIMASK_TIMER2 (1<<3)
1078	#define M8260_SIMASK_TIMER3 (1<<2)
1079	#define M8260_SIMASK_TIMER4 (1<<1)
1080
1081	#define M8260_SIUMCR_EARB (1<<31)
1082	#define M8260_SIUMCR_EARP0 (0<<28)
1083	#define M8260_SIUMCR_EARP1 (1<<28)
1084	#define M8260_SIUMCR_EARP2 (2<<28)
1085	#define M8260_SIUMCR_EARP3 (3<<28)
1086	#define M8260_SIUMCR_EARP4 (4<<28)
1087	#define M8260_SIUMCR_EARP5 (5<<28)
1088	#define M8260_SIUMCR_EARP6 (6<<28)
1089	#define M8260_SIUMCR_EARP7 (7<<28)
1090	#define M8260_SIUMCR_DSHW (1<<23)
1091	#define M8260_SIUMCR_DBGC0 (0<<21)
1092	#define M8260_SIUMCR_DBGC1 (1<<21)
1093	#define M8260_SIUMCR_DBGC2 (2<<21)
1094	#define M8260_SIUMCR_DBGC3 (3<<21)
1095	#define M8260_SIUMCR_DBPC0 (0<<19)
1096	#define M8260_SIUMCR_DBPC1 (1<<19)
1097	#define M8260_SIUMCR_DBPC2 (2<<19)
1098	#define M8260_SIUMCR_DBPC3 (3<<19)
1099	#define M8260_SIUMCR_FRC (1<<17)
1100	#define M8260_SIUMCR_DLK (1<<16)
1101	#define M8260_SIUMCR_PNCS (1<<15)
1102	#define M8260_SIUMCR_OPAR (1<<14)
1103	#define M8260_SIUMCR_DPC (1<<13)
1104	#define M8260_SIUMCR_MPRE (1<<12)
1105	#define M8260_SIUMCR_MLRC0 (0<<10)
1106	#define M8260_SIUMCR_MLRC1 (1<<10)
1107	#define M8260_SIUMCR_MLRC2 (2<<10)
1108	#define M8260_SIUMCR_MLRC3 (3<<10)
1109	#define M8260_SIUMCR_AEME (1<<9)
1110	#define M8260_SIUMCR_SEME (1<<8)
1111	#define M8260_SIUMCR_BSC (1<<7)
1112	#define M8260_SIUMCR_GB5E (1<<6)
1113	#define M8260_SIUMCR_B2DD (1<<5)
1114	#define M8260_SIUMCR_B3DD (1<<4)
1115
1116	/*
1117	*************************************************************************
1118	* MPC8260 DUAL-PORT RAM AND REGISTERS *
1119	*************************************************************************
1120	*/
1121	typedef struct m8260_ {
1122
1123	/*
1124	* CPM Dual-Port RAM
1125	*/
1126	uint8_t dpram1[16384]; /* 0x0000 - 0x3FFF BD/data/ucode */
1127	uint8_t cpm_pad0[16384]; /* 0x4000 - 0x7FFF Reserved */
1128
1129	m8260SCCparms_t scc1p;
1130	uint8_t pad_scc1[256-sizeof(m8260SCCparms_t)];
1131	m8260SCCparms_t scc2p;
1132	uint8_t pad_scc2[256-sizeof(m8260SCCparms_t)];
1133	m8260SCCparms_t scc3p;
1134	uint8_t pad_scc3[256-sizeof(m8260SCCparms_t)];
1135	m8260SCCparms_t scc4p;
1136	uint8_t pad_scc4[256-sizeof(m8260SCCparms_t)];
1137
1138	m8260FCCparms_t fcc1p;
1139	uint8_t pad_fcc1[256-sizeof(m8260FCCparms_t)];
1140	m8260FCCparms_t fcc2p;
1141	uint8_t pad_fcc2[256-sizeof(m8260FCCparms_t)];
1142	m8260FCCparms_t fcc3p;
1143	uint8_t pad_fcc3[256-sizeof(m8260FCCparms_t)];
1144
1145	uint8_t mcc1p[128];
1146	uint8_t pad_mcc1[124];
1147	uint16_t smc1_base;
1148	uint16_t idma1_base;
1149	uint8_t mcc2p[128];
1150	uint8_t pad_mcc2[124];
1151	uint16_t smc2_base;
1152	uint16_t idma2_base;
1153	uint8_t pad_spi[252];
1154	uint16_t spi_base;
1155	uint16_t idma3_base;
1156	uint8_t pad_risc[224];
1157	uint8_t risc_timers[16];
1158	uint16_t rev_num;
1159	uint16_t cpm_pad7;
1160	uint32_t cpm_pad8;
1161	uint16_t rand;
1162	uint16_t i2c_base;
1163	uint16_t idma4_base;
1164	uint8_t cpm_pad9[1282];
1165
1166	uint8_t cpm_pad1[8192]; /* 0x9000 - 0xAFFF Reserved */
1167
1168	m8260SMCparms_t smc1p;
1169	m8260SMCparms_t smc2p;
1170	uint8_t dpram3[4096-2*sizeof(m8260SMCparms_t)];
1171
1172	uint8_t cpm_pad2[16384]; /* 0xC000 - 0xFFFF Reserved */
1173
1174
1175	/*
1176	* General SIU Block
1177	*/
1178	uint32_t siumcr;
1179	uint32_t sypcr;
1180	uint8_t siu_pad0[6];
1181	uint16_t swsr;
1182	uint8_t siu_pad1[20];
1183	uint32_t bcr;
1184	uint8_t ppc_acr;
1185	uint8_t siu_pad4[3];
1186	uint32_t ppc_alrh;
1187	uint32_t ppc_alr1;
1188	uint8_t lcl_acr;
1189	uint8_t siu_pad5[3];
1190	uint32_t lcl_alrh;
1191	uint32_t lcl_alr1;
1192	uint32_t tescr1;
1193	uint32_t tescr2;
1194	uint32_t l_tescr1;
1195	uint32_t l_tescr2;
1196	uint32_t pdtea;
1197	uint8_t pdtem;
1198	uint8_t siu_pad2[3];
1199	uint32_t ldtea;
1200	uint8_t ldtem;
1201	uint8_t siu_pad3[163];
1202
1203
1204	/*
1205	* Memory Controller Block
1206	*/
1207	m8260MEMCRegisters_t memc[12];
1208	uint8_t mem_pad0[8];
1209	uint32_t mar;
1210	uint8_t mem_pad1[4];
1211	uint32_t mamr;
1212	uint32_t mbmr;
1213	uint32_t mcmr;
1214	uint32_t mdmr;
1215	uint8_t mem_pad2[4];
1216	uint16_t mptpr;
1217	uint8_t mem_pad5[2];
1218	uint32_t mdr;
1219	uint8_t mem_pad3[4];
1220	uint32_t psdmr;
1221	uint32_t lsdmr;
1222	uint8_t purt;
1223	uint8_t mem_pad6[3];
1224	uint8_t psrt;
1225	uint8_t mem_pad7[3];
1226	uint8_t lurt;
1227	uint8_t mem_pad8[3];
1228	uint8_t lsrt;
1229	uint8_t mem_pad9[3];
1230	uint32_t immr;
1231	uint8_t mem_pad4[84];
1232
1233
1234	/*
1235	* System integration timers
1236	*/
1237	uint8_t sit_pad0[32];
1238	uint16_t tmcntsc;
1239	uint8_t sit_pad6[2];
1240	uint32_t tmcnt;
1241	uint32_t tmcntsec;
1242	uint32_t tmcntal;
1243	uint8_t sit_pad2[16];
1244	uint16_t piscr;
1245	uint8_t sit_pad5[2];
1246	uint32_t pitc;
1247	uint32_t pitr;
1248	uint8_t sit_pad3[94];
1249	uint8_t sit_pad4[2390];
1250
1251
1252	/*
1253	* Interrupt Controller
1254	*/
1255	uint16_t sicr;
1256	uint8_t ict_pad1[2];
1257	uint32_t sivec;
1258	uint32_t sipnr_h;
1259	uint32_t sipnr_l;
1260	uint32_t siprr;
1261	uint32_t scprr_h;
1262	uint32_t scprr_l;
1263	uint32_t simr_h;
1264	uint32_t simr_l;
1265	uint32_t siexr;
1266	uint8_t ict_pad0[88];
1267
1268
1269	/*
1270	* Clocks and Reset
1271	*/
1272	uint32_t sccr;
1273	uint8_t clr_pad1[4];
1274	uint32_t scmr;
1275	uint8_t clr_pad2[4];
1276	uint32_t rsr;
1277	uint32_t rmr;
1278	uint8_t clr_pad0[104];
1279
1280
1281	/*
1282	* Input/ Output Port
1283	*/
1284	uint32_t pdira;
1285	uint32_t ppara;
1286	uint32_t psora;
1287	uint32_t podra;
1288	uint32_t pdata;
1289	uint8_t iop_pad0[12];
1290	uint32_t pdirb;
1291	uint32_t pparb;
1292	uint32_t psorb;
1293	uint32_t podrb;
1294	uint32_t pdatb;
1295	uint8_t iop_pad1[12];
1296	uint32_t pdirc;
1297	uint32_t pparc;
1298	uint32_t psorc;
1299	uint32_t podrc;
1300	uint32_t pdatc;
1301	uint8_t iop_pad2[12];
1302	uint32_t pdird;
1303	uint32_t ppard;
1304	uint32_t psord;
1305	uint32_t podrd;
1306	uint32_t pdatd;
1307	uint8_t iop_pad3[12];
1308
1309
1310	/*
1311	* CPM Timers
1312	*/
1313	uint8_t tgcr1;
1314	uint8_t cpt_pad0[3];
1315	uint8_t tgcr2;
1316	uint8_t cpt_pad1[11];
1317	uint16_t tmr1;
1318	uint16_t tmr2;
1319	uint16_t trr1;
1320	uint16_t trr2;
1321	uint16_t tcr1;
1322	uint16_t tcr2;
1323	uint16_t tcn1;
1324	uint16_t tcn2;
1325	uint16_t tmr3;
1326	uint16_t tmr4;
1327	uint16_t trr3;
1328	uint16_t trr4;
1329	uint16_t tcr3;
1330	uint16_t tcr4;
1331	uint16_t tcn3;
1332	uint16_t tcn4;
1333	uint16_t ter1;
1334	uint16_t ter2;
1335	uint16_t ter3;
1336	uint16_t ter4;
1337	uint8_t cpt_pad2[608];
1338
1339
1340	/*
1341	* DMA Block
1342	*/
1343	uint8_t sdsr;
1344	uint8_t dma_pad0[3];
1345	uint8_t sdmr;
1346	uint8_t dma_pad1[3];
1347
1348	uint8_t idsr1;
1349	uint8_t dma_pad2[3];
1350	uint8_t idmr1;
1351	uint8_t dma_pad3[3];
1352	uint8_t idsr2;
1353	uint8_t dma_pad4[3];
1354	uint8_t idmr2;
1355	uint8_t dma_pad5[3];
1356	uint8_t idsr3;
1357	uint8_t dma_pad6[3];
1358	uint8_t idmr3;
1359	uint8_t dma_pad7[3];
1360	uint8_t idsr4;
1361	uint8_t dma_pad8[3];
1362	uint8_t idmr4;
1363	uint8_t dma_pad9[707];
1364
1365
1366	/*
1367	* FCC Block
1368	*/
1369	m8260FCCRegisters_t fcc1;
1370	m8260FCCRegisters_t fcc2;
1371	m8260FCCRegisters_t fcc3;
1372
1373	uint8_t fcc_pad0[656];
1374
1375	/*
1376	* BRG 5-8 Block
1377	*/
1378	uint32_t brgc5;
1379	uint32_t brgc6;
1380	uint32_t brgc7;
1381	uint32_t brgc8;
1382	uint8_t brg_pad0[608];
1383
1384
1385	/*
1386	* I2C
1387	*/
1388	uint8_t i2mod;
1389	uint8_t i2m_pad0[3];
1390	uint8_t i2add;
1391	uint8_t i2m_pad1[3];
1392	uint8_t i2brg;
1393	uint8_t i2m_pad2[3];
1394	uint8_t i2com;
1395	uint8_t i2m_pad3[3];
1396	uint8_t i2cer;
1397	uint8_t i2m_pad4[3];
1398	uint8_t i2cmr;
1399	uint8_t i2m_pad5[331];
1400
1401
1402	/*
1403	* CPM Block
1404	*/
1405	uint32_t cpcr;
1406	uint32_t rccr;
1407	uint8_t cpm_pad3[14];
1408	uint16_t rter;
1409	uint8_t cpm_pad[2];
1410	uint16_t rtmr;
1411	uint16_t rtscr;
1412	uint8_t cpm_pad4[2];
1413	uint32_t rtsr;
1414	uint8_t cpm_pad5[12];
1415
1416
1417	/*
1418	* BRG 1-4 Block
1419	*/
1420	uint32_t brgc1;
1421	uint32_t brgc2;
1422	uint32_t brgc3;
1423	uint32_t brgc4;
1424
1425
1426	/*
1427	* SCC Block
1428	*/
1429	m8260SCCRegisters_t scc1;
1430	m8260SCCRegisters_t scc2;
1431	m8260SCCRegisters_t scc3;
1432	m8260SCCRegisters_t scc4;
1433
1434
1435	/*
1436	* SMC Block
1437	*/
1438	m8260SMCRegisters_t smc1;
1439	m8260SMCRegisters_t smc2;
1440
1441
1442	/*
1443	* SPI Block
1444	*/
1445	uint16_t spmode;
1446	uint8_t spi_pad0[4];
1447	uint8_t spie;
1448	uint8_t spi_pad1[3];
1449	uint8_t spim;
1450	uint8_t spi_pad2[2];
1451	uint8_t spcom;
1452	uint8_t spi_pad3[82];
1453
1454
1455	/*
1456	* CPM Mux Block
1457	*/
1458	uint8_t cmxsi1cr;
1459	uint8_t cmx_pad0[1];
1460	uint8_t cmxsi2cr;
1461	uint8_t cmx_pad1[1];
1462	uint32_t cmxfcr;
1463	uint32_t cmxscr;
1464	uint8_t cmxsmr;
1465	uint8_t cmx_pad2[1];
1466	uint16_t cmxuar;
1467	uint8_t cmx_pad3[16];
1468
1469
1470	/*
1471	* SI & MCC Blocks
1472	*/
1473	m8260SIRegisters_t si1;
1474	m8260MCCRegisters_t mcc1;
1475	m8260SIRegisters_t si2;
1476	m8260MCCRegisters_t mcc2;
1477
1478	uint8_t mcc_pad0[1152];
1479
1480	/*
1481	* SI1 RAM
1482	*/
1483	uint8_t si1txram[512];
1484	uint8_t ram_pad0[512];
1485	uint8_t si1rxram[512];
1486	uint8_t ram_pad1[512];
1487
1488
1489	/*
1490	* SI2 RAM
1491	*/
1492	uint8_t si2txram[512];
1493	uint8_t ram_pad2[512];
1494	uint8_t si2rxram[512];
1495	uint8_t ram_pad3[512];
1496
1497
1498	} m8260_t;
1499
1500	extern volatile m8260_t m8260;
1501	#endif /* ASM */
1502
1503	#endif /* _MPC8260_H */

Note: See TracBrowser for help on using the repository browser.

Download in other formats: