1 | /* |
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2 | * |
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3 | * MPC5xx Internal I/O Definitions |
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4 | */ |
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5 | |
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6 | /* |
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7 | * MPC5xx port sponsored by Defence Research and Development Canada - Suffield |
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8 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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9 | * |
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10 | * Derived from c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h: |
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11 | * |
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12 | * Submitted By: * |
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13 | * * |
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14 | * W. Eric Norum * |
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15 | * Saskatchewan Accelerator Laboratory * |
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16 | * University of Saskatchewan * |
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17 | * 107 North Road * |
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18 | * Saskatoon, Saskatchewan, CANADA * |
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19 | * S7N 5C6 * |
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20 | * * |
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21 | * eric@skatter.usask.ca * |
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22 | * * |
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23 | * Modified for use with the MPC860 (original code was for MC68360) * |
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24 | * by * |
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25 | * Jay Monkman * |
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26 | * Frasca International, Inc. * |
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27 | * 906 E. Airport Rd. * |
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28 | * Urbana, IL, 61801 * |
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29 | * * |
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30 | * jmonkman@frasca.com * |
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31 | * * |
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32 | * Modified further for use with the MPC821 by: * |
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33 | * Andrew Bray <andy@chaos.org.uk> * |
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34 | * * |
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35 | * With some corrections/additions by: * |
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36 | * Darlene A. Stewart and * |
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37 | * Charles-Antoine Gauthier * |
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38 | * Institute for Information Technology * |
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39 | * National Research Council of Canada * |
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40 | * Ottawa, ON K1A 0R6 * |
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41 | * * |
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42 | * Darlene.Stewart@iit.nrc.ca * |
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43 | * charles.gauthier@iit.nrc.ca * |
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44 | * * |
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45 | * Corrections/additions: * |
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46 | * Copyright (c) 1999, National Research Council of Canada * |
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47 | * |
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48 | * MPC5xx port sponsored by Defence Research and Development Canada - Suffield |
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49 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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50 | * |
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51 | * The license and distribution terms for this file may be |
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52 | * found in the file LICENSE in this distribution or at |
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53 | * http://www.rtems.org/license/LICENSE. |
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54 | */ |
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55 | |
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56 | #ifndef _MPC5XX_H |
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57 | #define _MPC5XX_H |
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58 | |
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59 | #include <libcpu/spr.h> |
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60 | |
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61 | |
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62 | #ifndef ASM |
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63 | |
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64 | #ifdef __cplusplus |
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65 | extern "C" { |
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66 | #endif |
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67 | |
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68 | /* |
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69 | * Macros for accessing Special Purpose Registers (SPRs) |
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70 | */ |
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71 | |
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72 | #define _eieio __asm__ volatile ("eieio\n"::) |
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73 | #define _sync __asm__ volatile ("sync\n"::) |
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74 | #define _isync __asm__ volatile ("isync\n"::) |
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75 | |
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76 | /* |
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77 | * Core Registers (SPRs) |
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78 | */ |
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79 | #define DER 149 /* Debug Enable Register */ |
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80 | #define IMMR 638 /* Internal Memory Map Register */ |
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81 | #define IMMR_FLEN (1<<11) /* Internal flash ROM enabled */ |
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82 | |
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83 | /* |
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84 | * Interrupt Control Registers (SPRs) |
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85 | */ |
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86 | #define EIE 80 /* External Interrupt Enable Register */ |
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87 | #define EID 81 /* External Interrupt Disable Register */ |
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88 | #define NRI 82 /* Non-Recoverable Interrupt Register */ |
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89 | |
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90 | #define ECR 148 /* Exception Cause Register */ |
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91 | |
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92 | /* |
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93 | * Bus Control Registers (SPRs) |
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94 | */ |
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95 | #define LCTRL1 156 /* L-Bus Support Control Register 1 */ |
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96 | #define LCTRL2 157 /* L-Bus Support Control Register 2 */ |
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97 | #define ICTRL 158 /* I-Bus Support Control Register */ |
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98 | |
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99 | /* |
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100 | * Burst Buffer Control Registers (SPRs) |
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101 | */ |
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102 | #define BBCMCR 560 /* Burst Buffer Configuration Register */ |
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103 | #define BBCMCR_BE (1<<13) /* Burst enable */ |
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104 | #define BBCMCR_ETRE (1<<12) /* Exception table relocation enable */ |
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105 | |
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106 | #define MI_RBA0 784 /* Region 0 Address Register */ |
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107 | #define MI_RBA1 785 /* Region 1 Address Register */ |
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108 | #define MI_RBA2 786 /* Region 2 Address Register */ |
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109 | #define MI_RBA3 787 /* Region 3 Address Register */ |
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110 | |
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111 | #define MI_RA0 816 /* Region 0 Attribute Register */ |
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112 | #define MI_RA1 817 /* Region 1 Attribute Register */ |
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113 | #define MI_RA2 818 /* Region 2 Attribute Register */ |
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114 | #define MI_RA3 819 /* Region 3 Attribute Register */ |
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115 | #define MI_GRA 528 /* Region Global Attribute Register */ |
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116 | #define MI_RA_PP (3 << 10) /* Protection bits: */ |
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117 | #define MI_RA_PP_SUPV (1 << 10) /* Supervisor */ |
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118 | #define MI_RA_PP_USER (2 << 10) /* User */ |
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119 | #define MI_RA_G (1 << 6) /* Guarded region */ |
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120 | |
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121 | |
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122 | /* |
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123 | * L-Bus to U-Bus Interface (L2U) Registers (SPRs) |
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124 | */ |
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125 | #define L2U_MCR 568 /* L2U Module Configuration Register */ |
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126 | |
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127 | #define L2U_RBA0 792 /* L2U Region 0 Address Register */ |
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128 | #define L2U_RBA1 793 /* L2U Region 1 Address Register */ |
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129 | #define L2U_RBA2 794 /* L2U Region 2 Address Register */ |
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130 | #define L2U_RBA3 795 /* L2U Region 3 Address Register */ |
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131 | |
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132 | #define L2U_RA0 824 /* L2U Region 0 Attribute Register */ |
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133 | #define L2U_RA1 825 /* L2U Region 1 Attribute Register */ |
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134 | #define L2U_RA2 826 /* L2U Region 2 Attribute Register */ |
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135 | #define L2U_RA3 827 /* L2U Region 3 Attribute Register */ |
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136 | #define L2U_GRA 536 /* L2U Global Region Attribute Register */ |
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137 | #define L2U_RA_PP (3 << 10) /* Protection bits: */ |
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138 | #define L2U_RA_PP_SUPV (1 << 10) /* Supervisor */ |
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139 | #define L2U_RA_PP_USER (2 << 10) /* User */ |
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140 | #define L2U_RA_G (1 << 6) /* Guarded region */ |
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141 | |
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142 | |
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143 | /* |
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144 | ************************************************************************* |
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145 | * REGISTER SUBBLOCKS * |
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146 | ************************************************************************* |
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147 | */ |
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148 | |
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149 | /* |
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150 | ************************************************************************* |
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151 | * System Protection Control Register (SYPCR) * |
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152 | ************************************************************************* |
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153 | */ |
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154 | #define USIU_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ |
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155 | #define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ |
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156 | #define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */ |
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157 | #define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */ |
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158 | #define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */ |
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159 | #define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ |
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160 | #define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */ |
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161 | |
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162 | #define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ |
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163 | #define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */ |
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164 | #define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */ |
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165 | #define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */ |
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166 | #define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ |
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167 | #define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */ |
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168 | |
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169 | /* |
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170 | ************************************************************************* |
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171 | * Software Service Register (SWSR) * |
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172 | ************************************************************************* |
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173 | */ |
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174 | #define TICKLE_WATCHDOG() \ |
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175 | do { \ |
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176 | usiu.swsr = 0x556C; \ |
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177 | usiu.swsr = 0xAA39; \ |
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178 | } while (0) \ |
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179 | |
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180 | /* |
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181 | ************************************************************************* |
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182 | * Memory Control Registers * |
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183 | ************************************************************************* |
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184 | */ |
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185 | #define USIU_MEMC_BR_BA(x) (((uint32_t)x)&0xffff8000) |
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186 | /* Base address */ |
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187 | #define USIU_MEMC_BR_AT(x) ((x)<<12) /* Address type */ |
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188 | #define USIU_MEMC_BR_PS8 (1<<10) /* 8 bit port */ |
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189 | #define USIU_MEMC_BR_PS16 (2<<10) /* 16 bit port */ |
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190 | #define USIU_MEMC_BR_PS32 (0<<10) /* 32 bit port */ |
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191 | #define USIU_MEMC_BR_WP (1<<8) /* Write protect */ |
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192 | #define USIU_MEMC_BR_WEBS (1<<5) /* Write enable/byte select */ |
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193 | #define USIU_MEMC_BR_TBDIP (1<<4) /* Toggle-Burst data in progress*/ |
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194 | #define USIU_MEMC_BR_LBDIP (1<<3) /* Late-burst data in progress */ |
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195 | #define USIU_MEMC_BR_SETA (1<<2) /* External transfer acknowledge */ |
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196 | #define USIU_MEMC_BR_BI (1<<1) /* Burst inhibit */ |
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197 | #define USIU_MEMC_BR_V (1<<0) /* Base/Option register are valid */ |
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198 | |
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199 | #define USIU_MEMC_OR_32K 0xffff8000 /* Address range */ |
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200 | #define USIU_MEMC_OR_64K 0xffff0000 |
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201 | #define USIU_MEMC_OR_128K 0xfffe0000 |
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202 | #define USIU_MEMC_OR_256K 0xfffc0000 |
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203 | #define USIU_MEMC_OR_512K 0xfff80000 |
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204 | #define USIU_MEMC_OR_1M 0xfff00000 |
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205 | #define USIU_MEMC_OR_2M 0xffe00000 |
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206 | #define USIU_MEMC_OR_4M 0xffc00000 |
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207 | #define USIU_MEMC_OR_8M 0xff800000 |
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208 | #define USIU_MEMC_OR_16M 0xff000000 |
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209 | #define USIU_MEMC_OR_32M 0xfe000000 |
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210 | #define USIU_MEMC_OR_64M 0xfc000000 |
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211 | #define USIU_MEMC_OR_128 0xf8000000 |
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212 | #define USIU_MEMC_OR_256M 0xf0000000 |
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213 | #define USIU_MEMC_OR_512M 0xe0000000 |
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214 | #define USIU_MEMC_OR_1G 0xc0000000 |
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215 | #define USIU_MEMC_OR_2G 0x80000000 |
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216 | #define USIU_MEMC_OR_4G 0x00000000 |
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217 | #define USIU_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ |
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218 | #define USIU_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ |
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219 | #define USIU_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ |
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220 | #define USIU_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ |
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221 | #define USIU_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ |
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222 | #define USIU_MEMC_OR_ETHR (1<<8) /* Extended hold time on reads */ |
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223 | #define USIU_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ |
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224 | #define USIU_MEMC_OR_BSCY(x) ((x)<<1) /* Burst beat length in clocks */ |
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225 | #define USIU_MEMC_OR_TRLX (1<<0) /* Relaxed timing in GPCM */ |
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226 | |
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227 | /* |
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228 | ************************************************************************* |
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229 | * Clocks and Reset Controlmer * |
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230 | ************************************************************************* |
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231 | */ |
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232 | |
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233 | #define USIU_SCCR_DBCT (1<<31) /* Disable backup clock for timers */ |
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234 | #define USIU_SCCR_COM(x) ((x)<<29) /* Clock output mode */ |
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235 | #define USIU_SCCR_RTDIV (1<<24) /* RTC, PIT divide by 256, not 4 */ |
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236 | #define USIU_PRQEN (1<<21) /* MSR[POW] controls frequency */ |
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237 | #define USIU_SCCR_EBDF(x) ((x)<<17) /* External bus division factor */ |
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238 | #define USIU_LME (1<<16) /* Enable limp mode */ |
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239 | #define USIU_ENGDIV(x) ((x)<<9) /* Set engineering clock divisor */ |
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240 | |
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241 | #define USIU_PLPRCR_MF(x) (((x)-1)<<20) /* PLL mult. factor (true) */ |
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242 | #define USIU_PLPRCR_SPLS (1<<16) /* System PLL locked */ |
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243 | #define USIU_PLPRCR_TEXPS (1<<14) /* Assert TEXP always */ |
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244 | |
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245 | /* |
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246 | ************************************************************************* |
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247 | * Programmable Interval Timer * |
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248 | ************************************************************************* |
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249 | */ |
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250 | #define USIU_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ |
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251 | #define USIU_PISCR_PS (1<<7) /* PIT Interrupt state */ |
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252 | #define USIU_PISCR_PIE (1<<2) /* PIT interrupt enable */ |
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253 | #define USIU_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ |
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254 | #define USIU_PISCR_PTE (1<<0) /* PIT enable */ |
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255 | |
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256 | /* |
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257 | ************************************************************************* |
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258 | * Time Base * |
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259 | ************************************************************************* |
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260 | */ |
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261 | #define USIU_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ |
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262 | #define USIU_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ |
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263 | #define USIU_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ |
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264 | #define USIU_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ |
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265 | #define USIU_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ |
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266 | #define USIU_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ |
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267 | #define USIU_TBSCR_TBE (1<<0) /* enable TB and decrementer */ |
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268 | |
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269 | /* |
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270 | ************************************************************************* |
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271 | * SIU Interrupt Mask * |
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272 | ************************************************************************* |
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273 | */ |
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274 | #define USIU_SIMASK_IRM0 (1<<31) |
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275 | #define USIU_SIMASK_LVM0 (1<<30) |
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276 | #define USIU_SIMASK_IRM1 (1<<29) |
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277 | #define USIU_SIMASK_LVM1 (1<<28) |
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278 | #define USIU_SIMASK_IRM2 (1<<27) |
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279 | #define USIU_SIMASK_LVM2 (1<<26) |
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280 | #define USIU_SIMASK_IRM3 (1<<25) |
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281 | #define USIU_SIMASK_LVM3 (1<<24) |
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282 | #define USIU_SIMASK_IRM4 (1<<23) |
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283 | #define USIU_SIMASK_LVM4 (1<<22) |
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284 | #define USIU_SIMASK_IRM5 (1<<21) |
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285 | #define USIU_SIMASK_LVM5 (1<<20) |
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286 | #define USIU_SIMASK_IRM6 (1<<19) |
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287 | #define USIU_SIMASK_LVM6 (1<<18) |
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288 | #define USIU_SIMASK_IRM7 (1<<17) |
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289 | #define USIU_SIMASK_LVM7 (1<<16) |
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290 | |
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291 | /* |
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292 | ************************************************************************* |
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293 | * SIU Module Control * |
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294 | ************************************************************************* |
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295 | */ |
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296 | #define USIU_SIUMCR_EARB (1<<31) |
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297 | #define USIU_SIUMCR_EARP0 (0<<28) |
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298 | #define USIU_SIUMCR_EARP1 (1<<28) |
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299 | #define USIU_SIUMCR_EARP2 (2<<28) |
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300 | #define USIU_SIUMCR_EARP3 (3<<28) |
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301 | #define USIU_SIUMCR_EARP4 (4<<28) |
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302 | #define USIU_SIUMCR_EARP5 (5<<28) |
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303 | #define USIU_SIUMCR_EARP6 (6<<28) |
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304 | #define USIU_SIUMCR_EARP7 (7<<28) |
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305 | #define USIU_SIUMCR_DSHW (1<<23) |
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306 | #define USIU_SIUMCR_DBGC0 (0<<21) |
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307 | #define USIU_SIUMCR_DBGC1 (1<<21) |
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308 | #define USIU_SIUMCR_DBGC2 (2<<21) |
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309 | #define USIU_SIUMCR_DBGC3 (3<<21) |
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310 | #define USIU_SIUMCR_DBPC (1<<20) |
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311 | #define USIU_SIUMCR_ATWC (1<<19) |
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312 | #define USIU_SIUMCR_GPC0 (0<<17) |
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313 | #define USIU_SIUMCR_GPC1 (1<<17) |
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314 | #define USIU_SIUMCR_GPC2 (2<<17) |
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315 | #define USIU_SIUMCR_GPC3 (3<<17) |
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316 | #define USIU_SIUMCR_DLK (1<<16) |
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317 | #define USIU_SIUMCR_SC0 (0<<13) |
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318 | #define USIU_SIUMCR_SC1 (1<<13) |
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319 | #define USIU_SIUMCR_SC2 (2<<13) |
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320 | #define USIU_SIUMCR_SC3 (3<<13) |
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321 | #define USIU_SIUMCR_RCTX (1<<12) |
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322 | #define USIU_SIUMCR_MLRC0 (0<<10) |
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323 | #define USIU_SIUMCR_MLRC1 (1<<10) |
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324 | #define USIU_SIUMCR_MLRC2 (2<<10) |
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325 | #define USIU_SIUMCR_MLRC3 (3<<10) |
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326 | #define USIU_SIUMCR_MTSC (1<<7) |
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327 | |
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328 | /* |
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329 | * Value to write to a key register to unlock the corresponding SIU register |
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330 | */ |
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331 | #define USIU_UNLOCK_KEY 0x55CCAA33 |
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332 | |
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333 | /* |
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334 | ************************************************************************* |
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335 | * UIMB Module Control * |
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336 | ************************************************************************* |
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337 | */ |
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338 | #define UIMB_UMCR_STOP (1<<31) |
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339 | #define UIMB_UMCR_IRQMUX(x) ((x)<<29) |
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340 | #define UIMB_UMCR_HSPEED (1<<28) |
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341 | |
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342 | /* |
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343 | ************************************************************************* |
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344 | * QSMCM Serial Communications Interface (SCI) * |
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345 | ************************************************************************* |
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346 | */ |
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347 | |
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348 | |
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349 | #define QSMCM_ILDSCI(x) ((x)<<8) /* SCI interrupt level */ |
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350 | |
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351 | #define QSMCM_SCI_BAUD(x) ((x)&0x1FFF) /* Baud rate field */ |
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352 | |
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353 | #define QSMCM_SCI_LOOPS (1<<14) /* Loopback test mode */ |
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354 | #define QSMCM_SCI_WOMS (1<<13) /* Wire-or mode select */ |
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355 | #define QSMCM_SCI_ILT (1<<12) /* Idle-line detect type */ |
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356 | #define QSMCM_SCI_PT (1<<11) /* Parity type */ |
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357 | #define QSMCM_SCI_PE (1<<10) /* Parity enable */ |
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358 | #define QSMCM_SCI_M (1<<9) /* 11-bit mode */ |
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359 | #define QSMCM_SCI_WAKE (1<<8) /* Wakeup mode */ |
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360 | |
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361 | #define QSMCM_SCI_TIE (1<<7) /* Transmitter interrupt enable */ |
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362 | #define QSMCM_SCI_TCIE (1<<6) /* Transmit complete intr. enable */ |
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363 | #define QSMCM_SCI_RIE (1<<5) /* Receiver interrupt enable */ |
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364 | #define QSMCM_SCI_ILIE (1<<4) /* Idle line interrupt enable */ |
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365 | #define QSMCM_SCI_TE (1<<3) /* Transmitter enable */ |
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366 | #define QSMCM_SCI_RE (1<<2) /* Receiver enable */ |
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367 | #define QSMCM_SCI_RWU (1<<1) /* Receiver wake-up enable */ |
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368 | #define QSMCM_SCI_SBK (1<<0) /* Send break */ |
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369 | |
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370 | #define QSMCM_SCI_TDRE (1<<8) /* Transmit data register empty */ |
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371 | #define QSMCM_SCI_TC (1<<7) /* Transmit complete */ |
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372 | #define QSMCM_SCI_RDRF (1<<6) /* Receive data register full */ |
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373 | #define QSMCM_SCI_RAF (1<<5) /* Receiver active flag */ |
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374 | #define QSMCM_SCI_IDLE (1<<4) /* Idle line detected */ |
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375 | #define QSMCM_SCI_OR (1<<3) /* Receiver overrun error */ |
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376 | #define QSMCM_SCI_NF (1<<2) /* Receiver noise error flag */ |
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377 | #define QSMCM_SCI_FE (1<<1) /* Receiver framing error */ |
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378 | #define QSMCM_SCI_PF (1<<0) /* Receiver parity error */ |
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379 | |
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380 | /* |
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381 | ************************************************************************* |
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382 | * Unified System Interface Unit * |
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383 | ************************************************************************* |
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384 | */ |
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385 | |
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386 | /* |
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387 | * Memory controller registers |
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388 | */ |
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389 | typedef struct m5xxMEMCRegisters_ { |
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390 | uint32_t _br; |
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391 | uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */ |
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392 | } m5xxMEMCRegisters_t; |
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393 | |
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394 | /* |
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395 | * USIU itself |
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396 | */ |
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397 | typedef struct usiu_ { |
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398 | /* |
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399 | * SIU Block |
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400 | */ |
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401 | uint32_t siumcr; |
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402 | uint32_t sypcr; |
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403 | uint32_t _pad70; |
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404 | uint16_t _pad0; |
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405 | uint16_t swsr; |
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406 | uint32_t sipend; |
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407 | uint32_t simask; |
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408 | uint32_t siel; |
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409 | uint32_t sivec; |
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410 | uint32_t tesr; |
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411 | uint32_t sgpiodt1; |
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412 | uint32_t sgpiodt2; |
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413 | uint32_t sgpiocr; |
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414 | uint32_t emcr; |
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415 | uint8_t _pad71[0x03C-0x034]; |
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416 | uint32_t pdmcr; |
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417 | uint8_t _pad2[0x100-0x40]; |
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418 | |
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419 | /* |
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420 | * MEMC Block |
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421 | */ |
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422 | m5xxMEMCRegisters_t memc[4]; |
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423 | uint8_t _pad7[0x140-0x120]; |
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424 | uint32_t dmbr; |
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425 | uint32_t dmor; |
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426 | uint8_t _pad8[0x178-0x148]; |
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427 | uint16_t mstat; |
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428 | uint8_t _pad9[0x200-0x17A]; |
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429 | |
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430 | /* |
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431 | * System integration timers |
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432 | */ |
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433 | uint16_t tbscr; |
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434 | uint16_t _pad10; |
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435 | uint32_t tbreff0; |
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436 | uint32_t tbreff1; |
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437 | uint8_t _pad11[0x220-0x20c]; |
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438 | uint16_t rtcsc; |
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439 | uint16_t _pad12; |
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440 | uint32_t rtc; |
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441 | uint32_t rtsec; |
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442 | uint32_t rtcal; |
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443 | uint32_t _pad13[4]; |
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444 | uint16_t piscr; |
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445 | uint16_t _pad14; |
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446 | uint16_t pitc; |
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447 | uint16_t _pad_14_1; |
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448 | uint16_t pitr; |
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449 | uint16_t _pad_14_2; |
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450 | uint8_t _pad15[0x280-0x24c]; |
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451 | |
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452 | /* |
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453 | * Clocks and Reset |
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454 | */ |
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455 | uint32_t sccr; |
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456 | uint32_t plprcr; |
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457 | uint16_t rsr; |
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458 | uint16_t _pad72; |
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459 | uint16_t colir; |
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460 | uint16_t _pad73; |
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461 | uint16_t vsrmcr; |
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462 | uint8_t _pad16[0x300-0x292]; |
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463 | |
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464 | /* |
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465 | * System integration timers keys |
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466 | */ |
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467 | uint32_t tbscrk; |
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468 | uint32_t tbreff0k; |
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469 | uint32_t tbreff1k; |
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470 | uint32_t tbk; |
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471 | uint32_t _pad17[4]; |
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472 | uint32_t rtcsk; |
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473 | uint32_t rtck; |
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474 | uint32_t rtseck; |
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475 | uint32_t rtcalk; |
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476 | uint32_t _pad18[4]; |
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477 | uint32_t piscrk; |
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478 | uint32_t pitck; |
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479 | uint8_t _pad19[0x380-0x348]; |
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480 | |
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481 | /* |
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482 | * Clocks and Reset Keys |
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483 | */ |
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484 | uint32_t sccrk; |
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485 | uint32_t plprck; |
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486 | uint32_t rsrk; |
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487 | uint8_t _pad20[0x400-0x38c]; |
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488 | } usiu_t; |
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489 | |
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490 | extern volatile usiu_t usiu; /* defined in linkcmds */ |
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491 | |
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492 | /* |
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493 | ************************************************************************* |
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494 | * Inter-Module Bus and Devices * |
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495 | ************************************************************************* |
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496 | */ |
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497 | |
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498 | /* |
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499 | * Dual-Port TPU RAM (DPTRAM) |
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500 | */ |
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501 | typedef struct m5xxDPTRAMRegisters_ { |
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502 | uint8_t pad[0x4000]; /* define later */ |
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503 | } m5xxDPTRAMRegisters_t; |
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504 | |
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505 | /* |
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506 | * Time Processor Unit (TPU) |
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507 | */ |
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508 | typedef struct m5xxTPU3Registers_ { |
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509 | uint8_t pad[0x400]; /* define later */ |
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510 | } m5xxTPU3Registers_t; |
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511 | |
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512 | /* |
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513 | * Queued A/D Converter (QADC) |
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514 | */ |
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515 | typedef struct m5xxQADC64Registers_ { |
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516 | uint8_t pad[0x400]; /* define later */ |
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517 | } m5xxQADC64Registers_t; |
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518 | |
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519 | /* |
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520 | * Serial Communications Interface (SCI) |
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521 | */ |
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522 | typedef struct m5xxSCIRegisters_ { |
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523 | uint16_t sccr0; |
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524 | uint16_t sccr1; |
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525 | uint16_t scsr; |
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526 | uint16_t scdr; |
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527 | } m5xxSCIRegisters_t; |
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528 | |
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529 | /* |
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530 | * Serial Peripheral Interface (SPI) |
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531 | */ |
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532 | typedef struct m5xxSPIRegisters_ { |
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533 | uint16_t spcr0; |
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534 | uint16_t spcr1; |
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535 | uint16_t spcr2; |
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536 | uint8_t spcr3; |
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537 | uint8_t spsr; |
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538 | } m5xxSPIRegisters_t; |
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539 | |
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540 | /* |
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541 | * Queued Serial Multi-Channel Module (QSMCM) |
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542 | */ |
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543 | typedef struct m5xxQSMCMRegisters_ { |
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544 | uint16_t qsmcmmcr; |
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545 | uint16_t qtest; |
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546 | uint16_t qdsci_il; |
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547 | uint16_t qspi_il; |
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548 | |
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549 | m5xxSCIRegisters_t sci1; |
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550 | |
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551 | uint8_t _pad10[0x14-0x10]; |
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552 | |
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553 | uint16_t portqs; |
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554 | uint16_t pqspar; |
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555 | m5xxSPIRegisters_t spi; |
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556 | |
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557 | m5xxSCIRegisters_t sci2; |
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558 | |
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559 | uint16_t qsci1cr; |
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560 | uint16_t qsci1sr; |
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561 | uint16_t sctq[0x10]; |
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562 | uint16_t scrq[0x10]; |
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563 | |
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564 | uint8_t _pad6C[0x140-0x06C]; |
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565 | |
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566 | uint16_t recram[0x20]; |
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567 | uint16_t tranram[0x20]; |
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568 | uint16_t comdram[0x20]; |
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569 | } m5xxQSMCMRegisters_t; |
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570 | |
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571 | /* |
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572 | * Modular Input/Output System (MIOS) |
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573 | */ |
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574 | typedef struct m5xxMIOS1Registers_ { |
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575 | uint8_t pad[0x1000]; /* define later */ |
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576 | } m5xxMIOS1Registers_t; |
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577 | |
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578 | /* |
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579 | * Can 2.0B Controller (TouCAN) |
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580 | */ |
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581 | typedef struct m5xxTouCANRegisters_ { |
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582 | uint8_t pad[0x400]; /* define later */ |
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583 | } m5xxTouCANRegisters_t; |
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584 | |
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585 | /* |
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586 | * U-Bus to IMB3 Bus Interface Module (UIMB) |
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587 | */ |
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588 | typedef struct m5xxUIMBRegisters_ { |
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589 | uint32_t umcr; |
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590 | uint32_t utstcreg; |
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591 | uint32_t uipend; |
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592 | } m5xxUIMBRegisters_t; |
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593 | |
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594 | /* |
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595 | * IMB itself |
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596 | */ |
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597 | typedef struct imb_ { |
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598 | m5xxDPTRAMRegisters_t dptram; |
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599 | m5xxTPU3Registers_t tpu[2]; |
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600 | m5xxQADC64Registers_t qadc[2]; |
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601 | m5xxQSMCMRegisters_t qsmcm; |
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602 | uint8_t _pad5200[0x6000-0x5200]; |
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603 | m5xxMIOS1Registers_t mios; |
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604 | m5xxTouCANRegisters_t toucan[2]; |
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605 | uint8_t _pad7800[0x7F80-0x7800]; |
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606 | m5xxUIMBRegisters_t uimb; |
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607 | } imb_t; |
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608 | |
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609 | extern volatile imb_t imb; /* defined in linkcmds */ |
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610 | |
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611 | |
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612 | /* |
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613 | * Methods shared across libcpu and the BSP. |
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614 | */ |
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615 | void clockOn(void* unused); |
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616 | void clockOff(void* unused); |
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617 | int clockIsOn(void* unused); |
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618 | rtems_isr Clock_isr(rtems_vector_number vector); |
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619 | |
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620 | #ifdef __cplusplus |
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621 | } |
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622 | #endif |
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623 | |
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624 | #endif /* ASM */ |
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625 | |
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626 | #endif /* _MPC5XX_H */ |
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