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source: rtems/bsps/powerpc/include/mpc5xx.h

Last change on this file was 753873e5, checked in by Joel Sherrill <joel@…>, on 03/22/22 at 20:03:30
Update Eric Norum contact info and start to normalize file headers
Property mode set to `100644`
File size: 22.1 KB

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1	/*
2	*
3	* MPC5xx Internal I/O Definitions
4	*/
5
6	/*
7	* MPC5xx port sponsored by Defence Research and Development Canada - Suffield
8	* Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
9	*
10	* Derived from c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h:
11	*
12	* Submitted By: *
13	* *
14	* Eric Norum <eric@norum.ca> *
15	* *
16	* Modified for use with the MPC860 (original code was for MC68360) *
17	* by *
18	* Jay Monkman *
19	* Frasca International, Inc. *
20	* 906 E. Airport Rd. *
21	* Urbana, IL, 61801 *
22	* *
23	* jmonkman@frasca.com *
24	* *
25	* Modified further for use with the MPC821 by: *
26	* Andrew Bray <andy@chaos.org.uk> *
27	* *
28	* With some corrections/additions by: *
29	* Darlene A. Stewart and *
30	* Charles-Antoine Gauthier *
31	* Institute for Information Technology *
32	* National Research Council of Canada *
33	* Ottawa, ON K1A 0R6 *
34	* *
35	* Darlene.Stewart@iit.nrc.ca *
36	* charles.gauthier@iit.nrc.ca *
37	* *
38	* Corrections/additions: *
39	* Copyright (c) 1999, National Research Council of Canada *
40	*
41	* MPC5xx port sponsored by Defence Research and Development Canada - Suffield
42	* Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
43	*
44	* The license and distribution terms for this file may be
45	* found in the file LICENSE in this distribution or at
46	* http://www.rtems.org/license/LICENSE.
47	*/
48
49	#ifndef _MPC5XX_H
50	#define _MPC5XX_H
51
52	#include <libcpu/spr.h>
53
54
55	#ifndef ASM
56
57	#ifdef __cplusplus
58	extern "C" {
59	#endif
60
61	/*
62	* Macros for accessing Special Purpose Registers (SPRs)
63	*/
64
65	#define _eieio __asm__ volatile ("eieio\n"::)
66	#define _sync __asm__ volatile ("sync\n"::)
67	#define _isync __asm__ volatile ("isync\n"::)
68
69	/*
70	* Core Registers (SPRs)
71	*/
72	#define DER 149 /* Debug Enable Register */
73	#define IMMR 638 /* Internal Memory Map Register */
74	#define IMMR_FLEN (1<<11) /* Internal flash ROM enabled */
75
76	/*
77	* Interrupt Control Registers (SPRs)
78	*/
79	#define EIE 80 /* External Interrupt Enable Register */
80	#define EID 81 /* External Interrupt Disable Register */
81	#define NRI 82 /* Non-Recoverable Interrupt Register */
82
83	#define ECR 148 /* Exception Cause Register */
84
85	/*
86	* Bus Control Registers (SPRs)
87	*/
88	#define LCTRL1 156 /* L-Bus Support Control Register 1 */
89	#define LCTRL2 157 /* L-Bus Support Control Register 2 */
90	#define ICTRL 158 /* I-Bus Support Control Register */
91
92	/*
93	* Burst Buffer Control Registers (SPRs)
94	*/
95	#define BBCMCR 560 /* Burst Buffer Configuration Register */
96	#define BBCMCR_BE (1<<13) /* Burst enable */
97	#define BBCMCR_ETRE (1<<12) /* Exception table relocation enable */
98
99	#define MI_RBA0 784 /* Region 0 Address Register */
100	#define MI_RBA1 785 /* Region 1 Address Register */
101	#define MI_RBA2 786 /* Region 2 Address Register */
102	#define MI_RBA3 787 /* Region 3 Address Register */
103
104	#define MI_RA0 816 /* Region 0 Attribute Register */
105	#define MI_RA1 817 /* Region 1 Attribute Register */
106	#define MI_RA2 818 /* Region 2 Attribute Register */
107	#define MI_RA3 819 /* Region 3 Attribute Register */
108	#define MI_GRA 528 /* Region Global Attribute Register */
109	#define MI_RA_PP (3 << 10) /* Protection bits: */
110	#define MI_RA_PP_SUPV (1 << 10) /* Supervisor */
111	#define MI_RA_PP_USER (2 << 10) /* User */
112	#define MI_RA_G (1 << 6) /* Guarded region */
113
114
115	/*
116	* L-Bus to U-Bus Interface (L2U) Registers (SPRs)
117	*/
118	#define L2U_MCR 568 /* L2U Module Configuration Register */
119
120	#define L2U_RBA0 792 /* L2U Region 0 Address Register */
121	#define L2U_RBA1 793 /* L2U Region 1 Address Register */
122	#define L2U_RBA2 794 /* L2U Region 2 Address Register */
123	#define L2U_RBA3 795 /* L2U Region 3 Address Register */
124
125	#define L2U_RA0 824 /* L2U Region 0 Attribute Register */
126	#define L2U_RA1 825 /* L2U Region 1 Attribute Register */
127	#define L2U_RA2 826 /* L2U Region 2 Attribute Register */
128	#define L2U_RA3 827 /* L2U Region 3 Attribute Register */
129	#define L2U_GRA 536 /* L2U Global Region Attribute Register */
130	#define L2U_RA_PP (3 << 10) /* Protection bits: */
131	#define L2U_RA_PP_SUPV (1 << 10) /* Supervisor */
132	#define L2U_RA_PP_USER (2 << 10) /* User */
133	#define L2U_RA_G (1 << 6) /* Guarded region */
134
135
136	/*
137	*************************************************************************
138	* REGISTER SUBBLOCKS *
139	*************************************************************************
140	*/
141
142	/*
143	*************************************************************************
144	* System Protection Control Register (SYPCR) *
145	*************************************************************************
146	*/
147	#define USIU_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */
148	#define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
149	#define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */
150	#define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */
151	#define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */
152	#define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
153	#define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */
154
155	#define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */
156	#define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */
157	#define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */
158	#define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */
159	#define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */
160	#define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */
161
162	/*
163	*************************************************************************
164	* Software Service Register (SWSR) *
165	*************************************************************************
166	*/
167	#define TICKLE_WATCHDOG() \
168	do { \
169	usiu.swsr = 0x556C; \
170	usiu.swsr = 0xAA39; \
171	} while (0) \
172
173	/*
174	*************************************************************************
175	* Memory Control Registers *
176	*************************************************************************
177	*/
178	#define USIU_MEMC_BR_BA(x) (((uint32_t)x)&0xffff8000)
179	/* Base address */
180	#define USIU_MEMC_BR_AT(x) ((x)<<12) /* Address type */
181	#define USIU_MEMC_BR_PS8 (1<<10) /* 8 bit port */
182	#define USIU_MEMC_BR_PS16 (2<<10) /* 16 bit port */
183	#define USIU_MEMC_BR_PS32 (0<<10) /* 32 bit port */
184	#define USIU_MEMC_BR_WP (1<<8) /* Write protect */
185	#define USIU_MEMC_BR_WEBS (1<<5) /* Write enable/byte select */
186	#define USIU_MEMC_BR_TBDIP (1<<4) /* Toggle-Burst data in progress*/
187	#define USIU_MEMC_BR_LBDIP (1<<3) /* Late-burst data in progress */
188	#define USIU_MEMC_BR_SETA (1<<2) /* External transfer acknowledge */
189	#define USIU_MEMC_BR_BI (1<<1) /* Burst inhibit */
190	#define USIU_MEMC_BR_V (1<<0) /* Base/Option register are valid */
191
192	#define USIU_MEMC_OR_32K 0xffff8000 /* Address range */
193	#define USIU_MEMC_OR_64K 0xffff0000
194	#define USIU_MEMC_OR_128K 0xfffe0000
195	#define USIU_MEMC_OR_256K 0xfffc0000
196	#define USIU_MEMC_OR_512K 0xfff80000
197	#define USIU_MEMC_OR_1M 0xfff00000
198	#define USIU_MEMC_OR_2M 0xffe00000
199	#define USIU_MEMC_OR_4M 0xffc00000
200	#define USIU_MEMC_OR_8M 0xff800000
201	#define USIU_MEMC_OR_16M 0xff000000
202	#define USIU_MEMC_OR_32M 0xfe000000
203	#define USIU_MEMC_OR_64M 0xfc000000
204	#define USIU_MEMC_OR_128 0xf8000000
205	#define USIU_MEMC_OR_256M 0xf0000000
206	#define USIU_MEMC_OR_512M 0xe0000000
207	#define USIU_MEMC_OR_1G 0xc0000000
208	#define USIU_MEMC_OR_2G 0x80000000
209	#define USIU_MEMC_OR_4G 0x00000000
210	#define USIU_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */
211	#define USIU_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */
212	#define USIU_MEMC_OR_ACS_NORM (0<<9) /* CS asserted with addr lines /
213	#define USIU_MEMC_OR_ACS_QRTR (2<<9) /* CS asserted 1/4 after addr /
214	#define USIU_MEMC_OR_ACS_HALF (3<<9) /* CS asserted 1/2 after addr /
215	#define USIU_MEMC_OR_ETHR (1<<8) /* Extended hold time on reads */
216	#define USIU_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */
217	#define USIU_MEMC_OR_BSCY(x) ((x)<<1) /* Burst beat length in clocks */
218	#define USIU_MEMC_OR_TRLX (1<<0) /* Relaxed timing in GPCM */
219
220	/*
221	*************************************************************************
222	* Clocks and Reset Controlmer *
223	*************************************************************************
224	*/
225
226	#define USIU_SCCR_DBCT (1<<31) /* Disable backup clock for timers */
227	#define USIU_SCCR_COM(x) ((x)<<29) /* Clock output mode */
228	#define USIU_SCCR_RTDIV (1<<24) /* RTC, PIT divide by 256, not 4 */
229	#define USIU_PRQEN (1<<21) /* MSR[POW] controls frequency */
230	#define USIU_SCCR_EBDF(x) ((x)<<17) /* External bus division factor */
231	#define USIU_LME (1<<16) /* Enable limp mode */
232	#define USIU_ENGDIV(x) ((x)<<9) /* Set engineering clock divisor */
233
234	#define USIU_PLPRCR_MF(x) (((x)-1)<<20) /* PLL mult. factor (true) */
235	#define USIU_PLPRCR_SPLS (1<<16) /* System PLL locked */
236	#define USIU_PLPRCR_TEXPS (1<<14) /* Assert TEXP always */
237
238	/*
239	*************************************************************************
240	* Programmable Interval Timer *
241	*************************************************************************
242	*/
243	#define USIU_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */
244	#define USIU_PISCR_PS (1<<7) /* PIT Interrupt state */
245	#define USIU_PISCR_PIE (1<<2) /* PIT interrupt enable */
246	#define USIU_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */
247	#define USIU_PISCR_PTE (1<<0) /* PIT enable */
248
249	/*
250	*************************************************************************
251	* Time Base *
252	*************************************************************************
253	*/
254	#define USIU_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */
255	#define USIU_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */
256	#define USIU_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */
257	#define USIU_TBSCR_REFAE (1<<3) /* Enable ints for REFA */
258	#define USIU_TBSCR_REFBE (1<<2) /* Enable ints for REFB */
259	#define USIU_TBSCR_TBF (1<<1) /* TB stops on FREEZE */
260	#define USIU_TBSCR_TBE (1<<0) /* enable TB and decrementer */
261
262	/*
263	*************************************************************************
264	* SIU Interrupt Mask *
265	*************************************************************************
266	*/
267	#define USIU_SIMASK_IRM0 (1<<31)
268	#define USIU_SIMASK_LVM0 (1<<30)
269	#define USIU_SIMASK_IRM1 (1<<29)
270	#define USIU_SIMASK_LVM1 (1<<28)
271	#define USIU_SIMASK_IRM2 (1<<27)
272	#define USIU_SIMASK_LVM2 (1<<26)
273	#define USIU_SIMASK_IRM3 (1<<25)
274	#define USIU_SIMASK_LVM3 (1<<24)
275	#define USIU_SIMASK_IRM4 (1<<23)
276	#define USIU_SIMASK_LVM4 (1<<22)
277	#define USIU_SIMASK_IRM5 (1<<21)
278	#define USIU_SIMASK_LVM5 (1<<20)
279	#define USIU_SIMASK_IRM6 (1<<19)
280	#define USIU_SIMASK_LVM6 (1<<18)
281	#define USIU_SIMASK_IRM7 (1<<17)
282	#define USIU_SIMASK_LVM7 (1<<16)
283
284	/*
285	*************************************************************************
286	* SIU Module Control *
287	*************************************************************************
288	*/
289	#define USIU_SIUMCR_EARB (1<<31)
290	#define USIU_SIUMCR_EARP0 (0<<28)
291	#define USIU_SIUMCR_EARP1 (1<<28)
292	#define USIU_SIUMCR_EARP2 (2<<28)
293	#define USIU_SIUMCR_EARP3 (3<<28)
294	#define USIU_SIUMCR_EARP4 (4<<28)
295	#define USIU_SIUMCR_EARP5 (5<<28)
296	#define USIU_SIUMCR_EARP6 (6<<28)
297	#define USIU_SIUMCR_EARP7 (7<<28)
298	#define USIU_SIUMCR_DSHW (1<<23)
299	#define USIU_SIUMCR_DBGC0 (0<<21)
300	#define USIU_SIUMCR_DBGC1 (1<<21)
301	#define USIU_SIUMCR_DBGC2 (2<<21)
302	#define USIU_SIUMCR_DBGC3 (3<<21)
303	#define USIU_SIUMCR_DBPC (1<<20)
304	#define USIU_SIUMCR_ATWC (1<<19)
305	#define USIU_SIUMCR_GPC0 (0<<17)
306	#define USIU_SIUMCR_GPC1 (1<<17)
307	#define USIU_SIUMCR_GPC2 (2<<17)
308	#define USIU_SIUMCR_GPC3 (3<<17)
309	#define USIU_SIUMCR_DLK (1<<16)
310	#define USIU_SIUMCR_SC0 (0<<13)
311	#define USIU_SIUMCR_SC1 (1<<13)
312	#define USIU_SIUMCR_SC2 (2<<13)
313	#define USIU_SIUMCR_SC3 (3<<13)
314	#define USIU_SIUMCR_RCTX (1<<12)
315	#define USIU_SIUMCR_MLRC0 (0<<10)
316	#define USIU_SIUMCR_MLRC1 (1<<10)
317	#define USIU_SIUMCR_MLRC2 (2<<10)
318	#define USIU_SIUMCR_MLRC3 (3<<10)
319	#define USIU_SIUMCR_MTSC (1<<7)
320
321	/*
322	* Value to write to a key register to unlock the corresponding SIU register
323	*/
324	#define USIU_UNLOCK_KEY 0x55CCAA33
325
326	/*
327	*************************************************************************
328	* UIMB Module Control *
329	*************************************************************************
330	*/
331	#define UIMB_UMCR_STOP (1<<31)
332	#define UIMB_UMCR_IRQMUX(x) ((x)<<29)
333	#define UIMB_UMCR_HSPEED (1<<28)
334
335	/*
336	*************************************************************************
337	* QSMCM Serial Communications Interface (SCI) *
338	*************************************************************************
339	*/
340
341
342	#define QSMCM_ILDSCI(x) ((x)<<8) /* SCI interrupt level */
343
344	#define QSMCM_SCI_BAUD(x) ((x)&0x1FFF) /* Baud rate field */
345
346	#define QSMCM_SCI_LOOPS (1<<14) /* Loopback test mode */
347	#define QSMCM_SCI_WOMS (1<<13) /* Wire-or mode select */
348	#define QSMCM_SCI_ILT (1<<12) /* Idle-line detect type */
349	#define QSMCM_SCI_PT (1<<11) /* Parity type */
350	#define QSMCM_SCI_PE (1<<10) /* Parity enable */
351	#define QSMCM_SCI_M (1<<9) /* 11-bit mode */
352	#define QSMCM_SCI_WAKE (1<<8) /* Wakeup mode */
353
354	#define QSMCM_SCI_TIE (1<<7) /* Transmitter interrupt enable */
355	#define QSMCM_SCI_TCIE (1<<6) /* Transmit complete intr. enable */
356	#define QSMCM_SCI_RIE (1<<5) /* Receiver interrupt enable */
357	#define QSMCM_SCI_ILIE (1<<4) /* Idle line interrupt enable */
358	#define QSMCM_SCI_TE (1<<3) /* Transmitter enable */
359	#define QSMCM_SCI_RE (1<<2) /* Receiver enable */
360	#define QSMCM_SCI_RWU (1<<1) /* Receiver wake-up enable */
361	#define QSMCM_SCI_SBK (1<<0) /* Send break */
362
363	#define QSMCM_SCI_TDRE (1<<8) /* Transmit data register empty */
364	#define QSMCM_SCI_TC (1<<7) /* Transmit complete */
365	#define QSMCM_SCI_RDRF (1<<6) /* Receive data register full */
366	#define QSMCM_SCI_RAF (1<<5) /* Receiver active flag */
367	#define QSMCM_SCI_IDLE (1<<4) /* Idle line detected */
368	#define QSMCM_SCI_OR (1<<3) /* Receiver overrun error */
369	#define QSMCM_SCI_NF (1<<2) /* Receiver noise error flag */
370	#define QSMCM_SCI_FE (1<<1) /* Receiver framing error */
371	#define QSMCM_SCI_PF (1<<0) /* Receiver parity error */
372
373	/*
374	*************************************************************************
375	* Unified System Interface Unit *
376	*************************************************************************
377	*/
378
379	/*
380	* Memory controller registers
381	*/
382	typedef struct m5xxMEMCRegisters_ {
383	uint32_t _br;
384	uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */
385	} m5xxMEMCRegisters_t;
386
387	/*
388	* USIU itself
389	*/
390	typedef struct usiu_ {
391	/*
392	* SIU Block
393	*/
394	uint32_t siumcr;
395	uint32_t sypcr;
396	uint32_t _pad70;
397	uint16_t _pad0;
398	uint16_t swsr;
399	uint32_t sipend;
400	uint32_t simask;
401	uint32_t siel;
402	uint32_t sivec;
403	uint32_t tesr;
404	uint32_t sgpiodt1;
405	uint32_t sgpiodt2;
406	uint32_t sgpiocr;
407	uint32_t emcr;
408	uint8_t _pad71[0x03C-0x034];
409	uint32_t pdmcr;
410	uint8_t _pad2[0x100-0x40];
411
412	/*
413	* MEMC Block
414	*/
415	m5xxMEMCRegisters_t memc[4];
416	uint8_t _pad7[0x140-0x120];
417	uint32_t dmbr;
418	uint32_t dmor;
419	uint8_t _pad8[0x178-0x148];
420	uint16_t mstat;
421	uint8_t _pad9[0x200-0x17A];
422
423	/*
424	* System integration timers
425	*/
426	uint16_t tbscr;
427	uint16_t _pad10;
428	uint32_t tbreff0;
429	uint32_t tbreff1;
430	uint8_t _pad11[0x220-0x20c];
431	uint16_t rtcsc;
432	uint16_t _pad12;
433	uint32_t rtc;
434	uint32_t rtsec;
435	uint32_t rtcal;
436	uint32_t _pad13[4];
437	uint16_t piscr;
438	uint16_t _pad14;
439	uint16_t pitc;
440	uint16_t _pad_14_1;
441	uint16_t pitr;
442	uint16_t _pad_14_2;
443	uint8_t _pad15[0x280-0x24c];
444
445	/*
446	* Clocks and Reset
447	*/
448	uint32_t sccr;
449	uint32_t plprcr;
450	uint16_t rsr;
451	uint16_t _pad72;
452	uint16_t colir;
453	uint16_t _pad73;
454	uint16_t vsrmcr;
455	uint8_t _pad16[0x300-0x292];
456
457	/*
458	* System integration timers keys
459	*/
460	uint32_t tbscrk;
461	uint32_t tbreff0k;
462	uint32_t tbreff1k;
463	uint32_t tbk;
464	uint32_t _pad17[4];
465	uint32_t rtcsk;
466	uint32_t rtck;
467	uint32_t rtseck;
468	uint32_t rtcalk;
469	uint32_t _pad18[4];
470	uint32_t piscrk;
471	uint32_t pitck;
472	uint8_t _pad19[0x380-0x348];
473
474	/*
475	* Clocks and Reset Keys
476	*/
477	uint32_t sccrk;
478	uint32_t plprck;
479	uint32_t rsrk;
480	uint8_t _pad20[0x400-0x38c];
481	} usiu_t;
482
483	extern volatile usiu_t usiu; /* defined in linkcmds */
484
485	/*
486	*************************************************************************
487	* Inter-Module Bus and Devices *
488	*************************************************************************
489	*/
490
491	/*
492	* Dual-Port TPU RAM (DPTRAM)
493	*/
494	typedef struct m5xxDPTRAMRegisters_ {
495	uint8_t pad[0x4000]; /* define later */
496	} m5xxDPTRAMRegisters_t;
497
498	/*
499	* Time Processor Unit (TPU)
500	*/
501	typedef struct m5xxTPU3Registers_ {
502	uint8_t pad[0x400]; /* define later */
503	} m5xxTPU3Registers_t;
504
505	/*
506	* Queued A/D Converter (QADC)
507	*/
508	typedef struct m5xxQADC64Registers_ {
509	uint8_t pad[0x400]; /* define later */
510	} m5xxQADC64Registers_t;
511
512	/*
513	* Serial Communications Interface (SCI)
514	*/
515	typedef struct m5xxSCIRegisters_ {
516	uint16_t sccr0;
517	uint16_t sccr1;
518	uint16_t scsr;
519	uint16_t scdr;
520	} m5xxSCIRegisters_t;
521
522	/*
523	* Serial Peripheral Interface (SPI)
524	*/
525	typedef struct m5xxSPIRegisters_ {
526	uint16_t spcr0;
527	uint16_t spcr1;
528	uint16_t spcr2;
529	uint8_t spcr3;
530	uint8_t spsr;
531	} m5xxSPIRegisters_t;
532
533	/*
534	* Queued Serial Multi-Channel Module (QSMCM)
535	*/
536	typedef struct m5xxQSMCMRegisters_ {
537	uint16_t qsmcmmcr;
538	uint16_t qtest;
539	uint16_t qdsci_il;
540	uint16_t qspi_il;
541
542	m5xxSCIRegisters_t sci1;
543
544	uint8_t _pad10[0x14-0x10];
545
546	uint16_t portqs;
547	uint16_t pqspar;
548	m5xxSPIRegisters_t spi;
549
550	m5xxSCIRegisters_t sci2;
551
552	uint16_t qsci1cr;
553	uint16_t qsci1sr;
554	uint16_t sctq[0x10];
555	uint16_t scrq[0x10];
556
557	uint8_t _pad6C[0x140-0x06C];
558
559	uint16_t recram[0x20];
560	uint16_t tranram[0x20];
561	uint16_t comdram[0x20];
562	} m5xxQSMCMRegisters_t;
563
564	/*
565	* Modular Input/Output System (MIOS)
566	*/
567	typedef struct m5xxMIOS1Registers_ {
568	uint8_t pad[0x1000]; /* define later */
569	} m5xxMIOS1Registers_t;
570
571	/*
572	* Can 2.0B Controller (TouCAN)
573	*/
574	typedef struct m5xxTouCANRegisters_ {
575	uint8_t pad[0x400]; /* define later */
576	} m5xxTouCANRegisters_t;
577
578	/*
579	* U-Bus to IMB3 Bus Interface Module (UIMB)
580	*/
581	typedef struct m5xxUIMBRegisters_ {
582	uint32_t umcr;
583	uint32_t utstcreg;
584	uint32_t uipend;
585	} m5xxUIMBRegisters_t;
586
587	/*
588	* IMB itself
589	*/
590	typedef struct imb_ {
591	m5xxDPTRAMRegisters_t dptram;
592	m5xxTPU3Registers_t tpu[2];
593	m5xxQADC64Registers_t qadc[2];
594	m5xxQSMCMRegisters_t qsmcm;
595	uint8_t _pad5200[0x6000-0x5200];
596	m5xxMIOS1Registers_t mios;
597	m5xxTouCANRegisters_t toucan[2];
598	uint8_t _pad7800[0x7F80-0x7800];
599	m5xxUIMBRegisters_t uimb;
600	} imb_t;
601
602	extern volatile imb_t imb; /* defined in linkcmds */
603
604
605	/*
606	* Methods shared across libcpu and the BSP.
607	*/
608	void clockOn(void* unused);
609	void clockOff(void* unused);
610	int clockIsOn(void* unused);
611	rtems_isr Clock_isr(rtems_vector_number vector);
612
613	#ifdef __cplusplus
614	}
615	#endif
616
617	#endif /* ASM */
618
619	#endif /* _MPC5XX_H */

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