source: rtems/bsps/powerpc/include/mpc55xx/regs-mmu.h @ 9964895

5
Last change on this file since 9964895 was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 5.9 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx
5 */
6
7/*
8 * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
9 *
10 *  embedded brains GmbH
11 *  Obere Lagerstr. 30
12 *  82178 Puchheim
13 *  Germany
14 *  <rtems@embedded-brains.de>
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 */
20
21/*********************************************************************
22 *
23 * Copyright:
24 *  Freescale Semiconductor, INC. All Rights Reserved.
25 *  You are hereby granted a copyright license to use, modify, and
26 *  distribute the SOFTWARE so long as this entire notice is
27 *  retained without alteration in any modified and/or redistributed
28 *  versions, and that such modified versions are clearly identified
29 *  as such. No licenses are granted by implication, estoppel or
30 *  otherwise under any patents or trademarks of Freescale
31 *  Semiconductor, Inc. This software is provided on an "AS IS"
32 *  basis and without warranty.
33 *
34 *  To the maximum extent permitted by applicable law, Freescale
35 *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
36 *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
37 *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
38 *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
39 *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
40 *
41 *  To the maximum extent permitted by applicable law, IN NO EVENT
42 *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
43 *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
44 *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
45 *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
46 *
47 *  Freescale Semiconductor assumes no responsibility for the
48 *  maintenance and support of this software
49 *
50 ********************************************************************/
51
52#ifndef LIBCPU_POWERPC_MPC55XX_REGS_MMU_H
53#define LIBCPU_POWERPC_MPC55XX_REGS_MMU_H
54
55#include <stdint.h>
56
57#include <bspopts.h>
58
59#ifdef  __cplusplus
60extern "C" {
61#endif
62
63/****************************************************************************/
64/*                          MMU                                             */
65/****************************************************************************/
66    struct MMU_tag {
67        union {
68            uint32_t R;
69            struct {
70                uint32_t : 2;
71                uint32_t TLBSEL : 2;
72                uint32_t : 7;
73                uint32_t ESEL : 5;
74                uint32_t : 11;
75                uint32_t NV : 5;
76            } B;
77        } MAS0;
78
79        union {
80            uint32_t R;
81            struct {
82                uint32_t VALID : 1;
83                uint32_t IPROT : 1;
84                uint32_t : 6;
85                uint32_t TID : 8;
86                uint32_t : 3;
87                uint32_t TS : 1;
88                uint32_t TSIZE : 5;
89                uint32_t : 7;
90            } B;
91        } MAS1;
92
93        union {
94            uint32_t R;
95            struct {
96                uint32_t EPN : 22;
97                uint32_t : 4;
98                uint32_t VLE : 1;
99                uint32_t W : 1;
100                uint32_t I : 1;
101                uint32_t M : 1;
102                uint32_t G : 1;
103                uint32_t E : 1;
104            } B;
105        } MAS2;
106
107        union {
108            uint32_t R;
109            struct {
110                uint32_t RPN : 22;
111                uint32_t U0 : 1;
112                uint32_t U1 : 1;
113                uint32_t U2 : 1;
114                uint32_t U3 : 1;
115                uint32_t UX : 1;
116                uint32_t SX : 1;
117                uint32_t UW : 1;
118                uint32_t SW : 1;
119                uint32_t UR : 1;
120                uint32_t SR : 1;
121            } B;
122        } MAS3;
123    };
124
125        union MMU_MAS4_tag {
126            uint32_t R;
127            struct {
128                uint32_t : 2;
129                uint32_t TLBSELD : 2;
130                uint32_t : 10;
131                uint32_t TIDSELD : 2;
132                uint32_t : 4;
133                uint32_t TSIZED : 4;
134                uint32_t : 3;
135                uint32_t WD : 1;
136                uint32_t ID : 1;
137                uint32_t MD : 1;
138                uint32_t GD : 1;
139                uint32_t ED : 1;
140            } B;
141        };
142
143        union MMU_MAS6_tag {
144            uint32_t R;
145            struct {
146                uint32_t : 8;
147                uint32_t SPID : 8;
148                uint32_t : 15;
149                uint32_t SAS : 1;
150            } B;
151        };
152
153#define MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addreff, addrreal, size, x, w, r, io) \
154  { \
155    .MAS0 = { .B = { .TLBSEL = 1, .ESEL = (idx) } }, \
156    .MAS1 = { .B = { \
157      .VALID = 1, .IPROT = 1, .TID = 0, .TS = 0, .TSIZE = (size) } \
158    }, \
159    .MAS2 = { .B = { \
160      .EPN = (addreff) >> 10, .VLE = 0, \
161      .W = (io) == 2, .I = (io) == 1, .M = 0, .G = (io) == 1, .E = 0 } \
162    }, \
163    .MAS3 = { .B = { \
164      .RPN = (addrreal) >> 10, .U0 = 0, .U1 = 0, .U2 = 0, .U3 = 0, .UX = 0, \
165      .SX = (x), .UW = 0, .SW = (w), .UR = 0, .SR = (r) } \
166    } \
167  }
168
169#define MPC55XX_MMU_TAG_INITIALIZER(idx, addr, size, x, w, r, io) \
170  MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addr, addr, size, x, w, r, io)
171
172#define MPC55XX_MMU_1K 0
173#define MPC55XX_MMU_2K 1
174#define MPC55XX_MMU_4K 2
175#define MPC55XX_MMU_8K 3
176#define MPC55XX_MMU_16K 4
177#define MPC55XX_MMU_32K 5
178#define MPC55XX_MMU_64K 6
179#define MPC55XX_MMU_128K 7
180#define MPC55XX_MMU_256K 8
181#define MPC55XX_MMU_512K 9
182#define MPC55XX_MMU_1M 10
183#define MPC55XX_MMU_2M 11
184#define MPC55XX_MMU_4M 12
185#define MPC55XX_MMU_8M 13
186#define MPC55XX_MMU_16M 14
187#define MPC55XX_MMU_32M 15
188#define MPC55XX_MMU_64M 16
189#define MPC55XX_MMU_128M 17
190#define MPC55XX_MMU_256M 18
191#define MPC55XX_MMU_512M 19
192#define MPC55XX_MMU_1G 20
193#define MPC55XX_MMU_2G 21
194#define MPC55XX_MMU_4G 22
195
196#ifdef  __cplusplus
197}
198#endif /* __cplusplus */
199
200#endif /* LIBCPU_POWERPC_MPC55XX_REGS_MMU_H */
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