1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. |
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9 | * |
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10 | * embedded brains GmbH |
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11 | * Obere Lagerstr. 30 |
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12 | * 82178 Puchheim |
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13 | * Germany |
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14 | * <rtems@embedded-brains.de> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | /********************************************************************* |
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22 | * |
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23 | * Copyright: |
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24 | * Freescale Semiconductor, INC. All Rights Reserved. |
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25 | * You are hereby granted a copyright license to use, modify, and |
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26 | * distribute the SOFTWARE so long as this entire notice is |
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27 | * retained without alteration in any modified and/or redistributed |
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28 | * versions, and that such modified versions are clearly identified |
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29 | * as such. No licenses are granted by implication, estoppel or |
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30 | * otherwise under any patents or trademarks of Freescale |
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31 | * Semiconductor, Inc. This software is provided on an "AS IS" |
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32 | * basis and without warranty. |
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33 | * |
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34 | * To the maximum extent permitted by applicable law, Freescale |
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35 | * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, |
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36 | * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A |
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37 | * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH |
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38 | * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) |
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39 | * AND ANY ACCOMPANYING WRITTEN MATERIALS. |
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40 | * |
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41 | * To the maximum extent permitted by applicable law, IN NO EVENT |
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42 | * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER |
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43 | * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, |
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44 | * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER |
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45 | * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. |
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46 | * |
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47 | * Freescale Semiconductor assumes no responsibility for the |
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48 | * maintenance and support of this software |
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49 | * |
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50 | ********************************************************************/ |
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51 | |
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52 | #ifndef LIBCPU_POWERPC_MPC55XX_REGS_MMU_H |
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53 | #define LIBCPU_POWERPC_MPC55XX_REGS_MMU_H |
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54 | |
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55 | #include <stdint.h> |
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56 | |
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57 | #include <bspopts.h> |
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58 | |
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59 | #ifdef __cplusplus |
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60 | extern "C" { |
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61 | #endif |
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62 | |
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63 | /****************************************************************************/ |
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64 | /* MMU */ |
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65 | /****************************************************************************/ |
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66 | struct MMU_tag { |
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67 | union { |
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68 | uint32_t R; |
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69 | struct { |
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70 | uint32_t : 2; |
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71 | uint32_t TLBSEL : 2; |
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72 | uint32_t : 7; |
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73 | uint32_t ESEL : 5; |
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74 | uint32_t : 11; |
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75 | uint32_t NV : 5; |
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76 | } B; |
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77 | } MAS0; |
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78 | |
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79 | union { |
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80 | uint32_t R; |
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81 | struct { |
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82 | uint32_t VALID : 1; |
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83 | uint32_t IPROT : 1; |
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84 | uint32_t : 6; |
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85 | uint32_t TID : 8; |
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86 | uint32_t : 3; |
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87 | uint32_t TS : 1; |
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88 | uint32_t TSIZE : 5; |
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89 | uint32_t : 7; |
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90 | } B; |
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91 | } MAS1; |
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92 | |
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93 | union { |
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94 | uint32_t R; |
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95 | struct { |
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96 | uint32_t EPN : 22; |
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97 | uint32_t : 4; |
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98 | uint32_t VLE : 1; |
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99 | uint32_t W : 1; |
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100 | uint32_t I : 1; |
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101 | uint32_t M : 1; |
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102 | uint32_t G : 1; |
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103 | uint32_t E : 1; |
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104 | } B; |
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105 | } MAS2; |
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106 | |
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107 | union { |
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108 | uint32_t R; |
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109 | struct { |
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110 | uint32_t RPN : 22; |
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111 | uint32_t U0 : 1; |
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112 | uint32_t U1 : 1; |
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113 | uint32_t U2 : 1; |
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114 | uint32_t U3 : 1; |
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115 | uint32_t UX : 1; |
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116 | uint32_t SX : 1; |
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117 | uint32_t UW : 1; |
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118 | uint32_t SW : 1; |
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119 | uint32_t UR : 1; |
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120 | uint32_t SR : 1; |
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121 | } B; |
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122 | } MAS3; |
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123 | }; |
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124 | |
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125 | union MMU_MAS4_tag { |
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126 | uint32_t R; |
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127 | struct { |
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128 | uint32_t : 2; |
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129 | uint32_t TLBSELD : 2; |
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130 | uint32_t : 10; |
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131 | uint32_t TIDSELD : 2; |
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132 | uint32_t : 4; |
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133 | uint32_t TSIZED : 4; |
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134 | uint32_t : 3; |
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135 | uint32_t WD : 1; |
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136 | uint32_t ID : 1; |
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137 | uint32_t MD : 1; |
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138 | uint32_t GD : 1; |
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139 | uint32_t ED : 1; |
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140 | } B; |
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141 | }; |
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142 | |
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143 | union MMU_MAS6_tag { |
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144 | uint32_t R; |
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145 | struct { |
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146 | uint32_t : 8; |
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147 | uint32_t SPID : 8; |
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148 | uint32_t : 15; |
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149 | uint32_t SAS : 1; |
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150 | } B; |
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151 | }; |
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152 | |
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153 | #define MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addreff, addrreal, size, x, w, r, io) \ |
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154 | { \ |
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155 | .MAS0 = { .B = { .TLBSEL = 1, .ESEL = (idx) } }, \ |
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156 | .MAS1 = { .B = { \ |
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157 | .VALID = 1, .IPROT = 1, .TID = 0, .TS = 0, .TSIZE = (size) } \ |
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158 | }, \ |
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159 | .MAS2 = { .B = { \ |
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160 | .EPN = (addreff) >> 10, .VLE = 0, \ |
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161 | .W = (io) == 2, .I = (io) == 1, .M = 0, .G = (io) == 1, .E = 0 } \ |
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162 | }, \ |
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163 | .MAS3 = { .B = { \ |
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164 | .RPN = (addrreal) >> 10, .U0 = 0, .U1 = 0, .U2 = 0, .U3 = 0, .UX = 0, \ |
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165 | .SX = (x), .UW = 0, .SW = (w), .UR = 0, .SR = (r) } \ |
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166 | } \ |
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167 | } |
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168 | |
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169 | #define MPC55XX_MMU_TAG_INITIALIZER(idx, addr, size, x, w, r, io) \ |
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170 | MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addr, addr, size, x, w, r, io) |
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171 | |
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172 | #define MPC55XX_MMU_1K 0 |
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173 | #define MPC55XX_MMU_2K 1 |
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174 | #define MPC55XX_MMU_4K 2 |
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175 | #define MPC55XX_MMU_8K 3 |
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176 | #define MPC55XX_MMU_16K 4 |
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177 | #define MPC55XX_MMU_32K 5 |
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178 | #define MPC55XX_MMU_64K 6 |
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179 | #define MPC55XX_MMU_128K 7 |
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180 | #define MPC55XX_MMU_256K 8 |
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181 | #define MPC55XX_MMU_512K 9 |
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182 | #define MPC55XX_MMU_1M 10 |
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183 | #define MPC55XX_MMU_2M 11 |
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184 | #define MPC55XX_MMU_4M 12 |
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185 | #define MPC55XX_MMU_8M 13 |
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186 | #define MPC55XX_MMU_16M 14 |
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187 | #define MPC55XX_MMU_32M 15 |
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188 | #define MPC55XX_MMU_64M 16 |
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189 | #define MPC55XX_MMU_128M 17 |
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190 | #define MPC55XX_MMU_256M 18 |
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191 | #define MPC55XX_MMU_512M 19 |
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192 | #define MPC55XX_MMU_1G 20 |
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193 | #define MPC55XX_MMU_2G 21 |
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194 | #define MPC55XX_MMU_4G 22 |
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195 | |
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196 | #ifdef __cplusplus |
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197 | } |
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198 | #endif /* __cplusplus */ |
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199 | |
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200 | #endif /* LIBCPU_POWERPC_MPC55XX_REGS_MMU_H */ |
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