1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx |
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5 | * |
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6 | * @brief Register definitions. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef LIBCPU_POWERPC_MPC55XX_REG_DEFS_H |
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24 | #define LIBCPU_POWERPC_MPC55XX_REG_DEFS_H |
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25 | |
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26 | #include <bspopts.h> |
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27 | |
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28 | #if MPC55XX_CHIP_FAMILY == 551 |
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29 | #define FLASH_BIUCR 0xFFFF801C |
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30 | #else |
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31 | #define FLASH_BIUCR 0xC3F8801C |
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32 | #endif |
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33 | |
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34 | /* |
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35 | * Definitions for FLASH_BIUCR (Flash BIU Control Register) |
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36 | */ |
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37 | |
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38 | /* Fields for Flash Bus Interface Control */ |
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39 | /* Fields for Prefetch Control (MnPFE Master n Prefetch Enable) */ |
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40 | |
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41 | /* Fields for M3PFE (Master 3 (EBI) prefetch enable bit [12]) */ |
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42 | #define FLASH_BUICR_EBI_PREFTCH 0x00080000 |
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43 | |
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44 | /* Fields for M2PFE (Master 2 (eDMA) prefetch enable bit [13]) */ |
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45 | #define FLASH_BUICR_EDMA_PREFTCH 0x00040000 |
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46 | |
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47 | /* Fields for M1PFE (Master 1 (Nexus) prefetch enable bit [14]) */ |
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48 | #define FLASH_BUICR_NEX_PREFTCH 0x00020000 |
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49 | |
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50 | /* Fields for M0PFE (Master 0 (e200z core) prefetch enable bit [15]) */ |
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51 | #define FLASH_BUICR_CPU_PREFTCH 0x00010000 |
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52 | |
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53 | /* Fields for APC (access pipelining control bits [16:18]) */ |
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54 | #define FLASH_BUICR_APC_0 0x00000000 |
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55 | #define FLASH_BUICR_APC_1 0x00002000 |
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56 | #define FLASH_BUICR_APC_2 0x00004000 |
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57 | #define FLASH_BUICR_APC_3 0x00006000 |
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58 | #define FLASH_BUICR_APC_4 0x00008000 |
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59 | #define FLASH_BUICR_APC_5 0x0000A000 |
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60 | #define FLASH_BUICR_APC_6 0x0000C000 |
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61 | #define FLASH_BUICR_APC_NO 0x0000E000 |
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62 | |
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63 | /* Fields for WWSC (write wait state control bits [19:20]) */ |
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64 | #define FLASH_BUICR_WWSC_1 0x00000800 |
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65 | #define FLASH_BUICR_WWSC_2 0x00001000 |
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66 | #define FLASH_BUICR_WWSC_3 0x00001800 |
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67 | |
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68 | /* Fields for RWSC (read wait state control bits [21:23]) */ |
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69 | #define FLASH_BUICR_RWSC_0 0x00000000 |
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70 | #define FLASH_BUICR_RWSC_1 0x00000100 |
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71 | #define FLASH_BUICR_RWSC_2 0x00000200 |
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72 | #define FLASH_BUICR_RWSC_3 0x00000300 |
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73 | #define FLASH_BUICR_RWSC_4 0x00000400 |
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74 | #define FLASH_BUICR_RWSC_5 0x00000500 |
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75 | #define FLASH_BUICR_RWSC_6 0x00000600 |
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76 | #define FLASH_BUICR_RWSC_7 0x00000700 |
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77 | |
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78 | /* Fields for DPFEN (data prefetch enable bits [24:25]) */ |
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79 | #define FLASH_BUICR_DPFEN_0 0x00000000 |
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80 | #define FLASH_BUICR_DPFEN_1 0x00000040 |
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81 | #define FLASH_BUICR_DPFEN_3 0x000000C0 |
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82 | |
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83 | /* Fields for IPFEN (instruction prefetch enable bits [26:27]) */ |
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84 | #define FLASH_BUICR_IPFEN_0 0x00000000 |
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85 | #define FLASH_BUICR_IPFEN_1 0x00000010 |
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86 | #define FLASH_BUICR_IPFEN_3 0x00000030 |
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87 | |
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88 | /* Fields for PFLIM (additional line prefetch (limit) bits [28:30]) */ |
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89 | #define FLASH_BUICR_PFLIM_0 0x00000000 |
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90 | #define FLASH_BUICR_PFLIM_1 0x00000002 |
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91 | #define FLASH_BUICR_PFLIM_2 0x00000004 |
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92 | #define FLASH_BUICR_PFLIM_3 0x00000006 |
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93 | #define FLASH_BUICR_PFLIM_4 0x00000008 |
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94 | #define FLASH_BUICR_PFLIM_5 0x0000000A |
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95 | #define FLASH_BUICR_PFLIM_6 0x0000000C |
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96 | |
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97 | /* Fields for BFEN (enable line read buffer hits bit [31]) */ |
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98 | #define FLASH_BUICR_BFEN 0x00000001 |
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99 | |
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100 | #endif /* LIBCPU_POWERPC_MPC55XX_REG_DEFS_H */ |
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