1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx |
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5 | * |
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6 | * @brief Documentation for this file |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | /** |
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24 | * @defgroup mpc55xx BSP for MPC55xx boards |
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25 | */ |
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26 | |
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27 | /** |
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28 | * @defgroup mpc55xx_config Configuration files |
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29 | * |
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30 | * @ingroup mpc55xx |
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31 | * |
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32 | * Makefiles, configure scripts etc. |
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33 | */ |
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34 | |
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35 | /** |
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36 | * @page mpc55xx_ext_doc External Documentation |
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37 | * |
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38 | * @section mpc55xx_ext_doc_mpc5567rm_1 MPC5567 Microcontroller Reference Manual (Rev. 1, January 2007, Volume 1 of 2) |
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39 | * @section mpc55xx_ext_doc_mpc5567rm_2 MPC5567 Microcontroller Reference Manual (Rev. 1, January 2007, Volume 2 of 2) |
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40 | */ |
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41 | |
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42 | #ifndef LIBCPU_POWERPC_MPC55XX_H |
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43 | #define LIBCPU_POWERPC_MPC55XX_H |
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44 | |
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45 | #include <mpc55xx/regs.h> |
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46 | #include <mpc55xx/regs-mmu.h> |
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47 | |
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48 | #include <libcpu/powerpc-utility.h> |
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49 | |
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50 | #ifdef __cplusplus |
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51 | extern "C" { |
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52 | #endif /* __cplusplus */ |
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53 | |
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54 | int mpc55xx_flash_copy(void *dest, const void *src, size_t nbytes); |
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55 | int mpc55xx_flash_copy_op(void *rdest, const void *src, size_t nbytes, |
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56 | uint32_t opmask, uint32_t *p_fail_addr); |
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57 | int mpc55xx_flash_size(uint32_t *p_size); |
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58 | int mpc55xx_flash_writable(void); |
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59 | uint32_t mpc55xx_flash_address(void); |
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60 | void mpc55xx_flash_set_read_only(void); |
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61 | void mpc55xx_flash_set_read_write(void); |
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62 | |
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63 | int mpc55xx_physical_address(const void *addr, uint32_t *p_result); |
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64 | int mpc55xx_mapped_address(const void *addr, uint32_t *p_result); |
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65 | |
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66 | /* Bits for opmask. */ |
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67 | #define MPC55XX_FLASH_BLANK_CHECK 0x01 |
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68 | #define MPC55XX_FLASH_UNLOCK 0x02 |
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69 | #define MPC55XX_FLASH_ERASE 0x04 |
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70 | #define MPC55XX_FLASH_PROGRAM 0x08 |
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71 | #define MPC55XX_FLASH_VERIFY 0x10 |
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72 | |
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73 | /* Error returns. CONFIG or SIZE might mean you just |
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74 | * need to check for new configuration bits. |
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75 | * SIZE and RANGE mean you are outside of a known flash region. |
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76 | * ERASE means the erase failed, |
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77 | * PROGRAM means the program failed, |
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78 | * BLANK means it wasn't blank and BLANK_CHECK was specified, |
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79 | * VERIFY means VERIFY was set and it didn't match the source, |
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80 | * and LOCK means either the locking failed or you needed to |
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81 | * specify MPC55XX_FLASH_UNLOCK and didn't. |
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82 | */ |
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83 | #define MPC55XX_FLASH_CONFIG_ERR (-1) |
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84 | #define MPC55XX_FLASH_SIZE_ERR (-2) |
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85 | #define MPC55XX_FLASH_RANGE_ERR (-3) |
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86 | #define MPC55XX_FLASH_ERASE_ERR (-4) |
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87 | #define MPC55XX_FLASH_PROGRAM_ERR (-5) |
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88 | #define MPC55XX_FLASH_NOT_BLANK_ERR (-6) |
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89 | #define MPC55XX_FLASH_VERIFY_ERR (-7) |
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90 | #define MPC55XX_FLASH_LOCK_ERR (-8) |
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91 | |
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92 | #define MPC55XX_CACHE_ALIGNED_MASK ((uintptr_t) 0x1f) |
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93 | |
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94 | #define MPC55XX_CACHE_LINE_SIZE 32 |
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95 | |
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96 | /** |
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97 | * @brief Returns true if the buffer starting at @a s of size @a n is cache aligned. |
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98 | */ |
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99 | static inline int mpc55xx_is_cache_aligned( const void *s, size_t n) |
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100 | { |
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101 | return !(((uintptr_t) s & MPC55XX_CACHE_ALIGNED_MASK) || (n & MPC55XX_CACHE_ALIGNED_MASK)); |
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102 | } |
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103 | |
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104 | static inline uintptr_t mpc55xx_cache_aligned_start( const void *s) |
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105 | { |
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106 | return ((uintptr_t) s & MPC55XX_CACHE_ALIGNED_MASK) ? (((uintptr_t) s & ~MPC55XX_CACHE_ALIGNED_MASK) + MPC55XX_CACHE_LINE_SIZE) : (uintptr_t)s; |
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107 | } |
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108 | |
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109 | static inline size_t mpc55xx_non_cache_aligned_size( const void *s) |
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110 | { |
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111 | return (uintptr_t) mpc55xx_cache_aligned_start( s) - (uintptr_t) s; |
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112 | } |
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113 | |
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114 | static inline size_t mpc55xx_cache_aligned_size( const void *s, size_t n) |
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115 | { |
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116 | return (n - mpc55xx_non_cache_aligned_size( s)) & ~MPC55XX_CACHE_ALIGNED_MASK; |
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117 | } |
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118 | |
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119 | /** |
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120 | * @brief Returns the number of leading zeros. |
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121 | */ |
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122 | static inline uint32_t mpc55xx_count_leading_zeros( uint32_t value) |
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123 | { |
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124 | uint32_t count; |
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125 | __asm__ ( |
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126 | "cntlzw %0, %1;" |
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127 | : "=r" (count) |
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128 | : "r" (value) |
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129 | ); |
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130 | return count; |
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131 | } |
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132 | |
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133 | static inline void mpc55xx_wait_for_interrupt(void) |
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134 | { |
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135 | #ifdef MPC55XX_HAS_WAIT_INSTRUCTION |
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136 | __asm__ volatile ("wait"); |
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137 | #else |
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138 | __asm__ volatile (""); |
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139 | #endif |
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140 | } |
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141 | |
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142 | static inline void mpc55xx_mmu_apply_config(const struct MMU_tag *config) |
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143 | { |
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144 | PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS0, config->MAS0.R); |
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145 | PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1, config->MAS1.R); |
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146 | PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS2, config->MAS2.R); |
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147 | PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS3, config->MAS3.R); |
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148 | __asm__ volatile ("tlbwe"); |
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149 | } |
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150 | |
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151 | #ifdef __cplusplus |
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152 | } |
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153 | #endif /* __cplusplus */ |
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154 | |
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155 | #endif /* LIBCPU_POWERPC_MPC55XX_H */ |
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