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fsl-mpc556x.h @ 9964895

Last change on this file since 9964895 was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

The make preinstall step itself needs time and disk space.

Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.

There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.

The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.

An introduction of a new build system is difficult.

Include paths specified by the -B option are system headers. This may suppress warnings.

The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

cpukit/include

cpukit/score/cpu/@RTEMS_CPU@/include

cpukit/libnetworking

The new BSP include directories are:

bsps/include

bsps/@RTEMS_CPU@/include

bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

Property mode set to 100644

File size: 156.7 KB

Line
1	/*
2	* Modifications of the original file provided by Freescale are:
3	*
4	* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
5	*
6	* embedded brains GmbH
7	* Obere Lagerstr. 30
8	* 82178 Puchheim
9	* Germany
10	* <info@embedded-brains.de>
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions
14	* are met:
15	* 1. Redistributions of source code must retain the above copyright
16	* notice, this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright
18	* notice, this list of conditions and the following disclaimer in the
19	* documentation and/or other materials provided with the distribution.
20	*
21	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32	*/
33
34	/**************************************************************************/
35	/* FILE NAME: mpc5567.h COPYRIGHT (c) Freescale 2007 */
36	/* VERSION: 1.5 All Rights Reserved */
37	/* */
38	/* DESCRIPTION: */
39	/* This file contain all of the register and bit field definitions for */
40	/* MPC5567. */
41	/========================================================================/
42	/* UPDATE HISTORY */
43	/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
44	/* --- ----------- --------- --------------------- */
45	/* 1.0 G. Emerson 03/Jan/06 Initial version. */
46	/* 1.1 G. Emerson 27/Mar/06 Fix issue with Flexcan BCC field. */
47	/* 1.2 S. Mathieson 28/Jul/06 Change Flexcan BCC bit to MBFEN */
48	/* Add Flexcan bits WRNEN, SRXDIS, */
49	/* TWRNMSK, RWRNMSK,TWRNINT,RWRNINT */
50	/* 1.3 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */
51	/* to DPB to align with documentation. */
52	/* 1.4 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */
53	/* alternate configuration. */
54	/* INTC, correction to the number of PSR */
55	/* registers. */
56	/* Updates to bitfield sizes in MBSSUTR, */
57	/* MBIVEC, MBIDX & RSBIR. RSBIR, SELEC */
58	/* changed to SEL & RFRFCFR, FNUM changed */
59	/* to SEL to align with documentation. */
60	/* Various register/ bitfield updates to */
61	/* correct errors (MCR, TMODE bit removed.*/
62	/* PADR register removed. PIER1, DRDIE bit*/
63	/* removed & PIFR1, DRDIF removed. PCR1, */
64	/* Filter bypass bit removed). */
65	/* 1.5 S. Mathieson 25/Apr/07 SRAM size changed from 64K to 80K. */
66	/* */
67	/**************************************************************************/
68	/>>>>NOTE! this file is auto-generated please do not edit it!<<<</
69
70	#ifndef _MPC5567_H_
71	#define _MPC5567_H_
72
73	#ifndef ASM
74
75	#include <stdint.h>
76
77	#include <mpc55xx/regs-edma.h>
78
79	#ifdef __cplusplus
80	extern "C" {
81	#endif
82
83	#ifdef __MWERKS__
84	#pragma push
85	#pragma ANSI_strict off
86	#endif
87
88	/****************************************************************************/
89	/* MODULE : PBRIDGE_A Peripheral Bridge */
90	/****************************************************************************/
91	struct PBRIDGE_A_tag {
92	union {
93	uint32_t R;
94	struct {
95	uint32_t MBW0:1;
96	uint32_t MTR0:1;
97	uint32_t MTW0:1;
98	uint32_t MPL0:1;
99	uint32_t MBW1:1;
100	uint32_t MTR1:1;
101	uint32_t MTW1:1;
102	uint32_t MPL1:1;
103	uint32_t MBW2:1;
104	uint32_t MTR2:1;
105	uint32_t MTW2:1;
106	uint32_t MPL2:1;
107	uint32_t MBW3:1;
108	uint32_t MTR3:1;
109	uint32_t MTW3:1;
110	uint32_t MPL3:1;
111
112	uint32_t MBW4:1; /* FEC */
113	uint32_t MTR4:1;
114	uint32_t MTW4:1;
115	uint32_t MPL4:1;
116
117	uint32_t:4;
118
119	uint32_t MBW6:1; /* FLEXRAY */
120	uint32_t MTR6:1;
121	uint32_t MTW6:1;
122	uint32_t MPL6:1;
123
124	uint32_t:4;
125	} B;
126	} MPCR; /* Master Privilege Control Register */
127
128	uint32_t pbridge_a_reserved2[7];
129
130	union {
131	uint32_t R;
132	struct {
133	uint32_t BW0:1;
134	uint32_t SP0:1;
135	uint32_t WP0:1;
136	uint32_t TP0:1;
137	uint32_t:28;
138	} B;
139	} PACR0;
140
141	uint32_t pbridge_a_reserved3[7];
142
143	union {
144	uint32_t R;
145	struct {
146	uint32_t BW0:1;
147	uint32_t SP0:1;
148	uint32_t WP0:1;
149	uint32_t TP0:1;
150	uint32_t BW1:1;
151	uint32_t SP1:1;
152	uint32_t WP1:1;
153	uint32_t TP1:1;
154	uint32_t BW2:1;
155	uint32_t SP2:1;
156	uint32_t WP2:1;
157	uint32_t TP2:1;
158	uint32_t:4;
159	uint32_t BW4:1;
160	uint32_t SP4:1;
161	uint32_t WP4:1;
162	uint32_t TP4:1;
163	uint32_t:12;
164	} B;
165	} OPACR0;
166
167	union {
168	uint32_t R;
169	struct {
170
171	uint32_t BW0:1; /* EMIOS */
172	uint32_t SP0:1;
173	uint32_t WP0:1;
174	uint32_t TP0:1;
175
176	uint32_t:28;
177	} B;
178	} OPACR1;
179
180	union {
181	uint32_t R;
182	struct {
183	uint32_t BW0:1;
184	uint32_t SP0:1;
185	uint32_t WP0:1;
186	uint32_t TP0:1;
187	uint32_t:4;
188	uint32_t BW2:1;
189	uint32_t SP2:1;
190	uint32_t WP2:1;
191	uint32_t TP2:1;
192	uint32_t BW3:1;
193	uint32_t SP3:1;
194	uint32_t WP3:1;
195	uint32_t TP3:1;
196	uint32_t BW4:1;
197	uint32_t SP4:1;
198	uint32_t WP4:1;
199	uint32_t TP4:1;
200	uint32_t:12;
201	} B;
202	} OPACR2;
203
204	};
205
206	/****************************************************************************/
207	/* MODULE : PBRIDGE_B Peripheral Bridge */
208	/****************************************************************************/
209	struct PBRIDGE_B_tag {
210	union {
211	uint32_t R;
212	struct {
213	uint32_t MBW0:1;
214	uint32_t MTR0:1;
215	uint32_t MTW0:1;
216	uint32_t MPL0:1;
217	uint32_t MBW1:1;
218	uint32_t MTR1:1;
219	uint32_t MTW1:1;
220	uint32_t MPL1:1;
221	uint32_t MBW2:1;
222	uint32_t MTR2:1;
223	uint32_t MTW2:1;
224	uint32_t MPL2:1;
225	uint32_t MBW3:1;
226	uint32_t MTR3:1;
227	uint32_t MTW3:1;
228	uint32_t MPL3:1;
229
230	uint32_t MBW4:1; /* FEC */
231	uint32_t MTR4:1;
232	uint32_t MTW4:1;
233	uint32_t MPL4:1;
234
235	uint32_t:4;
236
237	uint32_t MBW6:1; /* FLEXRAY */
238	uint32_t MTR6:1;
239	uint32_t MTW6:1;
240	uint32_t MPL6:1;
241
242	uint32_t:4;
243	} B;
244	} MPCR; /* Master Privilege Control Register */
245
246	uint32_t pbridge_b_reserved2[7];
247
248	union {
249	uint32_t R;
250	struct {
251	uint32_t BW0:1;
252	uint32_t SP0:1;
253	uint32_t WP0:1;
254	uint32_t TP0:1;
255	uint32_t BW1:1;
256	uint32_t SP1:1;
257	uint32_t WP1:1;
258	uint32_t TP1:1;
259	uint32_t:24;
260	} B;
261	} PACR0;
262
263	uint32_t pbridge_b_reserved3;
264
265	union {
266	uint32_t R;
267	struct {
268	uint32_t BW0:1;
269	uint32_t SP0:1;
270	uint32_t WP0:1;
271	uint32_t TP0:1;
272	uint32_t BW1:1;
273	uint32_t SP1:1;
274	uint32_t WP1:1;
275	uint32_t TP1:1;
276	uint32_t BW2:1;
277	uint32_t SP2:1;
278	uint32_t WP2:1;
279	uint32_t TP2:1;
280
281	uint32_t BW3:1; /* FEC */
282	uint32_t SP3:1;
283	uint32_t WP3:1;
284	uint32_t TP3:1;
285
286	uint32_t:16;
287
288	} B;
289	} PACR2;
290
291	uint32_t pbridge_b_reserved4[5];
292
293	union {
294	uint32_t R;
295	struct {
296	uint32_t BW0:1;
297	uint32_t SP0:1;
298	uint32_t WP0:1;
299	uint32_t TP0:1;
300	uint32_t:12;
301
302	uint32_t:4;
303
304	uint32_t BW5:1; /* DSPI_B */
305	uint32_t SP5:1;
306	uint32_t WP5:1;
307	uint32_t TP5:1;
308
309	uint32_t BW6:1;
310	uint32_t SP6:1;
311	uint32_t WP6:1;
312	uint32_t TP6:1;
313	uint32_t BW7:1;
314	uint32_t SP7:1;
315	uint32_t WP7:1;
316	uint32_t TP7:1;
317	} B;
318	} OPACR0;
319
320	union {
321	uint32_t R;
322	struct {
323	uint32_t:16;
324	uint32_t BW4:1;
325	uint32_t SP4:1;
326	uint32_t WP4:1;
327	uint32_t TP4:1;
328
329	uint32_t BW5:1; /* ESCI_B */
330	uint32_t SP5:1;
331	uint32_t WP5:1;
332	uint32_t TP5:1;
333
334	uint32_t:8;
335	} B;
336	} OPACR1;
337
338	union {
339	uint32_t R;
340	struct {
341	uint32_t BW0:1;
342	uint32_t SP0:1;
343	uint32_t WP0:1;
344	uint32_t TP0:1;
345
346	uint32_t BW1:1; /* CAN_B */
347	uint32_t SP1:1;
348	uint32_t WP1:1;
349	uint32_t TP1:1;
350
351	uint32_t BW2:1;
352	uint32_t SP2:1;
353	uint32_t WP2:1;
354	uint32_t TP2:1;
355
356	uint32_t BW3:1; /* CAN_D */
357	uint32_t SP3:1;
358	uint32_t WP3:1;
359	uint32_t TP3:1;
360
361	uint32_t BW4:1; /* CAN_E */
362	uint32_t SP4:1;
363	uint32_t WP4:1;
364	uint32_t TP4:1;
365
366	uint32_t:12;
367	} B;
368	} OPACR2;
369
370	union {
371	uint32_t R;
372	struct {
373
374	uint32_t BW0:1; /* FLEXRAY */
375	uint32_t SP0:1;
376	uint32_t WP0:1;
377	uint32_t TP0:1;
378
379	uint32_t:24;
380	uint32_t BW7:1;
381	uint32_t SP7:1;
382	uint32_t WP7:1;
383	uint32_t TP7:1;
384	} B;
385	} OPACR3;
386
387	};
388	/****************************************************************************/
389	/* MODULE : FMPLL */
390	/****************************************************************************/
391	struct FMPLL_tag {
392	union FMPLL_SYNCR_tag {
393	uint32_t R;
394	struct {
395	uint32_t:1;
396	uint32_t PREDIV:3;
397	uint32_t MFD:5;
398	uint32_t:1;
399	uint32_t RFD:3;
400	uint32_t LOCEN:1;
401	uint32_t LOLRE:1;
402	uint32_t LOCRE:1;
403	uint32_t DISCLK:1;
404	uint32_t LOLIRQ:1;
405	uint32_t LOCIRQ:1;
406	uint32_t RATE:1;
407	uint32_t DEPTH:2;
408	uint32_t EXP:10;
409	} B;
410	} SYNCR;
411
412	union FMPLL_SYNSR_tag {
413	uint32_t R;
414	struct {
415	uint32_t:22;
416	uint32_t LOLF:1;
417	uint32_t LOC:1;
418	uint32_t MODE:1;
419	uint32_t PLLSEL:1;
420	uint32_t PLLREF:1;
421	uint32_t LOCKS:1;
422	uint32_t LOCK:1;
423	uint32_t LOCF:1;
424	uint32_t CALDONE:1;
425	uint32_t CALPASS:1;
426	} B;
427	} SYNSR;
428
429	};
430	/****************************************************************************/
431	/* MODULE : External Bus Interface (EBI) */
432	/****************************************************************************/
433	struct EBI_CS_tag {
434	union { /* Base Register Bank */
435	uint32_t R;
436	struct {
437	uint32_t BA:17;
438	uint32_t:3;
439	uint32_t PS:1;
440	uint32_t:4;
441	uint32_t BL:1;
442	uint32_t WEBS:1;
443	uint32_t TBDIP:1;
444	uint32_t:2;
445	uint32_t BI:1;
446	uint32_t V:1;
447	} B;
448	} BR;
449
450	union { /* Option Register Bank */
451	uint32_t R;
452	struct {
453	uint32_t AM:17;
454	uint32_t:7;
455	uint32_t SCY:4;
456	uint32_t:1;
457	uint32_t BSCY:2;
458	uint32_t:1;
459	} B;
460	} OR;
461	};
462
463	struct EBI_CAL_CS_tag {
464	union { /* Calibration Base Register Bank */
465	uint32_t R;
466	struct {
467	uint32_t BA:17;
468	uint32_t:3;
469	uint32_t PS:1;
470	uint32_t:4;
471	uint32_t BL:1;
472	uint32_t WEBS:1;
473	uint32_t TBDIP:1;
474	uint32_t:2;
475	uint32_t BI:1;
476	uint32_t V:1;
477	} B;
478	} BR;
479
480	union { /* Calibration Option Register Bank */
481	uint32_t R;
482	struct {
483	uint32_t AM:17;
484	uint32_t:7;
485	uint32_t SCY:4;
486	uint32_t:1;
487	uint32_t BSCY:2;
488	uint32_t:1;
489	} B;
490	} OR;
491	};
492
493	struct EBI_tag {
494	union EBI_MCR_tag { /* Module Configuration Register */
495	uint32_t R;
496	struct {
497	uint32_t:5;
498	uint32_t SIZEEN:1;
499	uint32_t SIZE:2;
500	uint32_t:8;
501	uint32_t ACGE:1;
502	uint32_t EXTM:1;
503	uint32_t EARB:1;
504	uint32_t EARP:2;
505	uint32_t:4;
506	uint32_t MDIS:1;
507	uint32_t:5;
508	uint32_t DBM:1;
509	} B;
510	} MCR;
511
512	uint32_t EBI_reserved1;
513
514	union { /* Transfer Error Status Register */
515	uint32_t R;
516	struct {
517	uint32_t:30;
518	uint32_t TEAF:1;
519	uint32_t BMTF:1;
520	} B;
521	} TESR;
522
523	union { /* Bus Monitor Control Register */
524	uint32_t R;
525	struct {
526	uint32_t:16;
527	uint32_t BMT:8;
528	uint32_t BME:1;
529	uint32_t:7;
530	} B;
531	} BMCR;
532
533	struct EBI_CS_tag CS[4];
534
535	/* Calibration registers */
536	uint32_t EBI_reserved2[4];
537	struct EBI_CAL_CS_tag CAL_CS[4];
538
539	};
540	/****************************************************************************/
541	/* MODULE : FLASH */
542	/****************************************************************************/
543	struct FLASH_tag {
544	union { /* Module Configuration Register */
545	uint32_t R;
546	struct {
547	uint32_t:4;
548	uint32_t SIZE:4;
549	uint32_t:1;
550	uint32_t LAS:3;
551	uint32_t:3;
552	uint32_t MAS:1;
553	uint32_t EER:1;
554	uint32_t RWE:1;
555	uint32_t BBEPE:1;
556	uint32_t EPE:1;
557	uint32_t PEAS:1;
558	uint32_t DONE:1;
559	uint32_t PEG:1;
560
561	uint32_t:2;
562
563	uint32_t STOP:1;
564	uint32_t:1;
565	uint32_t PGM:1;
566	uint32_t PSUS:1;
567	uint32_t ERS:1;
568	uint32_t ESUS:1;
569	uint32_t EHV:1;
570	} B;
571	} MCR;
572
573	union LMLR_tag { /* LML Register */
574	uint32_t R;
575	struct {
576	uint32_t LME:1;
577	uint32_t:10;
578	uint32_t SLOCK:1;
579	uint32_t MLOCK:4;
580	uint32_t LLOCK:16;
581	} B;
582	} LMLR;
583
584	union HLR_tag { /* HL Register */
585	uint32_t R;
586	struct {
587	uint32_t HBE:1;
588	uint32_t:3;
589	uint32_t HBLOCK:28;
590	} B;
591	} HLR;
592
593	union SLMLR_tag { /* SLML Register */
594	uint32_t R;
595	struct {
596	uint32_t SLE:1;
597	uint32_t:10;
598	uint32_t SSLOCK:1;
599	uint32_t SMLOCK:4;
600	uint32_t SLLOCK:16;
601	} B;
602	} SLMLR;
603
604	union { /* LMS Register */
605	uint32_t R;
606	struct {
607	uint32_t:12;
608	uint32_t MSEL:4;
609	uint32_t LSEL:16;
610	} B;
611	} LMSR;
612
613	union {
614	uint32_t R;
615	struct {
616	uint32_t:4;
617	uint32_t HBSEL:28;
618	} B;
619	} HSR;
620
621	union {
622	uint32_t R;
623	struct {
624	uint32_t:10;
625	uint32_t ADDR:19;
626	uint32_t:3;
627	} B;
628	} AR;
629
630	union {
631	uint32_t R;
632	struct {
633
634	uint32_t:9;
635	uint32_t M6PFE:1; /* Flexray */
636	uint32_t:1;
637
638	uint32_t M4PFE:1; /* FEC */
639
640	uint32_t M3PFE:1;
641	uint32_t M2PFE:1;
642	uint32_t M1PFE:1;
643	uint32_t M0PFE:1;
644	uint32_t APC:3;
645	uint32_t WWSC:2;
646	uint32_t RWSC:3;
647
648	uint32_t DPFEN:2;
649	uint32_t IPFEN:2;
650
651	uint32_t PFLIM:3;
652	uint32_t BFEN:1;
653	} B;
654	} BIUCR;
655
656	union {
657	uint32_t R;
658	struct {
659
660	uint32_t:18;
661	uint32_t M6AP:2; /* Flexray */
662	uint32_t:2;
663
664	uint32_t M4AP:2; /* FEC */
665
666	uint32_t M3AP:2;
667	uint32_t M2AP:2;
668	uint32_t M1AP:2;
669	uint32_t M0AP:2;
670	} B;
671	} BIUAPR;
672	};
673	/****************************************************************************/
674	/* MODULE : SIU */
675	/****************************************************************************/
676	struct SIU_tag {
677	int32_t SIU_reserved0;
678
679	union { /* MCU ID Register */
680	uint32_t R;
681	struct {
682	uint32_t PARTNUM:16;
683	uint32_t MASKNUM:16;
684	} B;
685	} MIDR;
686	int32_t SIU_reserved00;
687
688	union { /* Reset Status Register */
689	uint32_t R;
690	struct {
691	uint32_t PORS:1;
692	uint32_t ERS:1;
693	uint32_t LLRS:1;
694	uint32_t LCRS:1;
695	uint32_t WDRS:1;
696	uint32_t CRS:1;
697	uint32_t:8;
698	uint32_t SSRS:1;
699	uint32_t SERF:1;
700	uint32_t WKPCFG:1;
701	uint32_t:12;
702	uint32_t BOOTCFG:2;
703	uint32_t RGF:1;
704	} B;
705	} RSR;
706
707	union { /* System Reset Control Register */
708	uint32_t R;
709	struct {
710	uint32_t SSR:1;
711	uint32_t SER:1;
712	uint32_t:14;
713	uint32_t CRE:1;
714	uint32_t:15;
715	} B;
716	} SRCR;
717
718	union SIU_EISR_tag { /* External Interrupt Status Register */
719	uint32_t R;
720	struct {
721	uint32_t:16;
722	uint32_t EIF15:1;
723	uint32_t EIF14:1;
724	uint32_t EIF13:1;
725	uint32_t EIF12:1;
726	uint32_t EIF11:1;
727	uint32_t EIF10:1;
728	uint32_t EIF9:1;
729	uint32_t EIF8:1;
730	uint32_t EIF7:1;
731	uint32_t EIF6:1;
732	uint32_t EIF5:1;
733	uint32_t EIF4:1;
734	uint32_t EIF3:1;
735	uint32_t EIF2:1;
736	uint32_t EIF1:1;
737	uint32_t EIF0:1;
738	} B;
739	} EISR;
740
741	union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */
742	uint32_t R;
743	struct {
744	uint32_t:16;
745	uint32_t EIRE15:1;
746	uint32_t EIRE14:1;
747	uint32_t EIRE13:1;
748	uint32_t EIRE12:1;
749	uint32_t EIRE11:1;
750	uint32_t EIRE10:1;
751	uint32_t EIRE9:1;
752	uint32_t EIRE8:1;
753	uint32_t EIRE7:1;
754	uint32_t EIRE6:1;
755	uint32_t EIRE5:1;
756	uint32_t EIRE4:1;
757	uint32_t EIRE3:1;
758	uint32_t EIRE2:1;
759	uint32_t EIRE1:1;
760	uint32_t EIRE0:1;
761	} B;
762	} DIRER;
763
764	union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */
765	uint32_t R;
766	struct {
767	uint32_t:28;
768	uint32_t DIRS3:1;
769	uint32_t DIRS2:1;
770	uint32_t DIRS1:1;
771	uint32_t DIRS0:1;
772	} B;
773	} DIRSR;
774
775	union { /* Overrun Status Register */
776	uint32_t R;
777	struct {
778	uint32_t:16;
779	uint32_t OVF15:1;
780	uint32_t OVF14:1;
781	uint32_t OVF13:1;
782	uint32_t OVF12:1;
783	uint32_t OVF11:1;
784	uint32_t OVF10:1;
785	uint32_t OVF9:1;
786	uint32_t OVF8:1;
787	uint32_t OVF7:1;
788	uint32_t OVF6:1;
789	uint32_t OVF5:1;
790	uint32_t OVF4:1;
791	uint32_t OVF3:1;
792	uint32_t OVF2:1;
793	uint32_t OVF1:1;
794	uint32_t OVF0:1;
795	} B;
796	} OSR;
797
798	union SIU_ORER_tag { /* Overrun Request Enable Register */
799	uint32_t R;
800	struct {
801	uint32_t:16;
802	uint32_t ORE15:1;
803	uint32_t ORE14:1;
804	uint32_t ORE13:1;
805	uint32_t ORE12:1;
806	uint32_t ORE11:1;
807	uint32_t ORE10:1;
808	uint32_t ORE9:1;
809	uint32_t ORE8:1;
810	uint32_t ORE7:1;
811	uint32_t ORE6:1;
812	uint32_t ORE5:1;
813	uint32_t ORE4:1;
814	uint32_t ORE3:1;
815	uint32_t ORE2:1;
816	uint32_t ORE1:1;
817	uint32_t ORE0:1;
818	} B;
819	} ORER;
820
821	union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */
822	uint32_t R;
823	struct {
824	uint32_t:16;
825	uint32_t IREE15:1;
826	uint32_t IREE14:1;
827	uint32_t IREE13:1;
828	uint32_t IREE12:1;
829	uint32_t IREE11:1;
830	uint32_t IREE10:1;
831	uint32_t IREE9:1;
832	uint32_t IREE8:1;
833	uint32_t IREE7:1;
834	uint32_t IREE6:1;
835	uint32_t IREE5:1;
836	uint32_t IREE4:1;
837	uint32_t IREE3:1;
838	uint32_t IREE2:1;
839	uint32_t IREE1:1;
840	uint32_t IREE0:1;
841	} B;
842	} IREER;
843
844	union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */
845	uint32_t R;
846	struct {
847	uint32_t:16;
848	uint32_t IFEE15:1;
849	uint32_t IFEE14:1;
850	uint32_t IFEE13:1;
851	uint32_t IFEE12:1;
852	uint32_t IFEE11:1;
853	uint32_t IFEE10:1;
854	uint32_t IFEE9:1;
855	uint32_t IFEE8:1;
856	uint32_t IFEE7:1;
857	uint32_t IFEE6:1;
858	uint32_t IFEE5:1;
859	uint32_t IFEE4:1;
860	uint32_t IFEE3:1;
861	uint32_t IFEE2:1;
862	uint32_t IFEE1:1;
863	uint32_t IFEE0:1;
864	} B;
865	} IFEER;
866
867	union SIU_IDFR_tag { /* External IRQ Digital Filter Register */
868	uint32_t R;
869	struct {
870	uint32_t:28;
871	uint32_t DFL:4;
872	} B;
873	} IDFR;
874
875	int32_t SIU_reserved1[3];
876
877	union SIU_PCR_tag { /* Pad Configuration Registers */
878	uint16_t R;
879	struct {
880	uint16_t:3;
881	uint16_t PA:3;
882	uint16_t OBE:1;
883	uint16_t IBE:1;
884	uint16_t DSC:2;
885	uint16_t ODE:1;
886	uint16_t HYS:1;
887	uint16_t SRC:2;
888	uint16_t WPE:1;
889	uint16_t WPS:1;
890	} B;
891	} PCR[512];
892
893	int16_t SIU_reserved_0[224];
894
895	union { /* GPIO Pin Data Output Registers */
896	uint8_t R;
897	struct {
898	uint8_t:7;
899	uint8_t PDO:1;
900	} B;
901	} GPDO[256];
902
903	int32_t SIU_reserved_3[64];
904
905	union { /* GPIO Pin Data Input Registers */
906	uint8_t R;
907	struct {
908	uint8_t:7;
909	uint8_t PDI:1;
910	} B;
911	} GPDI[256];
912
913	union { /* IMUX Register */
914	uint32_t R;
915	struct {
916	uint32_t TSEL5:2;
917	uint32_t TSEL4:2;
918	uint32_t TSEL3:2;
919	uint32_t TSEL2:2;
920	uint32_t TSEL1:2;
921	uint32_t TSEL0:2;
922	uint32_t:20;
923	} B;
924	} ETISR;
925
926	union { /* IMUX Register */
927	uint32_t R;
928	struct {
929	uint32_t ESEL15:2;
930	uint32_t ESEL14:2;
931	uint32_t ESEL13:2;
932	uint32_t ESEL12:2;
933	uint32_t ESEL11:2;
934	uint32_t ESEL10:2;
935	uint32_t ESEL9:2;
936	uint32_t ESEL8:2;
937	uint32_t ESEL7:2;
938	uint32_t ESEL6:2;
939	uint32_t ESEL5:2;
940	uint32_t ESEL4:2;
941	uint32_t ESEL3:2;
942	uint32_t ESEL2:2;
943	uint32_t ESEL1:2;
944	uint32_t ESEL0:2;
945	} B;
946	} EIISR;
947
948	union { /* IMUX Register */
949	uint32_t R;
950	struct {
951	uint32_t SINSELA:2;
952	uint32_t SSSELA:2;
953	uint32_t SCKSELA:2;
954	uint32_t TRIGSELA:2;
955	uint32_t SINSELB:2;
956	uint32_t SSSELB:2;
957	uint32_t SCKSELB:2;
958	uint32_t TRIGSELB:2;
959	uint32_t SINSELC:2;
960	uint32_t SSSELC:2;
961	uint32_t SCKSELC:2;
962	uint32_t TRIGSELC:2;
963	uint32_t SINSELD:2;
964	uint32_t SSSELD:2;
965	uint32_t SCKSELD:2;
966	uint32_t TRIGSELD:2;
967	} B;
968	} DISR;
969
970	int32_t SIU_reserved2[29];
971
972	union { /* Chip Configuration Register Register */
973	uint32_t R;
974	struct {
975	uint32_t:14;
976	uint32_t MATCH:1;
977	uint32_t DISNEX:1;
978	uint32_t:16;
979	} B;
980	} CCR;
981
982	union { /* External Clock Configuration Register Register */
983	uint32_t R;
984	struct {
985	uint32_t:18;
986	uint32_t ENGDIV:6;
987	uint32_t:4;
988	uint32_t EBTS:1;
989	uint32_t:1;
990	uint32_t EBDF:2;
991	} B;
992	} ECCR;
993
994	union {
995	uint32_t R;
996	} CARH;
997
998	union {
999	uint32_t R;
1000	} CARL;
1001
1002	union {
1003	uint32_t R;
1004	} CBRH;
1005
1006	union {
1007	uint32_t R;
1008	} CBRL;
1009
1010	};
1011	/****************************************************************************/
1012	/* MODULE : EMIOS */
1013	/****************************************************************************/
1014	struct EMIOS_tag {
1015	union EMIOS_MCR_tag {
1016	uint32_t R;
1017	struct {
1018	uint32_t:1;
1019	uint32_t MDIS:1;
1020	uint32_t FRZ:1;
1021	uint32_t GTBE:1;
1022	uint32_t ETB:1;
1023	uint32_t GPREN:1;
1024	uint32_t:6;
1025	uint32_t SRV:4;
1026	uint32_t GPRE:8;
1027	uint32_t:8;
1028	} B;
1029	} MCR; /* Module Configuration Register */
1030
1031	union {
1032	uint32_t R;
1033	struct {
1034	uint32_t:8;
1035	uint32_t F23:1;
1036	uint32_t F22:1;
1037	uint32_t F21:1;
1038	uint32_t F20:1;
1039	uint32_t F19:1;
1040	uint32_t F18:1;
1041	uint32_t F17:1;
1042	uint32_t F16:1;
1043	uint32_t F15:1;
1044	uint32_t F14:1;
1045	uint32_t F13:1;
1046	uint32_t F12:1;
1047	uint32_t F11:1;
1048	uint32_t F10:1;
1049	uint32_t F9:1;
1050	uint32_t F8:1;
1051	uint32_t F7:1;
1052	uint32_t F6:1;
1053	uint32_t F5:1;
1054	uint32_t F4:1;
1055	uint32_t F3:1;
1056	uint32_t F2:1;
1057	uint32_t F1:1;
1058	uint32_t F0:1;
1059	} B;
1060	} GFR; /* Global FLAG Register */
1061
1062	union {
1063	uint32_t R;
1064	struct {
1065	uint32_t:8;
1066	uint32_t OU23:1;
1067	uint32_t OU22:1;
1068	uint32_t OU21:1;
1069	uint32_t OU20:1;
1070	uint32_t OU19:1;
1071	uint32_t OU18:1;
1072	uint32_t OU17:1;
1073	uint32_t OU16:1;
1074	uint32_t OU15:1;
1075	uint32_t OU14:1;
1076	uint32_t OU13:1;
1077	uint32_t OU12:1;
1078	uint32_t OU11:1;
1079	uint32_t OU10:1;
1080	uint32_t OU9:1;
1081	uint32_t OU8:1;
1082	uint32_t OU7:1;
1083	uint32_t OU6:1;
1084	uint32_t OU5:1;
1085	uint32_t OU4:1;
1086	uint32_t OU3:1;
1087	uint32_t OU2:1;
1088	uint32_t OU1:1;
1089	uint32_t OU0:1;
1090	} B;
1091	} OUDR; /* Output Update Disable Register */
1092
1093	uint32_t emios_reserved[5];
1094
1095	struct EMIOS_CH_tag {
1096	union {
1097	uint32_t R; /* Channel A Data Register */
1098	} CADR;
1099
1100	union {
1101	uint32_t R; /* Channel B Data Register */
1102	} CBDR;
1103
1104	union {
1105	uint32_t R; /* Channel Counter Register */
1106	} CCNTR;
1107
1108	union EMIOS_CCR_tag {
1109	uint32_t R;
1110	struct {
1111	uint32_t FREN:1;
1112	uint32_t ODIS:1;
1113	uint32_t ODISSL:2;
1114	uint32_t UCPRE:2;
1115	uint32_t UCPREN:1;
1116	uint32_t DMA:1;
1117	uint32_t:1;
1118	uint32_t IF:4;
1119	uint32_t FCK:1;
1120	uint32_t FEN:1;
1121	uint32_t:3;
1122	uint32_t FORCMA:1;
1123	uint32_t FORCMB:1;
1124	uint32_t:1;
1125	uint32_t BSL:2;
1126	uint32_t EDSEL:1;
1127	uint32_t EDPOL:1;
1128	uint32_t MODE:7;
1129	} B;
1130	} CCR; /* Channel Control Register */
1131
1132	union EMIOS_CSR_tag {
1133	uint32_t R;
1134	struct {
1135	uint32_t OVR:1;
1136	uint32_t:15;
1137	uint32_t OVFL:1;
1138	uint32_t:12;
1139	uint32_t UCIN:1;
1140	uint32_t UCOUT:1;
1141	uint32_t FLAG:1;
1142	} B;
1143	} CSR; /* Channel Status Register */
1144
1145	union {
1146	uint32_t R; /* Alternate Channel A Data Register */
1147	} ALTCADR;
1148
1149	uint32_t emios_channel_reserved[2];
1150
1151	} CH[24];
1152
1153	};
1154	/****************************************************************************/
1155	/* MODULE :ETPU */
1156	/****************************************************************************/
1157
1158	/*************************Configuration Registers************************/
1159
1160	struct ETPU_tag {
1161	union { /* MODULE CONFIGURATION REGISTER */
1162	uint32_t R;
1163	struct {
1164	uint32_t GEC:1; /* Global Exception Clear */
1165	uint32_t:3;
1166	uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
1167
1168	uint32_t:1; /* For single ETPU implementations */
1169
1170	uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
1171
1172	uint32_t:1; /* For single ETPU implementations */
1173
1174	uint32_t:3;
1175	uint32_t SCMSIZE:5; /* Shared Code Memory size */
1176	uint32_t:5;
1177	uint32_t SCMMISF:1; /* SCM MISC Flag */
1178	uint32_t SCMMISEN:1; /* SCM MISC Enable */
1179	uint32_t:2;
1180	uint32_t VIS:1; /* SCM Visability */
1181	uint32_t:5;
1182	uint32_t GTBE:1; /* Global Time Base Enable */
1183	} B;
1184	} MCR;
1185
1186	union { /* COHERENT DUAL-PARAMETER CONTROL */
1187	uint32_t R;
1188	struct {
1189	uint32_t STS:1; /* Start Status bit */
1190	uint32_t CTBASE:5; /* Channel Transfer Base */
1191	uint32_t PBASE:10; /* Parameter Buffer Base Address */
1192	uint32_t PWIDTH:1; /* Parameter Width */
1193	uint32_t PARAM0:7; /* Channel Parameter 0 */
1194	uint32_t WR:1;
1195	uint32_t PARAM1:7; /* Channel Parameter 1 */
1196	} B;
1197	} CDCR;
1198
1199	uint32_t etpu_reserved1;
1200
1201	union { /* MISC Compare Register */
1202	uint32_t R;
1203	} MISCCMPR;
1204
1205	union { /* SCM off-range Date Register */
1206	uint32_t R;
1207	} SCMOFFDATAR;
1208
1209	union { /* ETPU_A Configuration Register */
1210	uint32_t R;
1211	struct {
1212	uint32_t FEND:1; /* Force END */
1213	uint32_t MDIS:1; /* Low power Stop */
1214	uint32_t:1;
1215	uint32_t STF:1; /* Stop Flag */
1216	uint32_t:4;
1217	uint32_t HLTF:1; /* Halt Mode Flag */
1218	uint32_t:4;
1219	uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
1220	uint32_t CDFC:2;
1221	uint32_t:9;
1222	uint32_t ETB:5; /* Entry Table Base */
1223	} B;
1224	} ECR_A;
1225	uint32_t etpu_reserved3; /* For single ETPU implementations */
1226
1227	uint32_t etpu_reserved4;
1228
1229	union { /* ETPU_A Timebase Configuration Register */
1230	uint32_t R;
1231	struct {
1232	uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
1233	uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
1234	uint32_t:1;
1235	uint32_t AM:1; /* Angle Mode */
1236	uint32_t:3;
1237	uint32_t TCR2P:6; /* TCR2 Prescaler Control */
1238	uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
1239	uint32_t:6;
1240	uint32_t TCR1P:8; /* TCR1 Prescaler Control */
1241	} B;
1242	} TBCR_A;
1243
1244	union { /* ETPU_A TCR1 Visibility Register */
1245	uint32_t R;
1246	} TB1R_A;
1247
1248	union { /* ETPU_A TCR2 Visibility Register */
1249	uint32_t R;
1250	} TB2R_A;
1251
1252	union { /* ETPU_A STAC Configuration Register */
1253	uint32_t R;
1254	struct {
1255	uint32_t REN1:1; /* Resource Enable TCR1 */
1256	uint32_t RSC1:1; /* Resource Control TCR1 */
1257	uint32_t:2;
1258	uint32_t SERVER_ID1:4;
1259	uint32_t:4;
1260	uint32_t SRV1:4; /* Resource Server Slot */
1261	uint32_t REN2:1; /* Resource Enable TCR2 */
1262	uint32_t RSC2:1; /* Resource Control TCR2 */
1263	uint32_t:2;
1264	uint32_t SERVER_ID2:4;
1265	uint32_t:4;
1266	uint32_t SRV2:4; /* Resource Server Slot */
1267	} B;
1268	} REDCR_A;
1269
1270	uint32_t etpu_reserved5[4];
1271	uint32_t etpu_reserved6[4]; /* For single ETPU implementations */
1272
1273	uint32_t etpu_reserved7[108];
1274
1275	/***************************Status and Control Registers************************/
1276
1277	union { /* ETPU_A Channel Interrut Status */
1278	uint32_t R;
1279	struct {
1280	uint32_t CIS31:1; /* Channel 31 Interrut Status */
1281	uint32_t CIS30:1; /* Channel 30 Interrut Status */
1282	uint32_t CIS29:1; /* Channel 29 Interrut Status */
1283	uint32_t CIS28:1; /* Channel 28 Interrut Status */
1284	uint32_t CIS27:1; /* Channel 27 Interrut Status */
1285	uint32_t CIS26:1; /* Channel 26 Interrut Status */
1286	uint32_t CIS25:1; /* Channel 25 Interrut Status */
1287	uint32_t CIS24:1; /* Channel 24 Interrut Status */
1288	uint32_t CIS23:1; /* Channel 23 Interrut Status */
1289	uint32_t CIS22:1; /* Channel 22 Interrut Status */
1290	uint32_t CIS21:1; /* Channel 21 Interrut Status */
1291	uint32_t CIS20:1; /* Channel 20 Interrut Status */
1292	uint32_t CIS19:1; /* Channel 19 Interrut Status */
1293	uint32_t CIS18:1; /* Channel 18 Interrut Status */
1294	uint32_t CIS17:1; /* Channel 17 Interrut Status */
1295	uint32_t CIS16:1; /* Channel 16 Interrut Status */
1296	uint32_t CIS15:1; /* Channel 15 Interrut Status */
1297	uint32_t CIS14:1; /* Channel 14 Interrut Status */
1298	uint32_t CIS13:1; /* Channel 13 Interrut Status */
1299	uint32_t CIS12:1; /* Channel 12 Interrut Status */
1300	uint32_t CIS11:1; /* Channel 11 Interrut Status */
1301	uint32_t CIS10:1; /* Channel 10 Interrut Status */
1302	uint32_t CIS9:1; /* Channel 9 Interrut Status */
1303	uint32_t CIS8:1; /* Channel 8 Interrut Status */
1304	uint32_t CIS7:1; /* Channel 7 Interrut Status */
1305	uint32_t CIS6:1; /* Channel 6 Interrut Status */
1306	uint32_t CIS5:1; /* Channel 5 Interrut Status */
1307	uint32_t CIS4:1; /* Channel 4 Interrut Status */
1308	uint32_t CIS3:1; /* Channel 3 Interrut Status */
1309	uint32_t CIS2:1; /* Channel 2 Interrut Status */
1310	uint32_t CIS1:1; /* Channel 1 Interrut Status */
1311	uint32_t CIS0:1; /* Channel 0 Interrut Status */
1312	} B;
1313	} CISR_A;
1314	uint32_t etpu_reserved8; /* For single ETPU implementations */
1315
1316	uint32_t etpu_reserved9[2];
1317
1318	union { /* ETPU_A Data Transfer Request Status */
1319	uint32_t R;
1320	struct {
1321	uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
1322	uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
1323	uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
1324	uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
1325	uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
1326	uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
1327	uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
1328	uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
1329	uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
1330	uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
1331	uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
1332	uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
1333	uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
1334	uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
1335	uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
1336	uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
1337	uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
1338	uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
1339	uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
1340	uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
1341	uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
1342	uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
1343	uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
1344	uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
1345	uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
1346	uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
1347	uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
1348	uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
1349	uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
1350	uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
1351	uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
1352	uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
1353	} B;
1354	} CDTRSR_A;
1355	uint32_t etpu_reserved10; /* For single ETPU implementations */
1356
1357	uint32_t etpu_reserved11[2];
1358
1359	union { /* ETPU_A Interruput Overflow Status */
1360	uint32_t R;
1361	struct {
1362	uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
1363	uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
1364	uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
1365	uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
1366	uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
1367	uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
1368	uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
1369	uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
1370	uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
1371	uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
1372	uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
1373	uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
1374	uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
1375	uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
1376	uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
1377	uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
1378	uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
1379	uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
1380	uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
1381	uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
1382	uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
1383	uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
1384	uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
1385	uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
1386	uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
1387	uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
1388	uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
1389	uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
1390	uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
1391	uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
1392	uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
1393	uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
1394	} B;
1395	} CIOSR_A;
1396	uint32_t etpu_reserved12; /* For single ETPU implementations */
1397
1398	uint32_t etpu_reserved13[2];
1399
1400	union { /* ETPU_A Data Transfer Overflow Status */
1401	uint32_t R;
1402	struct {
1403	uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
1404	uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
1405	uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
1406	uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
1407	uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
1408	uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
1409	uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
1410	uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
1411	uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
1412	uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
1413	uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
1414	uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
1415	uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
1416	uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
1417	uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
1418	uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
1419	uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
1420	uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
1421	uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
1422	uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
1423	uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
1424	uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
1425	uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
1426	uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
1427	uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
1428	uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
1429	uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
1430	uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
1431	uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
1432	uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
1433	uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
1434	uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
1435	} B;
1436	} CDTROSR_A;
1437	uint32_t etpu_reserved14; /* For single ETPU implementations */
1438
1439	uint32_t etpu_reserved15[2];
1440
1441	union { /* ETPU_A Channel Interruput Enable */
1442	uint32_t R;
1443	struct {
1444	uint32_t CIE31:1; /* Channel 31 Interruput Enable */
1445	uint32_t CIE30:1; /* Channel 30 Interruput Enable */
1446	uint32_t CIE29:1; /* Channel 29 Interruput Enable */
1447	uint32_t CIE28:1; /* Channel 28 Interruput Enable */
1448	uint32_t CIE27:1; /* Channel 27 Interruput Enable */
1449	uint32_t CIE26:1; /* Channel 26 Interruput Enable */
1450	uint32_t CIE25:1; /* Channel 25 Interruput Enable */
1451	uint32_t CIE24:1; /* Channel 24 Interruput Enable */
1452	uint32_t CIE23:1; /* Channel 23 Interruput Enable */
1453	uint32_t CIE22:1; /* Channel 22 Interruput Enable */
1454	uint32_t CIE21:1; /* Channel 21 Interruput Enable */
1455	uint32_t CIE20:1; /* Channel 20 Interruput Enable */
1456	uint32_t CIE19:1; /* Channel 19 Interruput Enable */
1457	uint32_t CIE18:1; /* Channel 18 Interruput Enable */
1458	uint32_t CIE17:1; /* Channel 17 Interruput Enable */
1459	uint32_t CIE16:1; /* Channel 16 Interruput Enable */
1460	uint32_t CIE15:1; /* Channel 15 Interruput Enable */
1461	uint32_t CIE14:1; /* Channel 14 Interruput Enable */
1462	uint32_t CIE13:1; /* Channel 13 Interruput Enable */
1463	uint32_t CIE12:1; /* Channel 12 Interruput Enable */
1464	uint32_t CIE11:1; /* Channel 11 Interruput Enable */
1465	uint32_t CIE10:1; /* Channel 10 Interruput Enable */
1466	uint32_t CIE9:1; /* Channel 9 Interruput Enable */
1467	uint32_t CIE8:1; /* Channel 8 Interruput Enable */
1468	uint32_t CIE7:1; /* Channel 7 Interruput Enable */
1469	uint32_t CIE6:1; /* Channel 6 Interruput Enable */
1470	uint32_t CIE5:1; /* Channel 5 Interruput Enable */
1471	uint32_t CIE4:1; /* Channel 4 Interruput Enable */
1472	uint32_t CIE3:1; /* Channel 3 Interruput Enable */
1473	uint32_t CIE2:1; /* Channel 2 Interruput Enable */
1474	uint32_t CIE1:1; /* Channel 1 Interruput Enable */
1475	uint32_t CIE0:1; /* Channel 0 Interruput Enable */
1476	} B;
1477	} CIER_A;
1478	uint32_t etpu_reserved16; /* For single ETPU implementations */
1479
1480	uint32_t etpu_reserved17[2];
1481
1482	union { /* ETPU_A Channel Data Transfer Request Enable */
1483	uint32_t R;
1484	struct {
1485	uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
1486	uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
1487	uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
1488	uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
1489	uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
1490	uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
1491	uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
1492	uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
1493	uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
1494	uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
1495	uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
1496	uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
1497	uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
1498	uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
1499	uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
1500	uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
1501	uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
1502	uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
1503	uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
1504	uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
1505	uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
1506	uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
1507	uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
1508	uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
1509	uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
1510	uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
1511	uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
1512	uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
1513	uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
1514	uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
1515	uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
1516	uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
1517	} B;
1518	} CDTRER_A;
1519	uint32_t etpu_reserved19; /* For single ETPU implementations */
1520
1521	uint32_t etpu_reserved20[10];
1522	union { /* ETPU_A Channel Pending Service Status */
1523	uint32_t R;
1524	struct {
1525	uint32_t SR31:1; /* Channel 31 Pending Service Status */
1526	uint32_t SR30:1; /* Channel 30 Pending Service Status */
1527	uint32_t SR29:1; /* Channel 29 Pending Service Status */
1528	uint32_t SR28:1; /* Channel 28 Pending Service Status */
1529	uint32_t SR27:1; /* Channel 27 Pending Service Status */
1530	uint32_t SR26:1; /* Channel 26 Pending Service Status */
1531	uint32_t SR25:1; /* Channel 25 Pending Service Status */
1532	uint32_t SR24:1; /* Channel 24 Pending Service Status */
1533	uint32_t SR23:1; /* Channel 23 Pending Service Status */
1534	uint32_t SR22:1; /* Channel 22 Pending Service Status */
1535	uint32_t SR21:1; /* Channel 21 Pending Service Status */
1536	uint32_t SR20:1; /* Channel 20 Pending Service Status */
1537	uint32_t SR19:1; /* Channel 19 Pending Service Status */
1538	uint32_t SR18:1; /* Channel 18 Pending Service Status */
1539	uint32_t SR17:1; /* Channel 17 Pending Service Status */
1540	uint32_t SR16:1; /* Channel 16 Pending Service Status */
1541	uint32_t SR15:1; /* Channel 15 Pending Service Status */
1542	uint32_t SR14:1; /* Channel 14 Pending Service Status */
1543	uint32_t SR13:1; /* Channel 13 Pending Service Status */
1544	uint32_t SR12:1; /* Channel 12 Pending Service Status */
1545	uint32_t SR11:1; /* Channel 11 Pending Service Status */
1546	uint32_t SR10:1; /* Channel 10 Pending Service Status */
1547	uint32_t SR9:1; /* Channel 9 Pending Service Status */
1548	uint32_t SR8:1; /* Channel 8 Pending Service Status */
1549	uint32_t SR7:1; /* Channel 7 Pending Service Status */
1550	uint32_t SR6:1; /* Channel 6 Pending Service Status */
1551	uint32_t SR5:1; /* Channel 5 Pending Service Status */
1552	uint32_t SR4:1; /* Channel 4 Pending Service Status */
1553	uint32_t SR3:1; /* Channel 3 Pending Service Status */
1554	uint32_t SR2:1; /* Channel 2 Pending Service Status */
1555	uint32_t SR1:1; /* Channel 1 Pending Service Status */
1556	uint32_t SR0:1; /* Channel 0 Pending Service Status */
1557	} B;
1558	} CPSSR_A;
1559	uint32_t etpu_reserved22; /* For single ETPU implementations */
1560
1561	uint32_t etpu_reserved20a[2];
1562
1563	union { /* ETPU_A Channel Service Status */
1564	uint32_t R;
1565	struct {
1566	uint32_t SS31:1; /* Channel 31 Service Status */
1567	uint32_t SS30:1; /* Channel 30 Service Status */
1568	uint32_t SS29:1; /* Channel 29 Service Status */
1569	uint32_t SS28:1; /* Channel 28 Service Status */
1570	uint32_t SS27:1; /* Channel 27 Service Status */
1571	uint32_t SS26:1; /* Channel 26 Service Status */
1572	uint32_t SS25:1; /* Channel 25 Service Status */
1573	uint32_t SS24:1; /* Channel 24 Service Status */
1574	uint32_t SS23:1; /* Channel 23 Service Status */
1575	uint32_t SS22:1; /* Channel 22 Service Status */
1576	uint32_t SS21:1; /* Channel 21 Service Status */
1577	uint32_t SS20:1; /* Channel 20 Service Status */
1578	uint32_t SS19:1; /* Channel 19 Service Status */
1579	uint32_t SS18:1; /* Channel 18 Service Status */
1580	uint32_t SS17:1; /* Channel 17 Service Status */
1581	uint32_t SS16:1; /* Channel 16 Service Status */
1582	uint32_t SS15:1; /* Channel 15 Service Status */
1583	uint32_t SS14:1; /* Channel 14 Service Status */
1584	uint32_t SS13:1; /* Channel 13 Service Status */
1585	uint32_t SS12:1; /* Channel 12 Service Status */
1586	uint32_t SS11:1; /* Channel 11 Service Status */
1587	uint32_t SS10:1; /* Channel 10 Service Status */
1588	uint32_t SS9:1; /* Channel 9 Service Status */
1589	uint32_t SS8:1; /* Channel 8 Service Status */
1590	uint32_t SS7:1; /* Channel 7 Service Status */
1591	uint32_t SS6:1; /* Channel 6 Service Status */
1592	uint32_t SS5:1; /* Channel 5 Service Status */
1593	uint32_t SS4:1; /* Channel 4 Service Status */
1594	uint32_t SS3:1; /* Channel 3 Service Status */
1595	uint32_t SS2:1; /* Channel 2 Service Status */
1596	uint32_t SS1:1; /* Channel 1 Service Status */
1597	uint32_t SS0:1; /* Channel 0 Service Status */
1598	} B;
1599	} CSSR_A;
1600	uint32_t etpu_reserved22a; /* For single ETPU implementations */
1601
1602	uint32_t etpu_reserved23[90];
1603
1604	/***************************Channels******************************/
1605
1606	struct {
1607	union {
1608	uint32_t R; /* Channel Configuration Register */
1609	struct {
1610	uint32_t CIE:1; /* Channel Interruput Enable */
1611	uint32_t DTRE:1; /* Data Transfer Request Enable */
1612	uint32_t CPR:2; /* Channel Priority */
1613	uint32_t:3;
1614	uint32_t ETCS:1; /* Entry Table Condition Select */
1615	uint32_t:3;
1616	uint32_t CFS:5; /* Channel Function Select */
1617	uint32_t ODIS:1; /* Output disable */
1618	uint32_t OPOL:1; /* output polarity */
1619	uint32_t:3;
1620	uint32_t CPBA:11; /* Channel Parameter Base Address */
1621	} B;
1622	} CR;
1623	union {
1624	uint32_t R; /* Channel Status Control Register */
1625	struct {
1626	uint32_t CIS:1; /* Channel Interruput Status */
1627	uint32_t CIOS:1; /* Channel Interruput Overflow Status */
1628	uint32_t:6;
1629	uint32_t DTRS:1; /* Data Transfer Status */
1630	uint32_t DTROS:1; /* Data Transfer Overflow Status */
1631	uint32_t:6;
1632	uint32_t IPS:1; /* Input Pin State */
1633	uint32_t OPS:1; /* Output Pin State */
1634	uint32_t OBE:1; /* Output Buffer Enable */
1635	uint32_t:11;
1636	uint32_t FM1:1; /* Function mode */
1637	uint32_t FM0:1; /* Function mode */
1638	} B;
1639	} SCR;
1640	union {
1641	uint32_t R; /* Channel Host Service Request Register */
1642	struct {
1643	uint32_t:29; /* Host Service Request */
1644	uint32_t HSR:3;
1645	} B;
1646	} HSRR;
1647	uint32_t etpu_reserved23;
1648	} CHAN[127];
1649
1650	};
1651	/****************************************************************************/
1652	/* MODULE : XBAR CrossBar */
1653	/****************************************************************************/
1654	struct XBAR_tag {
1655	union {
1656	uint32_t R;
1657	struct {
1658	uint32_t:4;
1659
1660	uint32_t:1;
1661	uint32_t MSTR6:3; /* FLEXRAY */
1662
1663	uint32_t:4;
1664
1665	uint32_t:4;
1666
1667	uint32_t:1;
1668	uint32_t MSTR3:3; /* FEC */
1669
1670	uint32_t:1;
1671	uint32_t MSTR2:3;
1672	uint32_t:1;
1673	uint32_t MSTR1:3;
1674	uint32_t:1;
1675	uint32_t MSTR0:3;
1676	} B;
1677	} MPR0; /* Master Priority Register for Slave Port 0 */
1678
1679	uint32_t xbar_reserved1[3];
1680
1681	union {
1682	uint32_t R;
1683	struct {
1684	uint32_t RO:1;
1685	uint32_t:21;
1686	uint32_t ARB:2;
1687	uint32_t:2;
1688	uint32_t PCTL:2;
1689	uint32_t:1;
1690	uint32_t PARK:3;
1691	} B;
1692	} SGPCR0; /* General Purpose Control Register for Slave Port 0 */
1693
1694	uint32_t xbar_reserved2[59];
1695
1696	union {
1697	uint32_t R;
1698	struct {
1699	uint32_t:4;
1700
1701	uint32_t:1;
1702	uint32_t MSTR6:3; /* FLEXRAY */
1703
1704	uint32_t:4;
1705
1706	uint32_t:4;
1707
1708	uint32_t:1;
1709	uint32_t MSTR3:3; /* FEC */
1710
1711	uint32_t:1;
1712	uint32_t MSTR2:3;
1713	uint32_t:1;
1714	uint32_t MSTR1:3;
1715	uint32_t:1;
1716	uint32_t MSTR0:3;
1717	} B;
1718	} MPR1; /* Master Priority Register for Slave Port 1 */
1719
1720	uint32_t xbar_reserved3[3];
1721
1722	union {
1723	uint32_t R;
1724	struct {
1725	uint32_t RO:1;
1726	uint32_t:21;
1727	uint32_t ARB:2;
1728	uint32_t:2;
1729	uint32_t PCTL:2;
1730	uint32_t:1;
1731	uint32_t PARK:3;
1732	} B;
1733	} SGPCR1; /* General Purpose Control Register for Slave Port 1 */
1734
1735	uint32_t xbar_reserved4[123];
1736
1737	union {
1738	uint32_t R;
1739	struct {
1740	uint32_t:4;
1741
1742	uint32_t:1;
1743	uint32_t MSTR6:3; /* FLEXRAY */
1744
1745	uint32_t:4;
1746
1747	uint32_t:4;
1748
1749	uint32_t:1;
1750	uint32_t MSTR3:3; /* FEC */
1751
1752	uint32_t:1;
1753	uint32_t MSTR2:3;
1754	uint32_t:1;
1755	uint32_t MSTR1:3;
1756	uint32_t:1;
1757	uint32_t MSTR0:3;
1758	} B;
1759	} MPR3; /* Master Priority Register for Slave Port 3 */
1760
1761	uint32_t xbar_reserved5[3];
1762
1763	union {
1764	uint32_t R;
1765	struct {
1766	uint32_t RO:1;
1767	uint32_t:21;
1768	uint32_t ARB:2;
1769	uint32_t:2;
1770	uint32_t PCTL:2;
1771	uint32_t:1;
1772	uint32_t PARK:3;
1773	} B;
1774	} SGPCR3; /* General Purpose Control Register for Slave Port 3 */
1775	uint32_t xbar_reserved6[187];
1776
1777	union {
1778	uint32_t R;
1779	struct {
1780	uint32_t:4;
1781
1782	uint32_t:1;
1783	uint32_t MSTR6:3; /* FLEXRAY */
1784
1785	uint32_t:4;
1786
1787	uint32_t:4;
1788
1789	uint32_t:1;
1790	uint32_t MSTR3:3; /* FEC */
1791
1792	uint32_t:1;
1793	uint32_t MSTR2:3;
1794	uint32_t:1;
1795	uint32_t MSTR1:3;
1796	uint32_t:1;
1797	uint32_t MSTR0:3;
1798	} B;
1799	} MPR6; /* Master Priority Register for Slave Port 6 */
1800
1801	uint32_t xbar_reserved7[3];
1802
1803	union {
1804	uint32_t R;
1805	struct {
1806	uint32_t RO:1;
1807	uint32_t:21;
1808	uint32_t ARB:2;
1809	uint32_t:2;
1810	uint32_t PCTL:2;
1811	uint32_t:1;
1812	uint32_t PARK:3;
1813	} B;
1814	} SGPCR6; /* General Purpose Control Register for Slave Port 6 */
1815
1816	uint32_t xbar_reserved8[59];
1817
1818	union {
1819	uint32_t R;
1820	struct {
1821	uint32_t:4;
1822
1823	uint32_t:1;
1824	uint32_t MSTR6:3; /* FLEXRAY */
1825
1826	uint32_t:4;
1827
1828	uint32_t:4;
1829
1830	uint32_t:1;
1831	uint32_t MSTR3:3; /* FEC */
1832
1833	uint32_t:1;
1834	uint32_t MSTR2:3;
1835	uint32_t:1;
1836	uint32_t MSTR1:3;
1837	uint32_t:1;
1838	uint32_t MSTR0:3;
1839	} B;
1840	} MPR7; /* Master Priority Register for Slave Port 7 */
1841
1842	uint32_t xbar_reserved9[3];
1843
1844	union {
1845	uint32_t R;
1846	struct {
1847	uint32_t RO:1;
1848	uint32_t:21;
1849	uint32_t ARB:2;
1850	uint32_t:2;
1851	uint32_t PCTL:2;
1852	uint32_t:1;
1853	uint32_t PARK:3;
1854	} B;
1855	} SGPCR7; /* General Purpose Control Register for Slave Port 7 */
1856
1857	};
1858	/****************************************************************************/
1859	/* MODULE : ECSM */
1860	/****************************************************************************/
1861	struct ECSM_tag {
1862
1863	uint32_t ecsm_reserved1[5];
1864
1865	uint16_t ecsm_reserved2;
1866
1867	union {
1868	uint16_t R;
1869	} SWTCR; //Software Watchdog Timer Control
1870
1871	uint8_t ecsm_reserved3[3];
1872
1873	union {
1874	uint8_t R;
1875	} SWTSR; //SWT Service Register
1876
1877	uint8_t ecsm_reserved4[3];
1878
1879	union {
1880	uint8_t R;
1881	} SWTIR; //SWT Interrupt Register
1882
1883	uint32_t ecsm_reserved5a[1];
1884
1885	union {
1886	uint32_t R;
1887	struct {
1888	uint32_t FSBCR0:1;
1889	uint32_t FSBCR1:1;
1890	uint32_t FSBCR2:1;
1891	uint32_t FSBCR3:1;
1892	uint32_t FSBCR4:1;
1893	uint32_t FSBCR5:1;
1894	uint32_t FSBCR6:1;
1895	uint32_t FSBCR7:1;
1896	uint32_t RBEN:1;
1897	uint32_t WBEN:1;
1898	uint32_t ACCERR:1;
1899	uint32_t:21;
1900	} B;
1901	} FSBMCR; /* FEC System Bus Master Control Register */
1902
1903	uint32_t ecsm_reserved5c[6];
1904
1905	uint8_t ecsm_reserved6[3];
1906
1907	union {
1908	uint8_t R;
1909	struct {
1910	uint8_t:6;
1911	uint8_t ERNCR:1;
1912	uint8_t EFNCR:1;
1913	} B;
1914	} ECR; //ECC Configuration Register
1915
1916	uint8_t mcm_reserved8[3];
1917
1918	union {
1919	uint8_t R;
1920	struct {
1921	uint8_t:6;
1922	uint8_t RNCE:1;
1923	uint8_t FNCE:1;
1924	} B;
1925	} ESR; //ECC Status Register
1926
1927	uint16_t ecsm_reserved9;
1928
1929	union {
1930	uint16_t R;
1931	struct {
1932	uint16_t:6;
1933	uint16_t FRCNCI:1;
1934	uint16_t FR1NCI:1;
1935	uint16_t:1;
1936	uint16_t ERRBIT:7;
1937	} B;
1938	} EEGR; //ECC Error Generation Register
1939
1940	uint32_t ecsm_reserved10;
1941
1942	union {
1943	uint32_t R;
1944	struct {
1945	uint32_t FEAR:32;
1946	} B;
1947	} FEAR; //Flash ECC Address Register
1948
1949	uint16_t ecsm_reserved11;
1950
1951	union {
1952	uint8_t R;
1953	struct {
1954	uint8_t:4;
1955	uint8_t FEMR:4;
1956	} B;
1957	} FEMR; //Flash ECC Master Register
1958
1959	union {
1960	uint8_t R;
1961	struct {
1962	uint8_t WRITE:1;
1963	uint8_t SIZE:3;
1964	uint8_t PROT0:1;
1965	uint8_t PROT1:1;
1966	uint8_t PROT2:1;
1967	uint8_t PROT3:1;
1968	} B;
1969	} FEAT; //Flash ECC Attributes Register
1970
1971	union {
1972	uint32_t R;
1973	struct {
1974	uint32_t FEDH:32;
1975	} B;
1976	} FEDRH; //Flash ECC Data High Register
1977
1978	union {
1979	uint32_t R;
1980	struct {
1981	uint32_t FEDL:32;
1982	} B;
1983	} FEDRL; //Flash ECC Data Low Register
1984
1985	union {
1986	uint32_t R;
1987	struct {
1988	uint32_t REAR:32;
1989	} B;
1990	} REAR; //RAM ECC Address
1991
1992	uint8_t ecsm_reserved12[2];
1993
1994	union {
1995	uint8_t R;
1996	struct {
1997	uint8_t:4;
1998	uint8_t REMR:4;
1999	} B;
2000	} REMR; //RAM ECC Master
2001
2002	union {
2003	uint8_t R;
2004	struct {
2005	uint8_t WRITE:1;
2006	uint8_t SIZE:3;
2007	uint8_t PROT0:1;
2008	uint8_t PROT1:1;
2009	uint8_t PROT2:1;
2010	uint8_t PROT3:1;
2011	} B;
2012	} REAT; // RAM ECC Attributes Register
2013
2014	union {
2015	uint32_t R;
2016	struct {
2017	uint32_t REDH:32;
2018	} B;
2019	} REDRH; //RAM ECC Data High Register
2020
2021	union {
2022	uint32_t R;
2023	struct {
2024	uint32_t REDL:32;
2025	} B;
2026	} REDRL; //RAMECC Data Low Register
2027
2028	};
2029	/****************************************************************************/
2030	/* MODULE : INTC */
2031	/****************************************************************************/
2032	struct INTC_tag {
2033	union {
2034	uint32_t R;
2035	struct {
2036	uint32_t:26;
2037	uint32_t VTES:1;
2038	uint32_t:4;
2039	uint32_t HVEN:1;
2040	} B;
2041	} MCR; /* Module Configuration Register */
2042
2043	int32_t INTC_reserved00;
2044
2045	union {
2046	uint32_t R;
2047	struct {
2048	uint32_t:28;
2049	uint32_t PRI:4;
2050	} B;
2051	} CPR; /* Current Priority Register */
2052
2053	uint32_t intc_reserved1;
2054
2055	union {
2056	uint32_t R;
2057	struct {
2058	uint32_t VTBA:21;
2059	uint32_t INTVEC:9;
2060	uint32_t:2;
2061	} B;
2062	} IACKR; /* Interrupt Acknowledge Register */
2063
2064	uint32_t intc_reserved2;
2065
2066	union {
2067	uint32_t R;
2068	struct {
2069	uint32_t:32;
2070	} B;
2071	} EOIR; /* End of Interrupt Register */
2072
2073	uint32_t intc_reserved3;
2074
2075	union {
2076	uint8_t R;
2077	struct {
2078	uint8_t:6;
2079	uint8_t SET:1;
2080	uint8_t CLR:1;
2081	} B;
2082	} SSCIR[8]; /* Software Set/Clear Interruput Register */
2083
2084	uint32_t intc_reserved4[6];
2085
2086	union {
2087	uint8_t R;
2088	struct {
2089	uint8_t:4;
2090	uint8_t PRI:4;
2091	} B;
2092	} PSR[358]; /* Software Set/Clear Interrupt Register */
2093
2094	};
2095	/****************************************************************************/
2096	/* MODULE : EQADC */
2097	/****************************************************************************/
2098	struct EQADC_tag {
2099	union {
2100	uint32_t R;
2101	struct {
2102	uint32_t:27;
2103	uint32_t ESSIE:2;
2104	uint32_t:1;
2105	uint32_t DBG:2;
2106	} B;
2107	} MCR; /* Module Configuration Register */
2108
2109	int32_t EQADC_reserved00;
2110
2111	union {
2112	uint32_t R;
2113	struct {
2114	uint32_t:6;
2115	uint32_t NMF:26;
2116	} B;
2117	} NMSFR; /* Null Message Send Format Register */
2118
2119	union {
2120	uint32_t R;
2121	struct {
2122	uint32_t:28;
2123	uint32_t DFL:4;
2124	} B;
2125	} ETDFR; /* External Trigger Digital Filter Register */
2126
2127	union {
2128	uint32_t R;
2129	struct {
2130	uint32_t CFPUSH:32;
2131	} B;
2132	} CFPR[6]; /* CFIFO Push Registers */
2133
2134	uint32_t eqadc_reserved1;
2135
2136	uint32_t eqadc_reserved2;
2137
2138	union {
2139	uint32_t R;
2140	struct {
2141	uint32_t:16;
2142	uint32_t RFPOP:16;
2143	} B;
2144	} RFPR[6]; /* Result FIFO Pop Registers */
2145
2146	uint32_t eqadc_reserved3;
2147
2148	uint32_t eqadc_reserved4;
2149
2150	union {
2151	uint16_t R;
2152	struct {
2153	uint16_t:5;
2154	uint16_t SSE:1;
2155	uint16_t CFINV:1;
2156	uint16_t:1;
2157	uint16_t MODE:4;
2158	uint16_t:4;
2159	} B;
2160	} CFCR[6]; /* CFIFO Control Registers */
2161
2162	uint32_t eqadc_reserved5;
2163
2164	union {
2165	uint16_t R;
2166	struct {
2167	uint16_t NCIE:1;
2168	uint16_t TORIE:1;
2169	uint16_t PIE:1;
2170	uint16_t EOQIE:1;
2171	uint16_t CFUIE:1;
2172	uint16_t:1;
2173	uint16_t CFFE:1;
2174	uint16_t CFFS:1;
2175	uint16_t:4;
2176	uint16_t RFOIE:1;
2177	uint16_t:1;
2178	uint16_t RFDE:1;
2179	uint16_t RFDS:1;
2180	} B;
2181	} IDCR[6]; /* Interrupt and DMA Control Registers */
2182
2183	uint32_t eqadc_reserved6;
2184
2185	union {
2186	uint32_t R;
2187	struct {
2188	uint32_t NCF:1;
2189	uint32_t TORF:1;
2190	uint32_t PF:1;
2191	uint32_t EOQF:1;
2192	uint32_t CFUF:1;
2193	uint32_t SSS:1;
2194	uint32_t CFFF:1;
2195	uint32_t:5;
2196	uint32_t RFOF:1;
2197	uint32_t:1;
2198	uint32_t RFDF:1;
2199	uint32_t:1;
2200	uint32_t CFCTR:4;
2201	uint32_t TNXTPTR:4;
2202	uint32_t RFCTR:4;
2203	uint32_t POPNXTPTR:4;
2204	} B;
2205	} FISR[6]; /* FIFO and Interrupt Status Registers */
2206
2207	uint32_t eqadc_reserved7;
2208
2209	uint32_t eqadc_reserved8;
2210
2211	union {
2212	uint16_t R;
2213	struct {
2214	uint16_t:5;
2215	uint16_t TCCF:11;
2216	} B;
2217	} CFTCR[6]; /* CFIFO Transfer Counter Registers */
2218
2219	uint32_t eqadc_reserved9;
2220
2221	union {
2222	uint32_t R;
2223	struct {
2224	uint32_t CFS0:2;
2225	uint32_t CFS1:2;
2226	uint32_t CFS2:2;
2227	uint32_t CFS3:2;
2228	uint32_t CFS4:2;
2229	uint32_t CFS5:2;
2230	uint32_t:5;
2231	uint32_t LCFTCB0:4;
2232	uint32_t TC_LCFTCB0:11;
2233	} B;
2234	} CFSSR0; /* CFIFO Status Register 0 */
2235
2236	union {
2237	uint32_t R;
2238	struct {
2239	uint32_t CFS0:2;
2240	uint32_t CFS1:2;
2241	uint32_t CFS2:2;
2242	uint32_t CFS3:2;
2243	uint32_t CFS4:2;
2244	uint32_t CFS5:2;
2245	uint32_t:5;
2246	uint32_t LCFTCB1:4;
2247	uint32_t TC_LCFTCB1:11;
2248	} B;
2249	} CFSSR1; /* CFIFO Status Register 1 */
2250
2251	union {
2252	uint32_t R;
2253	struct {
2254	uint32_t CFS0:2;
2255	uint32_t CFS1:2;
2256	uint32_t CFS2:2;
2257	uint32_t CFS3:2;
2258	uint32_t CFS4:2;
2259	uint32_t CFS5:2;
2260	uint32_t:4;
2261	uint32_t ECBNI:1;
2262	uint32_t LCFTSSI:4;
2263	uint32_t TC_LCFTSSI:11;
2264	} B;
2265	} CFSSR2; /* CFIFO Status Register 2 */
2266
2267	union {
2268	uint32_t R;
2269	struct {
2270	uint32_t CFS0:2;
2271	uint32_t CFS1:2;
2272	uint32_t CFS2:2;
2273	uint32_t CFS3:2;
2274	uint32_t CFS4:2;
2275	uint32_t CFS5:2;
2276	uint32_t:20;
2277	} B;
2278	} CFSR;
2279
2280	uint32_t eqadc_reserved11;
2281
2282	union {
2283	uint32_t R;
2284	struct {
2285	uint32_t:21;
2286	uint32_t MDT:3;
2287	uint32_t:4;
2288	uint32_t BR:4;
2289	} B;
2290	} SSICR; /* SSI Control Register */
2291
2292	union {
2293	uint32_t R;
2294	struct {
2295	uint32_t RDV:1;
2296	uint32_t:5;
2297	uint32_t RDATA:26;
2298	} B;
2299	} SSIRDR; /* SSI Recieve Data Register */
2300
2301	uint32_t eqadc_reserved12[17];
2302
2303	struct {
2304	union {
2305	uint32_t R;
2306	struct {
2307	uint32_t:32;
2308	} B;
2309	} R[4];
2310
2311	uint32_t eqadc_reserved13[12];
2312
2313	} CF[6];
2314
2315	uint32_t eqadc_reserved14[32];
2316
2317	struct {
2318	union {
2319	uint32_t R;
2320	struct {
2321	uint32_t:32;
2322	} B;
2323	} R[4];
2324
2325	uint32_t eqadc_reserved15[12];
2326
2327	} RF[6];
2328
2329	};
2330	/****************************************************************************/
2331	/* MODULE : DSPI */
2332	/****************************************************************************/
2333	struct DSPI_tag {
2334	union DSPI_MCR_tag {
2335	uint32_t R;
2336	struct {
2337	uint32_t MSTR:1;
2338	uint32_t CONT_SCKE:1;
2339	uint32_t DCONF:2;
2340	uint32_t FRZ:1;
2341	uint32_t MTFE:1;
2342	uint32_t PCSSE:1;
2343	uint32_t ROOE:1;
2344	uint32_t:2;
2345	uint32_t PCSIS5:1;
2346	uint32_t PCSIS4:1;
2347	uint32_t PCSIS3:1;
2348	uint32_t PCSIS2:1;
2349	uint32_t PCSIS1:1;
2350	uint32_t PCSIS0:1;
2351	uint32_t DOZE:1;
2352	uint32_t MDIS:1;
2353	uint32_t DIS_TXF:1;
2354	uint32_t DIS_RXF:1;
2355	uint32_t CLR_TXF:1;
2356	uint32_t CLR_RXF:1;
2357	uint32_t SMPL_PT:2;
2358	uint32_t:7;
2359	uint32_t HALT:1;
2360	} B;
2361	} MCR; /* Module Configuration Register */
2362
2363	uint32_t dspi_reserved1;
2364
2365	union {
2366	uint32_t R;
2367	struct {
2368	uint32_t TCNT:16;
2369	uint32_t:16;
2370	} B;
2371	} TCR;
2372
2373	union DSPI_CTAR_tag {
2374	uint32_t R;
2375	struct {
2376	uint32_t DBR:1;
2377	uint32_t FMSZ:4;
2378	uint32_t CPOL:1;
2379	uint32_t CPHA:1;
2380	uint32_t LSBFE:1;
2381	uint32_t PCSSCK:2;
2382	uint32_t PASC:2;
2383	uint32_t PDT:2;
2384	uint32_t PBR:2;
2385	uint32_t CSSCK:4;
2386	uint32_t ASC:4;
2387	uint32_t DT:4;
2388	uint32_t BR:4;
2389	} B;
2390	} CTAR[8]; /* Clock and Transfer Attributes Registers */
2391
2392	union DSPI_SR_tag {
2393	uint32_t R;
2394	struct {
2395	uint32_t TCF:1;
2396	uint32_t TXRXS:1;
2397	uint32_t:1;
2398	uint32_t EOQF:1;
2399	uint32_t TFUF:1;
2400	uint32_t:1;
2401	uint32_t TFFF:1;
2402	uint32_t:5;
2403	uint32_t RFOF:1;
2404	uint32_t:1;
2405	uint32_t RFDF:1;
2406	uint32_t:1;
2407	uint32_t TXCTR:4;
2408	uint32_t TXNXTPTR:4;
2409	uint32_t RXCTR:4;
2410	uint32_t POPNXTPTR:4;
2411	} B;
2412	} SR; /* Status Register */
2413
2414	union DSPI_RSER_tag {
2415	uint32_t R;
2416	struct {
2417	uint32_t TCFRE:1;
2418	uint32_t:2;
2419	uint32_t EOQFRE:1;
2420	uint32_t TFUFRE:1;
2421	uint32_t:1;
2422	uint32_t TFFFRE:1;
2423	uint32_t TFFFDIRS:1;
2424	uint32_t:4;
2425	uint32_t RFOFRE:1;
2426	uint32_t:1;
2427	uint32_t RFDFRE:1;
2428	uint32_t RFDFDIRS:1;
2429	uint32_t:16;
2430	} B;
2431	} RSER; /* DMA/Interrupt Request Select and Enable Register */
2432
2433	union DSPI_PUSHR_tag {
2434	uint32_t R;
2435	struct {
2436	uint32_t CONT:1;
2437	uint32_t CTAS:3;
2438	uint32_t EOQ:1;
2439	uint32_t CTCNT:1;
2440	uint32_t:4;
2441	uint32_t PCS5:1;
2442	uint32_t PCS4:1;
2443	uint32_t PCS3:1;
2444	uint32_t PCS2:1;
2445	uint32_t PCS1:1;
2446	uint32_t PCS0:1;
2447	uint32_t TXDATA:16;
2448	} B;
2449	} PUSHR; /* PUSH TX FIFO Register */
2450
2451	union DSPI_POPR_tag {
2452	uint32_t R;
2453	struct {
2454	uint32_t:16;
2455	uint32_t RXDATA:16;
2456	} B;
2457	} POPR; /* POP RX FIFO Register */
2458
2459	union {
2460	uint32_t R;
2461	struct {
2462	uint32_t TXCMD:16;
2463	uint32_t TXDATA:16;
2464	} B;
2465	} TXFR[4]; /* Transmit FIFO Registers */
2466
2467	uint32_t DSPI_reserved_txf[12];
2468
2469	union {
2470	uint32_t R;
2471	struct {
2472	uint32_t:16;
2473	uint32_t RXDATA:16;
2474	} B;
2475	} RXFR[4]; /* Transmit FIFO Registers */
2476
2477	uint32_t DSPI_reserved_rxf[12];
2478
2479	union {
2480	uint32_t R;
2481	struct {
2482	uint32_t MTOE:1;
2483	uint32_t:1;
2484	uint32_t MTOCNT:6;
2485	uint32_t:4;
2486	uint32_t TXSS:1;
2487	uint32_t TPOL:1;
2488	uint32_t TRRE:1;
2489	uint32_t CID:1;
2490	uint32_t DCONT:1;
2491	uint32_t DSICTAS:3;
2492	uint32_t:6;
2493	uint32_t DPCS5:1;
2494	uint32_t DPCS4:1;
2495	uint32_t DPCS3:1;
2496	uint32_t DPCS2:1;
2497	uint32_t DPCS1:1;
2498	uint32_t DPCS0:1;
2499	} B;
2500	} DSICR; /* DSI Configuration Register */
2501
2502	union {
2503	uint32_t R;
2504	struct {
2505	uint32_t:16;
2506	uint32_t SER_DATA:16;
2507	} B;
2508	} SDR; /* DSI Serialization Data Register */
2509
2510	union {
2511	uint32_t R;
2512	struct {
2513	uint32_t:16;
2514	uint32_t ASER_DATA:16;
2515	} B;
2516	} ASDR; /* DSI Alternate Serialization Data Register */
2517
2518	union {
2519	uint32_t R;
2520	struct {
2521	uint32_t:16;
2522	uint32_t COMP_DATA:16;
2523	} B;
2524	} COMPR; /* DSI Transmit Comparison Register */
2525
2526	union {
2527	uint32_t R;
2528	struct {
2529	uint32_t:16;
2530	uint32_t DESER_DATA:16;
2531	} B;
2532	} DDR; /* DSI deserialization Data Register */
2533
2534	};
2535	/****************************************************************************/
2536	/* MODULE : eSCI */
2537	/****************************************************************************/
2538	struct ESCI_tag {
2539	union ESCI_CR1_tag {
2540	uint32_t R;
2541	struct {
2542	uint32_t:3;
2543	uint32_t SBR:13;
2544	uint32_t LOOPS:1;
2545	uint32_t SCISDOZ:1;
2546	uint32_t RSRC:1;
2547	uint32_t M:1;
2548	uint32_t WAKE:1;
2549	uint32_t ILT:1;
2550	uint32_t PE:1;
2551	uint32_t PT:1;
2552	uint32_t TIE:1;
2553	uint32_t TCIE:1;
2554	uint32_t RIE:1;
2555	uint32_t ILIE:1;
2556	uint32_t TE:1;
2557	uint32_t RE:1;
2558	uint32_t RWU:1;
2559	uint32_t SBK:1;
2560	} B;
2561	} CR1; /* Control Register 1 */
2562
2563	union ESCI_CR2_tag {
2564	uint16_t R;
2565	struct {
2566	uint16_t MDIS:1;
2567	uint16_t FBR:1;
2568	uint16_t BSTP:1;
2569	uint16_t IEBERR:1;
2570	uint16_t RXDMA:1;
2571	uint16_t TXDMA:1;
2572	uint16_t BRK13:1;
2573	uint16_t:1;
2574	uint16_t BESM13:1;
2575	uint16_t SBSTP:1;
2576	uint16_t:2;
2577	uint16_t ORIE:1;
2578	uint16_t NFIE:1;
2579	uint16_t FEIE:1;
2580	uint16_t PFIE:1;
2581	} B;
2582	} CR2; /* Control Register 2 */
2583
2584	union ESCI_DR_tag {
2585	uint16_t R;
2586	struct {
2587	uint16_t R8:1;
2588	uint16_t T8:1;
2589	uint16_t:6;
2590	uint8_t D;
2591	} B;
2592	} DR; /* Data Register */
2593
2594	union ESCI_SR_tag {
2595	uint32_t R;
2596	struct {
2597	uint32_t TDRE:1;
2598	uint32_t TC:1;
2599	uint32_t RDRF:1;
2600	uint32_t IDLE:1;
2601	uint32_t OR:1;
2602	uint32_t NF:1;
2603	uint32_t FE:1;
2604	uint32_t PF:1;
2605	uint32_t:3;
2606	uint32_t BERR:1;
2607	uint32_t:3;
2608	uint32_t RAF:1;
2609	uint32_t RXRDY:1;
2610	uint32_t TXRDY:1;
2611	uint32_t LWAKE:1;
2612	uint32_t STO:1;
2613	uint32_t PBERR:1;
2614	uint32_t CERR:1;
2615	uint32_t CKERR:1;
2616	uint32_t FRC:1;
2617	uint32_t:7;
2618	uint32_t OVFL:1;
2619	} B;
2620	} SR; /* Status Register */
2621
2622	union {
2623	uint32_t R;
2624	struct {
2625	uint32_t LRES:1;
2626	uint32_t WU:1;
2627	uint32_t WUD0:1;
2628	uint32_t WUD1:1;
2629	uint32_t LDBG:1;
2630	uint32_t DSF:1;
2631	uint32_t PRTY:1;
2632	uint32_t LIN:1;
2633	uint32_t RXIE:1;
2634	uint32_t TXIE:1;
2635	uint32_t WUIE:1;
2636	uint32_t STIE:1;
2637	uint32_t PBIE:1;
2638	uint32_t CIE:1;
2639	uint32_t CKIE:1;
2640	uint32_t FCIE:1;
2641	uint32_t:7;
2642	uint32_t OFIE:1;
2643	uint32_t:8;
2644	} B;
2645	} LCR; /* LIN Control Register */
2646
2647	union {
2648	uint32_t R;
2649	} LTR; /* LIN Transmit Register */
2650
2651	union {
2652	uint32_t R;
2653	} LRR; /* LIN Recieve Register */
2654
2655	union {
2656	uint32_t R;
2657	} LPR; /* LIN CRC Polynom Register */
2658
2659	};
2660	/****************************************************************************/
2661	/* MODULE : FlexCAN */
2662	/****************************************************************************/
2663	struct FLEXCAN2_tag {
2664	union {
2665	uint32_t R;
2666	struct {
2667	uint32_t MDIS:1;
2668	uint32_t FRZ:1;
2669	uint32_t:1;
2670	uint32_t HALT:1;
2671	uint32_t NOTRDY:1;
2672	uint32_t:1;
2673	uint32_t SOFTRST:1;
2674	uint32_t FRZACK:1;
2675	uint32_t:1;
2676	uint32_t:1;
2677
2678	uint32_t WRNEN:1;
2679
2680	uint32_t MDISACK:1;
2681	uint32_t:1;
2682	uint32_t:1;
2683
2684	uint32_t SRXDIS:1;
2685	uint32_t MBFEN:1;
2686	uint32_t:10;
2687
2688	uint32_t MAXMB:6;
2689	} B;
2690	} MCR; /* Module Configuration Register */
2691
2692	union {
2693	uint32_t R;
2694	struct {
2695	uint32_t PRESDIV:8;
2696	uint32_t RJW:2;
2697	uint32_t PSEG1:3;
2698	uint32_t PSEG2:3;
2699	uint32_t BOFFMSK:1;
2700	uint32_t ERRMSK:1;
2701	uint32_t CLKSRC:1;
2702	uint32_t LPB:1;
2703
2704	uint32_t TWRNMSK:1;
2705	uint32_t RWRNMSK:1;
2706	uint32_t:2;
2707
2708	uint32_t SMP:1;
2709	uint32_t BOFFREC:1;
2710	uint32_t TSYN:1;
2711	uint32_t LBUF:1;
2712	uint32_t LOM:1;
2713	uint32_t PROPSEG:3;
2714	} B;
2715	} CR; /* Control Register */
2716
2717	union {
2718	uint32_t R;
2719	} TIMER; /* Free Running Timer */
2720	int32_t FLEXCAN_reserved00;
2721
2722	union {
2723	uint32_t R;
2724	struct {
2725	uint32_t:3;
2726	uint32_t MI:29;
2727	} B;
2728	} RXGMASK; /* RX Global Mask */
2729
2730	union {
2731	uint32_t R;
2732	struct {
2733	uint32_t:3;
2734	uint32_t MI:29;
2735	} B;
2736	} RX14MASK; /* RX 14 Mask */
2737
2738	union {
2739	uint32_t R;
2740	struct {
2741	uint32_t:3;
2742	uint32_t MI:29;
2743	} B;
2744	} RX15MASK; /* RX 15 Mask */
2745
2746	union {
2747	uint32_t R;
2748	struct {
2749	uint32_t:16;
2750	uint32_t RXECNT:8;
2751	uint32_t TXECNT:8;
2752	} B;
2753	} ECR; /* Error Counter Register */
2754
2755	union {
2756	uint32_t R;
2757	struct {
2758	uint32_t:14;
2759
2760	uint32_t TWRNINT:1;
2761	uint32_t RWRNINT:1;
2762
2763	uint32_t BIT1ERR:1;
2764	uint32_t BIT0ERR:1;
2765	uint32_t ACKERR:1;
2766	uint32_t CRCERR:1;
2767	uint32_t FRMERR:1;
2768	uint32_t STFERR:1;
2769	uint32_t TXWRN:1;
2770	uint32_t RXWRN:1;
2771	uint32_t IDLE:1;
2772	uint32_t TXRX:1;
2773	uint32_t FLTCONF:2;
2774	uint32_t:1;
2775	uint32_t BOFFINT:1;
2776	uint32_t ERRINT:1;
2777	uint32_t:1;
2778	} B;
2779	} ESR; /* Error and Status Register */
2780
2781	union {
2782	uint32_t R;
2783	struct {
2784	uint32_t BUF63M:1;
2785	uint32_t BUF62M:1;
2786	uint32_t BUF61M:1;
2787	uint32_t BUF60M:1;
2788	uint32_t BUF59M:1;
2789	uint32_t BUF58M:1;
2790	uint32_t BUF57M:1;
2791	uint32_t BUF56M:1;
2792	uint32_t BUF55M:1;
2793	uint32_t BUF54M:1;
2794	uint32_t BUF53M:1;
2795	uint32_t BUF52M:1;
2796	uint32_t BUF51M:1;
2797	uint32_t BUF50M:1;
2798	uint32_t BUF49M:1;
2799	uint32_t BUF48M:1;
2800	uint32_t BUF47M:1;
2801	uint32_t BUF46M:1;
2802	uint32_t BUF45M:1;
2803	uint32_t BUF44M:1;
2804	uint32_t BUF43M:1;
2805	uint32_t BUF42M:1;
2806	uint32_t BUF41M:1;
2807	uint32_t BUF40M:1;
2808	uint32_t BUF39M:1;
2809	uint32_t BUF38M:1;
2810	uint32_t BUF37M:1;
2811	uint32_t BUF36M:1;
2812	uint32_t BUF35M:1;
2813	uint32_t BUF34M:1;
2814	uint32_t BUF33M:1;
2815	uint32_t BUF32M:1;
2816	} B;
2817	} IMRH; /* Interruput Masks Register */
2818
2819	union {
2820	uint32_t R;
2821	struct {
2822	uint32_t BUF31M:1;
2823	uint32_t BUF30M:1;
2824	uint32_t BUF29M:1;
2825	uint32_t BUF28M:1;
2826	uint32_t BUF27M:1;
2827	uint32_t BUF26M:1;
2828	uint32_t BUF25M:1;
2829	uint32_t BUF24M:1;
2830	uint32_t BUF23M:1;
2831	uint32_t BUF22M:1;
2832	uint32_t BUF21M:1;
2833	uint32_t BUF20M:1;
2834	uint32_t BUF19M:1;
2835	uint32_t BUF18M:1;
2836	uint32_t BUF17M:1;
2837	uint32_t BUF16M:1;
2838	uint32_t BUF15M:1;
2839	uint32_t BUF14M:1;
2840	uint32_t BUF13M:1;
2841	uint32_t BUF12M:1;
2842	uint32_t BUF11M:1;
2843	uint32_t BUF10M:1;
2844	uint32_t BUF09M:1;
2845	uint32_t BUF08M:1;
2846	uint32_t BUF07M:1;
2847	uint32_t BUF06M:1;
2848	uint32_t BUF05M:1;
2849	uint32_t BUF04M:1;
2850	uint32_t BUF03M:1;
2851	uint32_t BUF02M:1;
2852	uint32_t BUF01M:1;
2853	uint32_t BUF00M:1;
2854	} B;
2855	} IMRL; /* Interruput Masks Register */
2856
2857	union {
2858	uint32_t R;
2859	struct {
2860	uint32_t BUF63I:1;
2861	uint32_t BUF62I:1;
2862	uint32_t BUF61I:1;
2863	uint32_t BUF60I:1;
2864	uint32_t BUF59I:1;
2865	uint32_t BUF58I:1;
2866	uint32_t BUF57I:1;
2867	uint32_t BUF56I:1;
2868	uint32_t BUF55I:1;
2869	uint32_t BUF54I:1;
2870	uint32_t BUF53I:1;
2871	uint32_t BUF52I:1;
2872	uint32_t BUF51I:1;
2873	uint32_t BUF50I:1;
2874	uint32_t BUF49I:1;
2875	uint32_t BUF48I:1;
2876	uint32_t BUF47I:1;
2877	uint32_t BUF46I:1;
2878	uint32_t BUF45I:1;
2879	uint32_t BUF44I:1;
2880	uint32_t BUF43I:1;
2881	uint32_t BUF42I:1;
2882	uint32_t BUF41I:1;
2883	uint32_t BUF40I:1;
2884	uint32_t BUF39I:1;
2885	uint32_t BUF38I:1;
2886	uint32_t BUF37I:1;
2887	uint32_t BUF36I:1;
2888	uint32_t BUF35I:1;
2889	uint32_t BUF34I:1;
2890	uint32_t BUF33I:1;
2891	uint32_t BUF32I:1;
2892	} B;
2893	} IFRH; /* Interruput Flag Register */
2894
2895	union {
2896	uint32_t R;
2897	struct {
2898	uint32_t BUF31I:1;
2899	uint32_t BUF30I:1;
2900	uint32_t BUF29I:1;
2901	uint32_t BUF28I:1;
2902	uint32_t BUF27I:1;
2903	uint32_t BUF26I:1;
2904	uint32_t BUF25I:1;
2905	uint32_t BUF24I:1;
2906	uint32_t BUF23I:1;
2907	uint32_t BUF22I:1;
2908	uint32_t BUF21I:1;
2909	uint32_t BUF20I:1;
2910	uint32_t BUF19I:1;
2911	uint32_t BUF18I:1;
2912	uint32_t BUF17I:1;
2913	uint32_t BUF16I:1;
2914	uint32_t BUF15I:1;
2915	uint32_t BUF14I:1;
2916	uint32_t BUF13I:1;
2917	uint32_t BUF12I:1;
2918	uint32_t BUF11I:1;
2919	uint32_t BUF10I:1;
2920	uint32_t BUF09I:1;
2921	uint32_t BUF08I:1;
2922	uint32_t BUF07I:1;
2923	uint32_t BUF06I:1;
2924	uint32_t BUF05I:1;
2925	uint32_t BUF04I:1;
2926	uint32_t BUF03I:1;
2927	uint32_t BUF02I:1;
2928	uint32_t BUF01I:1;
2929	uint32_t BUF00I:1;
2930	} B;
2931	} IFRL; /* Interruput Flag Register */
2932
2933	uint32_t flexcan2_reserved2[19];
2934
2935	struct canbuf_t {
2936	union {
2937	uint32_t R;
2938	struct {
2939	uint32_t:4;
2940	uint32_t CODE:4;
2941	uint32_t:1;
2942	uint32_t SRR:1;
2943	uint32_t IDE:1;
2944	uint32_t RTR:1;
2945	uint32_t LENGTH:4;
2946	uint32_t TIMESTAMP:16;
2947	} B;
2948	} CS;
2949
2950	union {
2951	uint32_t R;
2952	struct {
2953	uint32_t:3;
2954	uint32_t STD_ID:11;
2955	uint32_t EXT_ID:18;
2956	} B;
2957	} ID;
2958
2959	union {
2960	uint8_t B[8]; /* Data buffer in Bytes (8 bits) */
2961	uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
2962	uint32_t W[2]; /* Data buffer in words (32 bits) */
2963	uint32_t R[2]; /* Data buffer in words (32 bits) */
2964	} DATA;
2965
2966	} BUF[64];
2967
2968	uint32_t flexcan2_reserved3[256];
2969
2970	union {
2971	uint32_t R;
2972	struct {
2973	uint32_t:3;
2974	uint32_t MI:29;
2975	} B;
2976	} RXIMR[64]; /* RX Individual Mask Registers */
2977
2978	};
2979	/****************************************************************************/
2980	/* MODULE : FEC */
2981	/****************************************************************************/
2982	struct FEC_tag {
2983
2984	uint32_t fec_reserved_start[0x1];
2985
2986	union {
2987	uint32_t R;
2988	struct {
2989	uint32_t HBERR:1;
2990	uint32_t BABR:1;
2991	uint32_t BABT:1;
2992	uint32_t GRA:1;
2993	uint32_t TXF:1;
2994	uint32_t TXB:1;
2995	uint32_t RXF:1;
2996	uint32_t RXB:1;
2997	uint32_t MII:1;
2998	uint32_t EBERR:1;
2999	uint32_t LC:1;
3000	uint32_t RL:1;
3001	uint32_t UN:1;
3002	uint32_t:19;
3003	} B;
3004	} EIR; /* Interrupt Event Register */
3005
3006	union {
3007	uint32_t R;
3008	struct {
3009	uint32_t HBERRM:1;
3010	uint32_t BABRM:1;
3011	uint32_t BABTM:1;
3012	uint32_t GRAM:1;
3013	uint32_t TXFM:1;
3014	uint32_t TXBM:1;
3015	uint32_t RXFM:1;
3016	uint32_t RXBM:1;
3017	uint32_t MIIM:1;
3018	uint32_t EBERRM:1;
3019	uint32_t LCM:1;
3020	uint32_t RLM:1;
3021	uint32_t UNM:1;
3022	uint32_t:19;
3023	} B;
3024	} EIMR; /* Interrupt Mask Register */
3025
3026	uint32_t fec_reserved_eimr;
3027
3028	union {
3029	uint32_t R;
3030	struct {
3031	uint32_t:7;
3032	uint32_t R_DES_ACTIVE:1;
3033	uint32_t:24;
3034	} B;
3035	} RDAR; /* Receive Descriptor Active Register */
3036
3037	union {
3038	uint32_t R;
3039	struct {
3040	uint32_t:7;
3041	uint32_t X_DES_ACTIVE:1;
3042	uint32_t:24;
3043	} B;
3044	} TDAR; /* Transmit Descriptor Active Register */
3045
3046	uint32_t fec_reserved_tdar[3];
3047
3048	union {
3049	uint32_t R;
3050	struct {
3051	uint32_t:30;
3052	uint32_t ETHER_EN:1;
3053	uint32_t RESET:1;
3054	} B;
3055	} ECR; /* Ethernet Control Register */
3056
3057	uint32_t fec_reserved_ecr[6];
3058
3059	union {
3060	uint32_t R;
3061	struct {
3062	uint32_t ST:2;
3063	uint32_t CP:2;
3064	uint32_t PA:5;
3065	uint32_t RA:5;
3066	uint32_t TA:2;
3067	uint32_t DATA:16;
3068	} B;
3069	} MDATA; /* MII Data Register */
3070
3071	union {
3072	uint32_t R;
3073	struct {
3074	uint32_t:24;
3075	uint32_t DIS_PREAMBLE:1;
3076	uint32_t MII_SPEED:6;
3077	uint32_t:1;
3078	} B;
3079	} MSCR; /* MII Speed Control Register */
3080
3081	uint32_t fec_reserved_mscr[7];
3082
3083	union {
3084	uint32_t R;
3085	struct {
3086	uint32_t MIB_DISABLE:1;
3087	uint32_t MIB_IDLE:1;
3088	uint32_t:30;
3089	} B;
3090	} MIBC; /* MIB Control Register */
3091
3092	uint32_t fec_reserved_mibc[7];
3093
3094	union {
3095	uint32_t R;
3096	struct {
3097	uint32_t:5;
3098	uint32_t MAX_FL:11;
3099	uint32_t:10;
3100	uint32_t FCE:1;
3101	uint32_t BC_REJ:1;
3102	uint32_t PROM:1;
3103	uint32_t MII_MODE:1;
3104	uint32_t DRT:1;
3105	uint32_t LOOP:1;
3106	} B;
3107	} RCR; /* Receive Control Register */
3108
3109	uint32_t fec_reserved_rcr[15];
3110
3111	union {
3112	uint32_t R;
3113	struct {
3114	uint32_t:27;
3115	uint32_t RFC_PAUSE:1;
3116	uint32_t TFC_PAUSE:1;
3117	uint32_t FDEN:1;
3118	uint32_t HBC:1;
3119	uint32_t GTS:1;
3120	} B;
3121	} TCR; /* Transmit Control Register */
3122
3123	uint32_t fec_reserved_tcr[7];
3124
3125	union {
3126	uint32_t R;
3127	struct {
3128	uint32_t PADDR1:32;
3129	} B;
3130	} PALR; /* Physical Address Low Register */
3131
3132	union {
3133	uint32_t R;
3134	struct {
3135	uint32_t PADDR2:16;
3136	uint32_t TYPE:16;
3137	} B;
3138	} PAUR; /* Physical Address High + Type Register */
3139
3140	union {
3141	uint32_t R;
3142	struct {
3143	uint32_t OPCODE:16;
3144	uint32_t PAUSE_DUR:16;
3145	} B;
3146	} OPD; /* Opcode/Pause Duration Register */
3147
3148	uint32_t fec_reserved_opd[10];
3149
3150	union {
3151	uint32_t R;
3152	struct {
3153	uint32_t IADDR1:32;
3154	} B;
3155	} IAUR; /* Descriptor Individual Upper Address Register */
3156
3157	union {
3158	uint32_t R;
3159	struct {
3160	uint32_t IADDR2:32;
3161	} B;
3162	} IALR; /* Descriptor Individual Lower Address Register */
3163
3164	union {
3165	uint32_t R;
3166	struct {
3167	uint32_t GADDR1:32;
3168	} B;
3169	} GAUR; /* Descriptor Group Upper Address Register */
3170
3171	union {
3172	uint32_t R;
3173	struct {
3174	uint32_t GADDR2:32;
3175	} B;
3176	} GALR; /* Descriptor Group Lower Address Register */
3177
3178	uint32_t fec_reserved_galr[7];
3179
3180	union {
3181	uint32_t R;
3182	struct {
3183	uint32_t:30;
3184	uint32_t X_WMRK:2;
3185	} B;
3186	} TFWR; /* FIFO Transmit FIFO Watermark Register */
3187
3188	uint32_t fec_reserved_tfwr;
3189
3190	union {
3191	uint32_t R;
3192	struct {
3193	uint32_t:22;
3194	uint32_t R_BOUND:8;
3195	uint32_t:2;
3196	} B;
3197	} FRBR; /* FIFO Receive Bound Register */
3198
3199	union {
3200	uint32_t R;
3201	struct {
3202	uint32_t:22;
3203	uint32_t R_FSTART:8;
3204	uint32_t:2;
3205	} B;
3206	} FRSR; /* FIFO Receive Start Register */
3207
3208	uint32_t fec_reserved_frsr[11];
3209
3210	union {
3211	uint32_t R;
3212	struct {
3213	uint32_t R_DES_START:30;
3214	uint32_t:2;
3215	} B;
3216	} ERDSR; /* Receive Descriptor Ring Start Register */
3217
3218	union {
3219	uint32_t R;
3220	struct {
3221	uint32_t X_DES_START:30;
3222	uint32_t:2;
3223	} B;
3224	} ETDSR; /* Transmit Descriptor Ring Start Register */
3225
3226	union {
3227	uint32_t R;
3228	struct {
3229	uint32_t:21;
3230	uint32_t R_BUF_SIZE:7;
3231	uint32_t:4;
3232	} B;
3233	} EMRBR; /* Receive Buffer Size Register */
3234
3235	uint32_t fec_reserved_emrbr[29];
3236
3237	union {
3238	uint32_t R;
3239	} RMON_T_DROP; /* Count of frames not counted correctly */
3240
3241	union {
3242	uint32_t R;
3243	} RMON_T_PACKETS; /* RMON Tx packet count */
3244
3245	union {
3246	uint32_t R;
3247	} RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */
3248
3249	union {
3250	uint32_t R;
3251	} RMON_T_MC_PKT; /* RMON Tx Multicast Packets */
3252
3253	union {
3254	uint32_t R;
3255	} RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */
3256
3257	union {
3258	uint32_t R;
3259	} RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */
3260
3261	union {
3262	uint32_t R;
3263	} RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */
3264
3265	union {
3266	uint32_t R;
3267	} RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */
3268
3269	union {
3270	uint32_t R;
3271	} RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */
3272
3273	union {
3274	uint32_t R;
3275	} RMON_T_COL; /* RMON Tx collision count */
3276
3277	union {
3278	uint32_t R;
3279	} RMON_T_P64; /* RMON Tx 64 byte packets */
3280
3281	union {
3282	uint32_t R;
3283	} RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */
3284
3285	union {
3286	uint32_t R;
3287	} RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */
3288
3289	union {
3290	uint32_t R;
3291	} RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */
3292
3293	union {
3294	uint32_t R;
3295	} RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */
3296
3297	union {
3298	uint32_t R;
3299	} RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */
3300
3301	union {
3302	uint32_t R;
3303	} RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */
3304
3305	union {
3306	uint32_t R;
3307	} RMON_T_OCTETS; /* RMON Tx Octets */
3308
3309	union {
3310	uint32_t R;
3311	} IEEE_T_DROP; /* Count of frames not counted correctly */
3312
3313	union {
3314	uint32_t R;
3315	} IEEE_T_FRAME_OK; /* Frames Transmitted OK */
3316
3317	union {
3318	uint32_t R;
3319	} IEEE_T_1COL; /* Frames Transmitted with Single Collision */
3320
3321	union {
3322	uint32_t R;
3323	} IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */
3324
3325	union {
3326	uint32_t R;
3327	} IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */
3328
3329	union {
3330	uint32_t R;
3331	} IEEE_T_LCOL; /* Frames Transmitted with Late Collision */
3332
3333	union {
3334	uint32_t R;
3335	} IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */
3336
3337	union {
3338	uint32_t R;
3339	} IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */
3340
3341	union {
3342	uint32_t R;
3343	} IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */
3344
3345	union {
3346	uint32_t R;
3347	} IEEE_T_SQE; /* Frames Transmitted with SQE Error */
3348
3349	union {
3350	uint32_t R;
3351	} IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */
3352
3353	union {
3354	uint32_t R;
3355	} IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */
3356
3357	uint32_t fec_reserved_rmon_t_octets_ok[2];
3358
3359	union {
3360	uint32_t R;
3361	} RMON_R_DROP; /* Count of frames not counted correctly */
3362
3363	union {
3364	uint32_t R;
3365	} RMON_R_PACKETS; /* RMON Rx packet count */
3366
3367	union {
3368	uint32_t R;
3369	} RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */
3370
3371	union {
3372	uint32_t R;
3373	} RMON_R_MC_PKT; /* RMON Rx Multicast Packets */
3374
3375	union {
3376	uint32_t R;
3377	} RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */
3378
3379	union {
3380	uint32_t R;
3381	} RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */
3382
3383	union {
3384	uint32_t R;
3385	} RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */
3386
3387	union {
3388	uint32_t R;
3389	} RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */
3390
3391	union {
3392	uint32_t R;
3393	} RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */
3394
3395	uint32_t fec_reserved_rmon_r_jab;
3396
3397	union {
3398	uint32_t R;
3399	} RMON_R_P64; /* RMON Rx 64 byte packets */
3400
3401	union {
3402	uint32_t R;
3403	} RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */
3404
3405	union {
3406	uint32_t R;
3407	} RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */
3408
3409	union {
3410	uint32_t R;
3411	} RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */
3412
3413	union {
3414	uint32_t R;
3415	} RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */
3416
3417	union {
3418	uint32_t R;
3419	} RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */
3420
3421	union {
3422	uint32_t R;
3423	} RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */
3424
3425	union {
3426	uint32_t R;
3427	} RMON_R_OCTETS; /* RMON Rx Octets */
3428
3429	union {
3430	uint32_t R;
3431	} IEEE_R_DROP; /* Count of frames not counted correctly */
3432
3433	union {
3434	uint32_t R;
3435	} IEEE_R_FRAME_OK; /* Frames Received OK */
3436
3437	union {
3438	uint32_t R;
3439	} IEEE_R_CRC; /* Frames Received with CRC Error */
3440
3441	union {
3442	uint32_t R;
3443	} IEEE_R_ALIGN; /* Frames Received with Alignment Error */
3444
3445	union {
3446	uint32_t R;
3447	} IEEE_R_MACERR; /* Receive Fifo Overflow count */
3448
3449	union {
3450	uint32_t R;
3451	} IEEE_R_FDXFC; /* Flow Control Pause frames received */
3452
3453	union {
3454	uint32_t R;
3455	} IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */
3456
3457	};
3458	/****************************************************************************/
3459	/* MODULE : FlexRay */
3460	/****************************************************************************/
3461
3462	typedef union uMVR {
3463	uint16_t R;
3464	struct {
3465	uint16_t CHIVER:8; /* CHI Version Number */
3466	uint16_t PEVER:8; /* PE Version Number */
3467	} B;
3468	} MVR_t;
3469
3470	typedef union uMCR {
3471	uint16_t R;
3472	struct {
3473	uint16_t MEN:1; /* module enable */
3474	uint16_t:1;
3475	uint16_t SCMD:1; /* single channel mode */
3476	uint16_t CHB:1; /* channel B enable */
3477	uint16_t CHA:1; /* channel A enable */
3478	uint16_t SFFE:1; /* synchronization frame filter enable */
3479	uint16_t:5;
3480	uint16_t CLKSEL:1; /* protocol engine clock source select */
3481	uint16_t PRESCALE:3; /* protocol engine clock prescaler */
3482	uint16_t:1;
3483	} B;
3484	} MCR_t;
3485	typedef union uSTBSCR {
3486	uint16_t R;
3487	struct {
3488	uint16_t WMD:1; /* write mode */
3489	uint16_t STBSSEL:7; /* strobe signal select */
3490	uint16_t:3;
3491	uint16_t ENB:1; /* strobe signal enable */
3492	uint16_t:2;
3493	uint16_t STBPSEL:2; /* strobe port select */
3494	} B;
3495	} STBSCR_t;
3496	typedef union uSTBPCR {
3497	uint16_t R;
3498	struct {
3499	uint16_t:12;
3500	uint16_t STB3EN:1; /* strobe port enable */
3501	uint16_t STB2EN:1; /* strobe port enable */
3502	uint16_t STB1EN:1; /* strobe port enable */
3503	uint16_t STB0EN:1; /* strobe port enable */
3504	} B;
3505	} STBPCR_t;
3506
3507	typedef union uMBDSR {
3508	uint16_t R;
3509	struct {
3510	uint16_t:1;
3511	uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
3512	uint16_t:1;
3513	uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
3514	} B;
3515	} MBDSR_t;
3516	typedef union uMBSSUTR {
3517	uint16_t R;
3518	struct {
3519
3520	uint16_t:1;
3521	uint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */
3522	uint16_t:1;
3523	uint16_t LAST_MB_UTIL:7; /* last message buffer utilized */
3524	} B;
3525	} MBSSUTR_t;
3526
3527	typedef union uPOCR {
3528	uint16_t R;
3529	uint8_t byte[2];
3530	struct {
3531	uint16_t WME:1; /* write mode external correction command */
3532	uint16_t:3;
3533	uint16_t EOC_AP:2; /* external offset correction application */
3534	uint16_t ERC_AP:2; /* external rate correction application */
3535	uint16_t BSY:1; /* command write busy / write mode command */
3536	uint16_t:3;
3537	uint16_t POCCMD:4; /* protocol command */
3538	} B;
3539	} POCR_t;
3540	/* protocol commands */
3541	typedef union uGIFER {
3542	uint16_t R;
3543	struct {
3544	uint16_t MIF:1; /* module interrupt flag */
3545	uint16_t PRIF:1; /* protocol interrupt flag */
3546	uint16_t CHIF:1; /* CHI interrupt flag */
3547	uint16_t WKUPIF:1; /* wakeup interrupt flag */
3548	uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
3549	uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
3550	uint16_t RBIF:1; /* receive message buffer interrupt flag */
3551	uint16_t TBIF:1; /* transmit buffer interrupt flag */
3552	uint16_t MIE:1; /* module interrupt enable */
3553	uint16_t PRIE:1; /* protocol interrupt enable */
3554	uint16_t CHIE:1; /* CHI interrupt enable */
3555	uint16_t WKUPIE:1; /* wakeup interrupt enable */
3556	uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
3557	uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
3558	uint16_t RBIE:1; /* receive message buffer interrupt enable */
3559	uint16_t TBIE:1; /* transmit buffer interrupt enable */
3560	} B;
3561	} GIFER_t;
3562	typedef union uPIFR0 {
3563	uint16_t R;
3564	struct {
3565	uint16_t FATLIF:1; /* fatal protocol error interrupt flag */
3566	uint16_t INTLIF:1; /* internal protocol error interrupt flag */
3567	uint16_t ILCFIF:1; /* illegal protocol configuration flag */
3568	uint16_t CSAIF:1; /* cold start abort interrupt flag */
3569	uint16_t MRCIF:1; /* missing rate correctio interrupt flag */
3570	uint16_t MOCIF:1; /* missing offset correctio interrupt flag */
3571	uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
3572	uint16_t MXSIF:1; /* max sync frames detected interrupt flag */
3573	uint16_t MTXIF:1; /* media access test symbol received flag */
3574	uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
3575	uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
3576	uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
3577	uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
3578	uint16_t TI2IF:1; /* timer 2 expired interrupt flag */
3579	uint16_t TI1IF:1; /* timer 1 expired interrupt flag */
3580	uint16_t CYSIF:1; /* cycle start interrupt flag */
3581	} B;
3582	} PIFR0_t;
3583	typedef union uPIFR1 {
3584	uint16_t R;
3585	struct {
3586	uint16_t EMCIF:1; /* error mode changed interrupt flag */
3587	uint16_t IPCIF:1; /* illegal protocol command interrupt flag */
3588	uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
3589	uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
3590	uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
3591	uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
3592	uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
3593	uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
3594	uint16_t:2;
3595	uint16_t EVTIF:1; /* even cycle table written interrupt flag */
3596	uint16_t ODTIF:1; /* odd cycle table written interrupt flag */
3597	uint16_t:4;
3598	} B;
3599	} PIFR1_t;
3600	typedef union uPIER0 {
3601	uint16_t R;
3602	struct {
3603	uint16_t FATLIE:1; /* fatal protocol error interrupt enable */
3604	uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
3605	uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
3606	uint16_t CSAIE:1; /* cold start abort interrupt enable */
3607	uint16_t MRCIE:1; /* missing rate correctio interrupt enable */
3608	uint16_t MOCIE:1; /* missing offset correctio interrupt enable */
3609	uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
3610	uint16_t MXSIE:1; /* max sync frames detected interrupt enable */
3611	uint16_t MTXIE:1; /* media access test symbol received interrupt enable */
3612	uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
3613	uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
3614	uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
3615	uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
3616	uint16_t TI2IE:1; /* timer 2 expired interrupt enable */
3617	uint16_t TI1IE:1; /* timer 1 expired interrupt enable */
3618	uint16_t CYSIE:1; /* cycle start interrupt enable */
3619	} B;
3620	} PIER0_t;
3621	typedef union uPIER1 {
3622	uint16_t R;
3623	struct {
3624	uint16_t EMCIE:1; /* error mode changed interrupt enable */
3625	uint16_t IPCIE:1; /* illegal protocol command interrupt enable */
3626	uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
3627	uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
3628	uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
3629	uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
3630	uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
3631	uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
3632	uint16_t:2;
3633	uint16_t EVTIE:1; /* even cycle table written interrupt enable */
3634	uint16_t ODTIE:1; /* odd cycle table written interrupt enable */
3635	uint16_t:4;
3636	} B;
3637	} PIER1_t;
3638	typedef union uCHIERFR {
3639	uint16_t R;
3640	struct {
3641	uint16_t FRLBEF:1; /* flame lost channel B error flag */
3642	uint16_t FRLAEF:1; /* frame lost channel A error flag */
3643	uint16_t PCMIEF:1; /* command ignored error flag */
3644	uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
3645	uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
3646	uint16_t MSBEF:1; /* message buffer search error flag */
3647	uint16_t MBUEF:1; /* message buffer utilization error flag */
3648	uint16_t LCKEF:1; /* lock error flag */
3649	uint16_t DBLEF:1; /* double transmit message buffer lock error flag */
3650	uint16_t SBCFEF:1; /* system bus communication failure error flag */
3651	uint16_t FIDEF:1; /* frame ID error flag */
3652	uint16_t DPLEF:1; /* dynamic payload length error flag */
3653	uint16_t SPLEF:1; /* static payload length error flag */
3654	uint16_t NMLEF:1; /* network management length error flag */
3655	uint16_t NMFEF:1; /* network management frame error flag */
3656	uint16_t ILSAEF:1; /* illegal access error flag */
3657	} B;
3658	} CHIERFR_t;
3659	typedef union uMBIVEC {
3660	uint16_t R;
3661	struct {
3662
3663	uint16_t:1;
3664	uint16_t TBIVEC:7; /* transmit buffer interrupt vector */
3665	uint16_t:1;
3666	uint16_t RBIVEC:7; /* receive buffer interrupt vector */
3667	} B;
3668	} MBIVEC_t;
3669
3670	typedef union uPSR0 {
3671	uint16_t R;
3672	struct {
3673	uint16_t ERRMODE:2; /* error mode */
3674	uint16_t SLOTMODE:2; /* slot mode */
3675	uint16_t:1;
3676	uint16_t PROTSTATE:3; /* protocol state */
3677	uint16_t SUBSTATE:4; /* protocol sub state */
3678	uint16_t:1;
3679	uint16_t WAKEUPSTATUS:3; /* wakeup status */
3680	} B;
3681	} PSR0_t;
3682
3683	/* protocol states */
3684	/* protocol sub-states */
3685	/* wakeup status */
3686	typedef union uPSR1 {
3687	uint16_t R;
3688	struct {
3689	uint16_t CSAA:1; /* cold start attempt abort flag */
3690	uint16_t SCP:1; /* cold start path */
3691	uint16_t:1;
3692	uint16_t REMCSAT:5; /* remanining coldstart attempts */
3693	uint16_t CPN:1; /* cold start noise path */
3694	uint16_t HHR:1; /* host halt request pending */
3695	uint16_t FRZ:1; /* freeze occured */
3696	uint16_t APTAC:5; /* allow passive to active counter */
3697	} B;
3698	} PSR1_t;
3699	typedef union uPSR2 {
3700	uint16_t R;
3701	struct {
3702	uint16_t NBVB:1; /* NIT boundary violation on channel B */
3703	uint16_t NSEB:1; /* NIT syntax error on channel B */
3704	uint16_t STCB:1; /* symbol window transmit conflict on channel B */
3705	uint16_t SBVB:1; /* symbol window boundary violation on channel B */
3706	uint16_t SSEB:1; /* symbol window syntax error on channel B */
3707	uint16_t MTB:1; /* media access test symbol MTS received on channel B */
3708	uint16_t NBVA:1; /* NIT boundary violation on channel A */
3709	uint16_t NSEA:1; /* NIT syntax error on channel A */
3710	uint16_t STCA:1; /* symbol window transmit conflict on channel A */
3711	uint16_t SBVA:1; /* symbol window boundary violation on channel A */
3712	uint16_t SSEA:1; /* symbol window syntax error on channel A */
3713	uint16_t MTA:1; /* media access test symbol MTS received on channel A */
3714	uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
3715	} B;
3716	} PSR2_t;
3717	typedef union uPSR3 {
3718	uint16_t R;
3719	struct {
3720	uint16_t:2;
3721	uint16_t WUB:1; /* wakeup symbol received on channel B */
3722	uint16_t ABVB:1; /* aggregated boundary violation on channel B */
3723	uint16_t AACB:1; /* aggregated additional communication on channel B */
3724	uint16_t ACEB:1; /* aggregated content error on channel B */
3725	uint16_t ASEB:1; /* aggregated syntax error on channel B */
3726	uint16_t AVFB:1; /* aggregated valid frame on channel B */
3727	uint16_t:2;
3728	uint16_t WUA:1; /* wakeup symbol received on channel A */
3729	uint16_t ABVA:1; /* aggregated boundary violation on channel A */
3730	uint16_t AACA:1; /* aggregated additional communication on channel A */
3731	uint16_t ACEA:1; /* aggregated content error on channel A */
3732	uint16_t ASEA:1; /* aggregated syntax error on channel A */
3733	uint16_t AVFA:1; /* aggregated valid frame on channel A */
3734	} B;
3735	} PSR3_t;
3736	typedef union uCIFRR {
3737	uint16_t R;
3738	struct {
3739	uint16_t:8;
3740	uint16_t MIFR:1; /* module interrupt flag */
3741	uint16_t PRIFR:1; /* protocol interrupt flag */
3742	uint16_t CHIFR:1; /* CHI interrupt flag */
3743	uint16_t WUPIFR:1; /* wakeup interrupt flag */
3744	uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
3745	uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
3746	uint16_t RBIFR:1; /* receive message buffer interrupt flag */
3747	uint16_t TBIFR:1; /* transmit buffer interrupt flag */
3748	} B;
3749	} CIFRR_t;
3750	typedef union uSFCNTR {
3751	uint16_t R;
3752	struct {
3753	uint16_t SFEVB:4; /* sync frames channel B, even cycle */
3754	uint16_t SFEVA:4; /* sync frames channel A, even cycle */
3755	uint16_t SFODB:4; /* sync frames channel B, odd cycle */
3756	uint16_t SFODA:4; /* sync frames channel A, odd cycle */
3757	} B;
3758	} SFCNTR_t;
3759
3760	typedef union uSFTCCSR {
3761	uint16_t R;
3762	struct {
3763	uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
3764	uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
3765	uint16_t CYCNUM:6; /* cycle number */
3766	uint16_t ELKS:1; /* even cycle tables lock status */
3767	uint16_t OLKS:1; /* odd cycle tables lock status */
3768	uint16_t EVAL:1; /* even cycle tables valid */
3769	uint16_t OVAL:1; /* odd cycle tables valid */
3770	uint16_t:1;
3771	uint16_t OPT:1; /one pair trigger /
3772	uint16_t SDVEN:1; /* sync frame deviation table enable */
3773	uint16_t SIDEN:1; /* sync frame ID table enable */
3774	} B;
3775	} SFTCCSR_t;
3776	typedef union uSFIDRFR {
3777	uint16_t R;
3778	struct {
3779	uint16_t:6;
3780	uint16_t SYNFRID:10; /* sync frame rejection ID */
3781	} B;
3782	} SFIDRFR_t;
3783
3784	typedef union uTICCR {
3785	uint16_t R;
3786	struct {
3787	uint16_t:2;
3788	uint16_t T2CFG:1; /* timer 2 configuration */
3789	uint16_t T2REP:1; /* timer 2 repetitive mode */
3790	uint16_t:1;
3791	uint16_t T2SP:1; /* timer 2 stop */
3792	uint16_t T2TR:1; /* timer 2 trigger */
3793	uint16_t T2ST:1; /* timer 2 state */
3794	uint16_t:3;
3795	uint16_t T1REP:1; /* timer 1 repetitive mode */
3796	uint16_t:1;
3797	uint16_t T1SP:1; /* timer 1 stop */
3798	uint16_t T1TR:1; /* timer 1 trigger */
3799	uint16_t T1ST:1; /* timer 1 state */
3800
3801	} B;
3802	} TICCR_t;
3803	typedef union uTI1CYSR {
3804	uint16_t R;
3805	struct {
3806	uint16_t:2;
3807	uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
3808	uint16_t:2;
3809	uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
3810
3811	} B;
3812	} TI1CYSR_t;
3813
3814	typedef union uSSSR {
3815	uint16_t R;
3816	struct {
3817	uint16_t WMD:1; /* write mode */
3818	uint16_t:1;
3819	uint16_t SEL:2; /* static slot number */
3820	uint16_t:1;
3821	uint16_t SLOTNUMBER:11; /* selector */
3822	} B;
3823	} SSSR_t;
3824
3825	typedef union uSSCCR {
3826	uint16_t R;
3827	struct {
3828	uint16_t WMD:1; /* write mode */
3829	uint16_t:1;
3830	uint16_t SEL:2; /* selector */
3831	uint16_t:1;
3832	uint16_t CNTCFG:2; /* counter configuration */
3833	uint16_t MCY:1; /* multi cycle selection */
3834	uint16_t VFR:1; /* valid frame selection */
3835	uint16_t SYF:1; /* sync frame selection */
3836	uint16_t NUF:1; /* null frame selection */
3837	uint16_t SUF:1; /* startup frame selection */
3838	uint16_t STATUSMASK:4; /* slot status mask */
3839	} B;
3840	} SSCCR_t;
3841	typedef union uSSR {
3842	uint16_t R;
3843	struct {
3844	uint16_t VFB:1; /* valid frame on channel B */
3845	uint16_t SYB:1; /* valid sync frame on channel B */
3846	uint16_t NFB:1; /* valid null frame on channel B */
3847	uint16_t SUB:1; /* valid startup frame on channel B */
3848	uint16_t SEB:1; /* syntax error on channel B */
3849	uint16_t CEB:1; /* content error on channel B */
3850	uint16_t BVB:1; /* boundary violation on channel B */
3851	uint16_t TCB:1; /* tx conflict on channel B */
3852	uint16_t VFA:1; /* valid frame on channel A */
3853	uint16_t SYA:1; /* valid sync frame on channel A */
3854	uint16_t NFA:1; /* valid null frame on channel A */
3855	uint16_t SUA:1; /* valid startup frame on channel A */
3856	uint16_t SEA:1; /* syntax error on channel A */
3857	uint16_t CEA:1; /* content error on channel A */
3858	uint16_t BVA:1; /* boundary violation on channel A */
3859	uint16_t TCA:1; /* tx conflict on channel A */
3860	} B;
3861	} SSR_t;
3862	typedef union uMTSCFR {
3863	uint16_t R;
3864	struct {
3865	uint16_t MTE:1; /* media access test symbol transmission enable */
3866	uint16_t:1;
3867	uint16_t CYCCNTMSK:6; /* cycle counter mask */
3868	uint16_t:2;
3869	uint16_t CYCCNTVAL:6; /* cycle counter value */
3870	} B;
3871	} MTSCFR_t;
3872	typedef union uRSBIR {
3873	uint16_t R;
3874	struct {
3875	uint16_t WMD:1; /* write mode */
3876	uint16_t:1;
3877	uint16_t SEL:2; /* selector */
3878	uint16_t:4;
3879	uint16_t RSBIDX:8; /* receive shadow buffer index */
3880	} B;
3881	} RSBIR_t;
3882	typedef union uRFDSR {
3883	uint16_t R;
3884	struct {
3885	uint16_t FIFODEPTH:8; /* fifo depth */
3886	uint16_t:1;
3887	uint16_t ENTRYSIZE:7; /* entry size */
3888	} B;
3889	} RFDSR_t;
3890
3891	typedef union uRFRFCFR {
3892	uint16_t R;
3893	struct {
3894	uint16_t WMD:1; /* write mode */
3895	uint16_t IBD:1; /* interval boundary */
3896	uint16_t SEL:2; /* filter number */
3897	uint16_t:1;
3898	uint16_t SID:11; /* slot ID */
3899	} B;
3900	} RFRFCFR_t;
3901
3902	typedef union uRFRFCTR {
3903	uint16_t R;
3904	struct {
3905	uint16_t:4;
3906	uint16_t F3MD:1; /* filter mode */
3907	uint16_t F2MD:1; /* filter mode */
3908	uint16_t F1MD:1; /* filter mode */
3909	uint16_t F0MD:1; /* filter mode */
3910	uint16_t:4;
3911	uint16_t F3EN:1; /* filter enable */
3912	uint16_t F2EN:1; /* filter enable */
3913	uint16_t F1EN:1; /* filter enable */
3914	uint16_t F0EN:1; /* filter enable */
3915	} B;
3916	} RFRFCTR_t;
3917	typedef union uPCR0 {
3918	uint16_t R;
3919	struct {
3920	uint16_t ACTION_POINT_OFFSET:6;
3921	uint16_t STATIC_SLOT_LENGTH:10;
3922	} B;
3923	} PCR0_t;
3924
3925	typedef union uPCR1 {
3926	uint16_t R;
3927	struct {
3928	uint16_t:2;
3929	uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
3930	} B;
3931	} PCR1_t;
3932
3933	typedef union uPCR2 {
3934	uint16_t R;
3935	struct {
3936	uint16_t MINISLOT_AFTER_ACTION_POINT:6;
3937	uint16_t NUMBER_OF_STATIC_SLOTS:10;
3938	} B;
3939	} PCR2_t;
3940
3941	typedef union uPCR3 {
3942	uint16_t R;
3943	struct {
3944	uint16_t WAKEUP_SYMBOL_RX_LOW:6;
3945	uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
3946	uint16_t COLDSTART_ATTEMPTS:5;
3947	} B;
3948	} PCR3_t;
3949
3950	typedef union uPCR4 {
3951	uint16_t R;
3952	struct {
3953	uint16_t CAS_RX_LOW_MAX:7;
3954	uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
3955	} B;
3956	} PCR4_t;
3957
3958	typedef union uPCR5 {
3959	uint16_t R;
3960	struct {
3961	uint16_t TSS_TRANSMITTER:4;
3962	uint16_t WAKEUP_SYMBOL_TX_LOW:6;
3963	uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
3964	} B;
3965	} PCR5_t;
3966
3967	typedef union uPCR6 {
3968	uint16_t R;
3969	struct {
3970	uint16_t:1;
3971	uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
3972	uint16_t MACRO_INITIAL_OFFSET_A:7;
3973	} B;
3974	} PCR6_t;
3975
3976	typedef union uPCR7 {
3977	uint16_t R;
3978	struct {
3979	uint16_t DECODING_CORRECTION_B:9;
3980	uint16_t MICRO_PER_MACRO_NOM_HALF:7;
3981	} B;
3982	} PCR7_t;
3983
3984	typedef union uPCR8 {
3985	uint16_t R;
3986	struct {
3987	uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
3988	uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
3989	uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
3990	} B;
3991	} PCR8_t;
3992
3993	typedef union uPCR9 {
3994	uint16_t R;
3995	struct {
3996	uint16_t MINISLOT_EXISTS:1;
3997	uint16_t SYMBOL_WINDOW_EXISTS:1;
3998	uint16_t OFFSET_CORRECTION_OUT:14;
3999	} B;
4000	} PCR9_t;
4001
4002	typedef union uPCR10 {
4003	uint16_t R;
4004	struct {
4005	uint16_t SINGLE_SLOT_ENABLED:1;
4006	uint16_t WAKEUP_CHANNEL:1;
4007	uint16_t MACRO_PER_CYCLE:14;
4008	} B;
4009	} PCR10_t;
4010
4011	typedef union uPCR11 {
4012	uint16_t R;
4013	struct {
4014	uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
4015	uint16_t KEY_SLOT_USED_FOR_SYNC:1;
4016	uint16_t OFFSET_CORRECTION_START:14;
4017	} B;
4018	} PCR11_t;
4019
4020	typedef union uPCR12 {
4021	uint16_t R;
4022	struct {
4023	uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
4024	uint16_t KEY_SLOT_HEADER_CRC:11;
4025	} B;
4026	} PCR12_t;
4027
4028	typedef union uPCR13 {
4029	uint16_t R;
4030	struct {
4031	uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
4032	uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
4033	} B;
4034	} PCR13_t;
4035
4036	typedef union uPCR14 {
4037	uint16_t R;
4038	struct {
4039	uint16_t RATE_CORRECTION_OUT:11;
4040	uint16_t LISTEN_TIMEOUT_H:5;
4041	} B;
4042	} PCR14_t;
4043
4044	typedef union uPCR15 {
4045	uint16_t R;
4046	struct {
4047	uint16_t LISTEN_TIMEOUT_L:16;
4048	} B;
4049	} PCR15_t;
4050
4051	typedef union uPCR16 {
4052	uint16_t R;
4053	struct {
4054	uint16_t MACRO_INITIAL_OFFSET_B:7;
4055	uint16_t NOISE_LISTEN_TIMEOUT_H:9;
4056	} B;
4057	} PCR16_t;
4058
4059	typedef union uPCR17 {
4060	uint16_t R;
4061	struct {
4062	uint16_t NOISE_LISTEN_TIMEOUT_L:16;
4063	} B;
4064	} PCR17_t;
4065
4066	typedef union uPCR18 {
4067	uint16_t R;
4068	struct {
4069	uint16_t WAKEUP_PATTERN:6;
4070	uint16_t KEY_SLOT_ID:10;
4071	} B;
4072	} PCR18_t;
4073
4074	typedef union uPCR19 {
4075	uint16_t R;
4076	struct {
4077	uint16_t DECODING_CORRECTION_A:9;
4078	uint16_t PAYLOAD_LENGTH_STATIC:7;
4079	} B;
4080	} PCR19_t;
4081
4082	typedef union uPCR20 {
4083	uint16_t R;
4084	struct {
4085	uint16_t MICRO_INITIAL_OFFSET_B:8;
4086	uint16_t MICRO_INITIAL_OFFSET_A:8;
4087	} B;
4088	} PCR20_t;
4089
4090	typedef union uPCR21 {
4091	uint16_t R;
4092	struct {
4093	uint16_t EXTERN_RATE_CORRECTION:3;
4094	uint16_t LATEST_TX:13;
4095	} B;
4096	} PCR21_t;
4097
4098	typedef union uPCR22 {
4099	uint16_t R;
4100	struct {
4101	uint16_t:1;
4102	uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
4103	uint16_t MICRO_PER_CYCLE_H:4;
4104	} B;
4105	} PCR22_t;
4106
4107	typedef union uPCR23 {
4108	uint16_t R;
4109	struct {
4110	uint16_t micro_per_cycle_l:16;
4111	} B;
4112	} PCR23_t;
4113
4114	typedef union uPCR24 {
4115	uint16_t R;
4116	struct {
4117	uint16_t CLUSTER_DRIFT_DAMPING:5;
4118	uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
4119	uint16_t MICRO_PER_CYCLE_MIN_H:4;
4120	} B;
4121	} PCR24_t;
4122
4123	typedef union uPCR25 {
4124	uint16_t R;
4125	struct {
4126	uint16_t MICRO_PER_CYCLE_MIN_L:16;
4127	} B;
4128	} PCR25_t;
4129
4130	typedef union uPCR26 {
4131	uint16_t R;
4132	struct {
4133	uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
4134	uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
4135	uint16_t MICRO_PER_CYCLE_MAX_H:4;
4136	} B;
4137	} PCR26_t;
4138
4139	typedef union uPCR27 {
4140	uint16_t R;
4141	struct {
4142	uint16_t MICRO_PER_CYCLE_MAX_L:16;
4143	} B;
4144	} PCR27_t;
4145
4146	typedef union uPCR28 {
4147	uint16_t R;
4148	struct {
4149	uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
4150	uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
4151	} B;
4152	} PCR28_t;
4153
4154	typedef union uPCR29 {
4155	uint16_t R;
4156	struct {
4157	uint16_t EXTERN_OFFSET_CORRECTION:3;
4158	uint16_t MINISLOTS_MAX:13;
4159	} B;
4160	} PCR29_t;
4161
4162	typedef union uPCR30 {
4163	uint16_t R;
4164	struct {
4165	uint16_t:12;
4166	uint16_t SYNC_NODE_MAX:4;
4167	} B;
4168	} PCR30_t;
4169
4170	typedef struct uMSG_BUFF_CCS {
4171	union {
4172	uint16_t R;
4173	struct {
4174	uint16_t:1;
4175	uint16_t MCM:1; /* message buffer commit mode */
4176	uint16_t MBT:1; /* message buffer type */
4177	uint16_t MTD:1; /* message buffer direction */
4178	uint16_t CMT:1; /* commit for transmission */
4179	uint16_t EDT:1; /* enable / disable trigger */
4180	uint16_t LCKT:1; /* lock request trigger */
4181	uint16_t MBIE:1; /* message buffer interrupt enable */
4182	uint16_t:3;
4183	uint16_t DUP:1; /* data updated */
4184	uint16_t DVAL:1; /* data valid */
4185	uint16_t EDS:1; /* lock status */
4186	uint16_t LCKS:1; /* enable / disable status */
4187	uint16_t MBIF:1; /* message buffer interrupt flag */
4188	} B;
4189	} MBCCSR;
4190	union {
4191	uint16_t R;
4192	struct {
4193	uint16_t MTM:1; /* message buffer transmission mode */
4194	uint16_t CHNLA:1; /* channel assignement */
4195	uint16_t CHNLB:1; /* channel assignement */
4196	uint16_t CCFE:1; /* cycle counter filter enable */
4197	uint16_t CCFMSK:6; /* cycle counter filter mask */
4198	uint16_t CCFVAL:6; /* cycle counter filter value */
4199	} B;
4200	} MBCCFR;
4201	union {
4202	uint16_t R;
4203	struct {
4204	uint16_t:5;
4205	uint16_t FID:11; /* frame ID */
4206	} B;
4207	} MBFIDR;
4208	union {
4209	uint16_t R;
4210	struct {
4211	uint16_t:8;
4212	uint16_t MBIDX:8; /* message buffer index */
4213	} B;
4214	} MBIDXR;
4215	} MSG_BUFF_CCS_t;
4216	typedef union uSYSBADHR {
4217	uint16_t R;
4218	} SYSBADHR_t;
4219	typedef union uSYSBADLR {
4220	uint16_t R;
4221	} SYSBADLR_t;
4222	typedef union uPDAR {
4223	uint16_t R;
4224	} PDAR_t;
4225	typedef union uCASERCR {
4226	uint16_t R;
4227	} CASERCR_t;
4228	typedef union uCBSERCR {
4229	uint16_t R;
4230	} CBSERCR_t;
4231	typedef union uCYCTR {
4232	uint16_t R;
4233	} CYCTR_t;
4234	typedef union uMTCTR {
4235	uint16_t R;
4236	} MTCTR_t;
4237	typedef union uSLTCTAR {
4238	uint16_t R;
4239	} SLTCTAR_t;
4240	typedef union uSLTCTBR {
4241	uint16_t R;
4242	} SLTCTBR_t;
4243	typedef union uRTCORVR {
4244	uint16_t R;
4245	} RTCORVR_t;
4246	typedef union uOFCORVR {
4247	uint16_t R;
4248	} OFCORVR_t;
4249	typedef union uSFTOR {
4250	uint16_t R;
4251	} SFTOR_t;
4252	typedef union uSFIDAFVR {
4253	uint16_t R;
4254	} SFIDAFVR_t;
4255	typedef union uSFIDAFMR {
4256	uint16_t R;
4257	} SFIDAFMR_t;
4258	typedef union uNMVR {
4259	uint16_t R;
4260	} NMVR_t;
4261	typedef union uNMVLR {
4262	uint16_t R;
4263	} NMVLR_t;
4264	typedef union uT1MTOR {
4265	uint16_t R;
4266	} T1MTOR_t;
4267	typedef union uTI2CR0 {
4268	uint16_t R;
4269	} TI2CR0_t;
4270	typedef union uTI2CR1 {
4271	uint16_t R;
4272	} TI2CR1_t;
4273	typedef union uSSCR {
4274	uint16_t R;
4275	} SSCR_t;
4276	typedef union uRFSR {
4277	uint16_t R;
4278	} RFSR_t;
4279	typedef union uRFSIR {
4280	uint16_t R;
4281	} RFSIR_t;
4282	typedef union uRFARIR {
4283	uint16_t R;
4284	} RFARIR_t;
4285	typedef union uRFBRIR {
4286	uint16_t R;
4287	} RFBRIR_t;
4288	typedef union uRFMIDAFVR {
4289	uint16_t R;
4290	} RFMIDAFVR_t;
4291	typedef union uRFMIAFMR {
4292	uint16_t R;
4293	} RFMIAFMR_t;
4294	typedef union uRFFIDRFVR {
4295	uint16_t R;
4296	} RFFIDRFVR_t;
4297	typedef union uRFFIDRFMR {
4298	uint16_t R;
4299	} RFFIDRFMR_t;
4300	typedef union uLDTXSLAR {
4301	uint16_t R;
4302	} LDTXSLAR_t;
4303	typedef union uLDTXSLBR {
4304	uint16_t R;
4305	} LDTXSLBR_t;
4306
4307	typedef struct FR_tag {
4308	volatile MVR_t MVR; /module version register //0 /
4309	volatile MCR_t MCR; /module configuration register //2 /
4310	volatile SYSBADHR_t SYSBADHR; /system memory base address high register //4 /
4311	volatile SYSBADLR_t SYSBADLR; /system memory base address low register //6 /
4312	volatile STBSCR_t STBSCR; /strobe signal control register //8 /
4313	volatile STBPCR_t STBPCR; /strobe port control register //A /
4314	volatile MBDSR_t MBDSR; /message buffer data size register //C /
4315	volatile MBSSUTR_t MBSSUTR; /message buffer segment size and utilization register //E /
4316	uint16_t reserved3a[1]; /10 /
4317	volatile PDAR_t PDAR; /PE data register //12 /
4318	volatile POCR_t POCR; /Protocol operation control register //14 /
4319	volatile GIFER_t GIFER; /global interrupt flag and enable register //16 /
4320	volatile PIFR0_t PIFR0; /protocol interrupt flag register 0 //18 /
4321	volatile PIFR1_t PIFR1; /protocol interrupt flag register 1 //1A /
4322	volatile PIER0_t PIER0; /protocol interrupt enable register 0 //1C /
4323	volatile PIER1_t PIER1; /protocol interrupt enable register 1 //1E /
4324	volatile CHIERFR_t CHIERFR; /CHI error flag register //20 /
4325	volatile MBIVEC_t MBIVEC; /message buffer interrupt vector register //22 /
4326	volatile CASERCR_t CASERCR; /channel A status error counter register //24 /
4327	volatile CBSERCR_t CBSERCR; /channel B status error counter register //26 /
4328	volatile PSR0_t PSR0; /protocol status register 0 //28 /
4329	volatile PSR1_t PSR1; /protocol status register 1 //2A /
4330	volatile PSR2_t PSR2; /protocol status register 2 //2C /
4331	volatile PSR3_t PSR3; /protocol status register 3 //2E /
4332	volatile MTCTR_t MTCTR; /macrotick counter register //30 /
4333	volatile CYCTR_t CYCTR; /cycle counter register //32 /
4334	volatile SLTCTAR_t SLTCTAR; /slot counter channel A register //34 /
4335	volatile SLTCTBR_t SLTCTBR; /slot counter channel B register //36 /
4336	volatile RTCORVR_t RTCORVR; /rate correction value register //38 /
4337	volatile OFCORVR_t OFCORVR; /offset correction value register //3A /
4338	volatile CIFRR_t CIFRR; /combined interrupt flag register //3C /
4339	uint16_t reserved3[1]; /3E /
4340	volatile SFCNTR_t SFCNTR; /sync frame counter register //40 /
4341	volatile SFTOR_t SFTOR; /sync frame table offset register //42 /
4342	volatile SFTCCSR_t SFTCCSR; /sync frame table configuration, control, status register //44 /
4343	volatile SFIDRFR_t SFIDRFR; /sync frame ID rejection filter register //46 /
4344	volatile SFIDAFVR_t SFIDAFVR; /sync frame ID acceptance filter value regiater //48 /
4345	volatile SFIDAFMR_t SFIDAFMR; /sync frame ID acceptance filter mask register //4A /
4346	volatile NMVR_t NMVR[6]; /network management vector registers (12 bytes) //4C /
4347	volatile NMVLR_t NMVLR; /network management vector length register //58 /
4348	volatile TICCR_t TICCR; /timer configuration and control register //5A /
4349	volatile TI1CYSR_t TI1CYSR; /timer 1 cycle set register //5C /
4350	volatile T1MTOR_t T1MTOR; /timer 1 macrotick offset register //5E /
4351	volatile TI2CR0_t TI2CR0; /timer 2 configuration register 0 //60 /
4352	volatile TI2CR1_t TI2CR1; /timer 2 configuration register 1 //62 /
4353	volatile SSSR_t SSSR; /slot status selection register //64 /
4354	volatile SSCCR_t SSCCR; /slot status counter condition register //66 /
4355	volatile SSR_t SSR[8]; /slot status registers 0-7 //68 /
4356	volatile SSCR_t SSCR[4]; /slot status counter registers 0-3 //78 /
4357	volatile MTSCFR_t MTSACFR; /mts a config register //80 /
4358	volatile MTSCFR_t MTSBCFR; /mts b config register //82 /
4359	volatile RSBIR_t RSBIR; /receive shadow buffer index register //84 /
4360	volatile RFSR_t RFSR; /receive fifo selection register //86 /
4361	volatile RFSIR_t RFSIR; /receive fifo start index register //88 /
4362	volatile RFDSR_t RFDSR; /receive fifo depth and size register //8A /
4363	volatile RFARIR_t RFARIR; /receive fifo a read index register //8C /
4364	volatile RFBRIR_t RFBRIR; /receive fifo b read index register //8E /
4365	volatile RFMIDAFVR_t RFMIDAFVR; /receive fifo message ID acceptance filter value register //90 /
4366	volatile RFMIAFMR_t RFMIAFMR; /receive fifo message ID acceptance filter mask register //92 /
4367	volatile RFFIDRFVR_t RFFIDRFVR; /receive fifo frame ID rejection filter value register //94 /
4368	volatile RFFIDRFMR_t RFFIDRFMR; /receive fifo frame ID rejection filter mask register //96 /
4369	volatile RFRFCFR_t RFRFCFR; /receive fifo range filter configuration register //98 /
4370	volatile RFRFCTR_t RFRFCTR; /receive fifo range filter control register //9A /
4371	volatile LDTXSLAR_t LDTXSLAR; /last dynamic transmit slot channel A register //9C /
4372	volatile LDTXSLBR_t LDTXSLBR; /last dynamic transmit slot channel B register //9E /
4373	volatile PCR0_t PCR0; /protocol configuration register 0 //A0 /
4374	volatile PCR1_t PCR1; /protocol configuration register 1 //A2 /
4375	volatile PCR2_t PCR2; /protocol configuration register 2 //A4 /
4376	volatile PCR3_t PCR3; /protocol configuration register 3 //A6 /
4377	volatile PCR4_t PCR4; /protocol configuration register 4 //A8 /
4378	volatile PCR5_t PCR5; /protocol configuration register 5 //AA /
4379	volatile PCR6_t PCR6; /protocol configuration register 6 //AC /
4380	volatile PCR7_t PCR7; /protocol configuration register 7 //AE /
4381	volatile PCR8_t PCR8; /protocol configuration register 8 //B0 /
4382	volatile PCR9_t PCR9; /protocol configuration register 9 //B2 /
4383	volatile PCR10_t PCR10; /protocol configuration register 10 //B4 /
4384	volatile PCR11_t PCR11; /protocol configuration register 11 //B6 /
4385	volatile PCR12_t PCR12; /protocol configuration register 12 //B8 /
4386	volatile PCR13_t PCR13; /protocol configuration register 13 //BA /
4387	volatile PCR14_t PCR14; /protocol configuration register 14 //BC /
4388	volatile PCR15_t PCR15; /protocol configuration register 15 //BE /
4389	volatile PCR16_t PCR16; /protocol configuration register 16 //C0 /
4390	volatile PCR17_t PCR17; /protocol configuration register 17 //C2 /
4391	volatile PCR18_t PCR18; /protocol configuration register 18 //C4 /
4392	volatile PCR19_t PCR19; /protocol configuration register 19 //C6 /
4393	volatile PCR20_t PCR20; /protocol configuration register 20 //C8 /
4394	volatile PCR21_t PCR21; /protocol configuration register 21 //CA /
4395	volatile PCR22_t PCR22; /protocol configuration register 22 //CC /
4396	volatile PCR23_t PCR23; /protocol configuration register 23 //CE /
4397	volatile PCR24_t PCR24; /protocol configuration register 24 //D0 /
4398	volatile PCR25_t PCR25; /protocol configuration register 25 //D2 /
4399	volatile PCR26_t PCR26; /protocol configuration register 26 //D4 /
4400	volatile PCR27_t PCR27; /protocol configuration register 27 //D6 /
4401	volatile PCR28_t PCR28; /protocol configuration register 28 //D8 /
4402	volatile PCR29_t PCR29; /protocol configuration register 29 //DA /
4403	volatile PCR30_t PCR30; /protocol configuration register 30 //DC /
4404	uint16_t reserved2[17];
4405	volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 //100 */
4406	} FR_tag_t;
4407
4408	typedef union uF_HEADER /* frame header */
4409	{
4410	struct {
4411	uint16_t:5;
4412	uint16_t HDCRC:11; /* Header CRC */
4413	uint16_t:2;
4414	uint16_t CYCCNT:6; /* Cycle Count */
4415	uint16_t:1;
4416	uint16_t PLDLEN:7; /* Payload Length */
4417	uint16_t:1;
4418	uint16_t PPI:1; /* Payload Preamble Indicator */
4419	uint16_t NUF:1; /* Null Frame Indicator */
4420	uint16_t SYF:1; /* Sync Frame Indicator */
4421	uint16_t SUF:1; /* Startup Frame Indicator */
4422	uint16_t FID:11; /* Frame ID */
4423	} B;
4424	uint16_t WORDS[3];
4425	} F_HEADER_t;
4426	typedef union uS_STSTUS /* slot status */
4427	{
4428	struct {
4429	uint16_t VFB:1; /* Valid Frame on channel B */
4430	uint16_t SYB:1; /* Sync Frame Indicator channel B */
4431	uint16_t NFB:1; /* Null Frame Indicator channel B */
4432	uint16_t SUB:1; /* Startup Frame Indicator channel B */
4433	uint16_t SEB:1; /* Syntax Error on channel B */
4434	uint16_t CEB:1; /* Content Error on channel B */
4435	uint16_t BVB:1; /* Boundary Violation on channel B */
4436	uint16_t CH:1; /* Channel */
4437	uint16_t VFA:1; /* Valid Frame on channel A */
4438	uint16_t SYA:1; /* Sync Frame Indicator channel A */
4439	uint16_t NFA:1; /* Null Frame Indicator channel A */
4440	uint16_t SUA:1; /* Startup Frame Indicator channel A */
4441	uint16_t SEA:1; /* Syntax Error on channel A */
4442	uint16_t CEA:1; /* Content Error on channel A */
4443	uint16_t BVA:1; /* Boundary Violation on channel A */
4444	uint16_t:1;
4445	} RX;
4446	struct {
4447	uint16_t VFB:1; /* Valid Frame on channel B */
4448	uint16_t SYB:1; /* Sync Frame Indicator channel B */
4449	uint16_t NFB:1; /* Null Frame Indicator channel B */
4450	uint16_t SUB:1; /* Startup Frame Indicator channel B */
4451	uint16_t SEB:1; /* Syntax Error on channel B */
4452	uint16_t CEB:1; /* Content Error on channel B */
4453	uint16_t BVB:1; /* Boundary Violation on channel B */
4454	uint16_t TCB:1; /* Tx Conflict on channel B */
4455	uint16_t VFA:1; /* Valid Frame on channel A */
4456	uint16_t SYA:1; /* Sync Frame Indicator channel A */
4457	uint16_t NFA:1; /* Null Frame Indicator channel A */
4458	uint16_t SUA:1; /* Startup Frame Indicator channel A */
4459	uint16_t SEA:1; /* Syntax Error on channel A */
4460	uint16_t CEA:1; /* Content Error on channel A */
4461	uint16_t BVA:1; /* Boundary Violation on channel A */
4462	uint16_t TCA:1; /* Tx Conflict on channel A */
4463	} TX;
4464	uint16_t R;
4465	} S_STATUS_t;
4466
4467	typedef struct uMB_HEADER /* message buffer header */
4468	{
4469	F_HEADER_t FRAME_HEADER;
4470	uint16_t DATA_OFFSET;
4471	S_STATUS_t SLOT_STATUS;
4472	} MB_HEADER_t;
4473
4474	/* Define memories */
4475
4476	#define SRAM_START 0x40000000
4477	#define SRAM_SIZE 0x14000
4478	#define SRAM_END 0x40013FFF
4479
4480	#define FLASH_START 0x0
4481	#define FLASH_SIZE 0x200000
4482	#define FLASH_END 0x1FFFFF
4483
4484	/* Define instances of modules */
4485	#define PBRIDGE_A ((volatile struct PBRIDGE_A_tag ) 0xC3F00000)
4486	#define FMPLL ((volatile struct FMPLL_tag ) 0xC3F80000)
4487	#define EBI ((volatile struct EBI_tag ) 0xC3F84000)
4488	#define FLASH ((volatile struct FLASH_tag ) 0xC3F88000)
4489	#define SIU ((volatile struct SIU_tag ) 0xC3F90000)
4490
4491	#define EMIOS ((volatile struct EMIOS_tag ) 0xC3FA0000)
4492	#define ETPU ((volatile struct ETPU_tag ) 0xC3FC0000)
4493	#define ETPU_DATA_RAM (( uint32_t ) 0xC3FC8000)
4494	#define ETPU_DATA_RAM_EXT (( uint32_t ) 0xC3FCC000)
4495	#define ETPU_DATA_RAM_END 0xC3FC89FC
4496	#define CODE_RAM (( uint32_t ) 0xC3FD0000)
4497	#define ETPU_CODE_RAM (( uint32_t ) 0xC3FD0000)
4498
4499	#define PBRIDGE_B ((volatile struct PBRIDGE_B_tag ) 0xFFF00000)
4500	#define XBAR ((volatile struct XBAR_tag ) 0xFFF04000)
4501	#define ECSM ((volatile struct ECSM_tag ) 0xFFF40000)
4502	#define EDMA ((volatile struct EDMA_tag ) 0xFFF44000)
4503	#define INTC ((volatile struct INTC_tag ) 0xFFF48000)
4504
4505	#define EQADC ((volatile struct EQADC_tag ) 0xFFF80000)
4506
4507	#define DSPI_A ((volatile struct DSPI_tag ) 0xFFF90000)
4508	#define DSPI_B ((volatile struct DSPI_tag ) 0xFFF94000)
4509	#define DSPI_C ((volatile struct DSPI_tag ) 0xFFF98000)
4510	#define DSPI_D ((volatile struct DSPI_tag ) 0xFFF9C000)
4511
4512	#define ESCI_A ((volatile struct ESCI_tag ) 0xFFFB0000)
4513	#define ESCI_B ((volatile struct ESCI_tag ) 0xFFFB4000)
4514
4515	#define CAN_A ((volatile struct FLEXCAN2_tag ) 0xFFFC0000)
4516	#define CAN_B ((volatile struct FLEXCAN2_tag ) 0xFFFC4000)
4517	#define CAN_C ((volatile struct FLEXCAN2_tag ) 0xFFFC8000)
4518	#define CAN_D ((volatile struct FLEXCAN2_tag ) 0xFFFCC000)
4519	#define CAN_E ((volatile struct FLEXCAN2_tag ) 0xFFFD0000)
4520
4521	#define FEC ((volatile struct FEC_tag ) 0xFFF4C000)
4522
4523	#define FR ((volatile struct FR_tag ) 0xFFFE0000)
4524
4525	#ifdef __MWERKS__
4526	#pragma pop
4527	#endif
4528
4529	#ifdef __cplusplus
4530	}
4531	#endif
4532	#endif /* ASM */
4533	#endif /* ifdef _MPC5567_H */
4534	/*********************************************************************
4535	*
4536	* Copyright:
4537	* Freescale Semiconductor, INC. All Rights Reserved.
4538	* You are hereby granted a copyright license to use, modify, and
4539	* distribute the SOFTWARE so long as this entire notice is
4540	* retained without alteration in any modified and/or redistributed
4541	* versions, and that such modified versions are clearly identified
4542	* as such. No licenses are granted by implication, estoppel or
4543	* otherwise under any patents or trademarks of Freescale
4544	* Semiconductor, Inc. This software is provided on an "AS IS"
4545	* basis and without warranty.
4546	*
4547	* To the maximum extent permitted by applicable law, Freescale
4548	* Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
4549	* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
4550	* PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
4551	* REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
4552	* AND ANY ACCOMPANYING WRITTEN MATERIALS.
4553	*
4554	* To the maximum extent permitted by applicable law, IN NO EVENT
4555	* SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
4556	* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
4557	* BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
4558	* PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
4559	*
4560	* Freescale Semiconductor assumes no responsibility for the
4561	* maintenance and support of this software
4562	*
4563	********************************************************************/

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source: rtems/bsps/powerpc/include/mpc55xx/fsl-mpc556x.h @ 9964895

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