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source: rtems/bsps/powerpc/include/bsp/vmeUniverse.h @ 828276b

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Last change on this file since 828276b was 828276b, checked in by Sebastian Huber <sebastian.huber@…>, on 03/05/19 at 06:58:18

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1	/**
2	* @file
3	*
4	* @ingroup shared_vmeuniverse
5	*
6	* @brief Driver for the Tundra Universe II pci-vme bridge
7	*/
8
9	#ifndef VME_UNIVERSE_UTIL_H
10	#define VME_UNIVERSE_UTIL_H
11
12	/*
13	* Authorship
14	* ----------
15	* This software was created by
16	* Till Straumann <strauman@slac.stanford.edu>, 2000-2007,
17	* Stanford Linear Accelerator Center, Stanford University.
18	*
19	* Acknowledgement of sponsorship
20	* ------------------------------
21	* This software was produced by
22	* the Stanford Linear Accelerator Center, Stanford University,
23	* under Contract DE-AC03-76SFO0515 with the Department of Energy.
24	*
25	* Government disclaimer of liability
26	* ----------------------------------
27	* Neither the United States nor the United States Department of Energy,
28	* nor any of their employees, makes any warranty, express or implied, or
29	* assumes any legal liability or responsibility for the accuracy,
30	* completeness, or usefulness of any data, apparatus, product, or process
31	* disclosed, or represents that its use would not infringe privately owned
32	* rights.
33	*
34	* Stanford disclaimer of liability
35	* --------------------------------
36	* Stanford University makes no representations or warranties, express or
37	* implied, nor assumes any liability for the use of this software.
38	*
39	* Stanford disclaimer of copyright
40	* --------------------------------
41	* Stanford University, owner of the copyright, hereby disclaims its
42	* copyright and all other rights in this software. Hence, anyone may
43	* freely use it for any purpose without restriction.
44	*
45	* Maintenance of notices
46	* ----------------------
47	* In the interest of clarity regarding the origin and status of this
48	* SLAC software, this and all the preceding Stanford University notices
49	* are to remain affixed to any copy or derivative of this software made
50	* or distributed by the recipient and are to be affixed to any copy of
51	* software made or distributed by the recipient that contains a copy or
52	* derivative of this software.
53	*
54	* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
55	*/
56
57	/**
58	* @defgroup shared_vmeuniverse_reg Register definitions
59	*
60	* @ingroup shared_vmeuniverse
61	*
62	* @brief all registers contents in PCI space are LITTLE ENDIAN
63	*/
64
65	#ifdef __vxworks
66	#include <vme.h>
67	#else
68
69	#include <bsp/vme_am_defs.h>
70
71	#endif
72
73	/* These bits can be or'ed with the address-modifier when calling
74	* the 'XlateAddr' routine below to further qualify the
75	* search criteria.
76	*/
77	#define VME_MODE_MATCH_MASK (3<<30)
78	#define VME_MODE_EXACT_MATCH (2<<30) /* all bits must match */
79	#define VME_MODE_AS_MATCH (1<<30) /* only A16/24/32 must match */
80
81
82	typedef unsigned long LERegister; /* emphasize contents are little endian */
83
84	/**** NOTE: USE OF VmeUniverseDMAPacket IS DEPRECATED *******
85	**** USE API IN VMEDMA.h INSTEAD *******/
86
87	/* NOTE: DMA packet descriptors MUST be 32 byte aligned */
88	typedef struct VmeUniverseDMAPacketRec_ {
89	LERegister dctl __attribute__((aligned(32)));
90	LERegister dtbc __attribute__((packed));
91	LERegister dla __attribute__((packed));
92	LERegister dummy1 __attribute__((packed));
93	LERegister dva __attribute__((packed));
94	LERegister dummy2 __attribute__((packed));
95	LERegister dcpp __attribute__((packed));
96	LERegister dummy3 __attribute__((packed));
97	} VmeUniverseDMAPacketRec, VmeUniverseDMAPacket; / DEPRECATED */
98
99	/* PCI CSR register */
100	#define UNIV_REGOFF_PCI_CSR 0x4
101	# define UNIV_PCI_CSR_D_PE (1<<31) /* detected parity error; write 1 to clear */
102	# define UNIV_PCI_CSR_S_SERR (1<<30) /* SERR (signalled error) asserted; write 1 to clear */
103	# define UNIV_PCI_CSR_R_MA (1<<29) /* received master abort; write 1 to clear */
104	# define UNIV_PCI_CSR_R_TA (1<<28) /* received target abort; write 1 to clear */
105	# define UNIV_PCI_CSR_S_TA (1<<27) /* signalled target abort; write 1 to clear */
106	# define UNIV_PCI_CSR_DEVSEL_MASK (3<<25) /* device select timing (RO) */
107	# define UNIV_PCI_CSR_DP_D (1<<24) /* data parity error detected; write 1 to clear */
108	# define UNIV_PCI_CSR_TFBBC (1<<23) /* target fast back to back capable (RO) */
109	# define UNIV_PCI_CSR_MFBBC (1<<9) /* master fast back to back capable (RO) */
110	# define UNIV_PCI_CSR_SERR_EN (1<<8) /* enable SERR driver */
111	# define UNIV_PCI_CSR_WAIT (1<<7) /* wait cycle control (RO) */
112	# define UNIV_PCI_CSR_PERESP (1<<6) /* parity error response enable */
113	# define UNIV_PCI_CSR_VGAPS (1<<5) /* VGA palette snoop (RO) */
114	# define UNIV_PCI_CSR_MWI_EN (1<<4) /* Memory write and invalidate enable (RO) */
115	# define UNIV_PCI_CSR_SC (1<<3) /* special cycles (RO) */
116	# define UNIV_PCI_CSR_BM (1<<2) /* master enable (MUST SET TO ENABLE VME SLAVES) */
117	# define UNIV_PCI_CSR_MS (1<<1) /* target memory enable */
118	# define UNIV_PCI_CSR_IOS (1<<0) /* target IO enable */
119
120	/* Special cycle (ADOH, RMW) control register */
121	#define UNIV_REGOFF_SCYC_CTL 0x170 /* write 0 to disable */
122	# define UNIV_SCYC_CTL_LAS_IO (1<<2) /* PCI address space (1: IO, 0: mem) */
123	# define UNIV_SCYC_CTL_SCYC_RMW (1<<0) /* do a RMW cycle when reading PCI address */
124	# define UNIV_SCYC_CTL_SCYC_ADOH (2<<0) /* do a ADOH cycle when reading/writing PCI address */
125
126	/* Special cycle address register */
127	#define UNIV_REGOFF_SCYC_ADDR 0x174 /* PCI address (must be long word aligned) */
128
129	/* Special cycle Swap/Compare/Enable */
130	#define UNIV_REGOFF_SCYC_EN 0x178 /* mask determining the bits involved in the compare and swap operations for VME RMW cycles */
131
132	/* Special cycle compare data register */
133	#define UNIV_REGOFF_SCYC_CMP 0x17c /* data to compare with word returned from VME RMW read */
134
135	/* Special cycle swap data register */
136	#define UNIV_REGOFF_SCYC_SWP 0x180 /* If enabled bits of CMP match, corresponding SWP bits are written back to VME (under control of EN) */
137
138	/* PCI miscellaneous register */
139	#define UNIV_REGOFF_LMISC 0x184
140	# define UNIV_LMISC_CRT_MASK (7<<28) /* Univ. I only, not used on II */
141	# define UNIV_LMISC_CRT_INF (0<<28) /* Coupled Request Timeout */
142	# define UNIV_LMISC_CRT_128_US (1<<28) /* Coupled Request Timeout */
143	# define UNIV_LMISC_CRT_256_US (2<<28) /* Coupled Request Timeout */
144	# define UNIV_LMISC_CRT_512_US (3<<28) /* Coupled Request Timeout */
145	# define UNIV_LMISC_CRT_1024_US (4<<28) /* Coupled Request Timeout */
146	# define UNIV_LMISC_CRT_2048_US (5<<28) /* Coupled Request Timeout */
147	# define UNIV_LMISC_CRT_4096_US (6<<28) /* Coupled Request Timeout */
148
149	# define UNIV_LMISC_CWT_MASK (7<<24) /* coupled window timer */
150	# define UNIV_LMISC_CWT_DISABLE 0 /* disabled (release VME after 1 coupled xaction) */
151	# define UNIV_LMISC_CWT_16 (1<<24) /* 16 PCI clock cycles */
152	# define UNIV_LMISC_CWT_32 (2<<24) /* 32 PCI clock cycles */
153	# define UNIV_LMISC_CWT_64 (3<<24) /* 64 PCI clock cycles */
154	# define UNIV_LMISC_CWT_128 (4<<24) /* 128 PCI clock cycles */
155	# define UNIV_LMISC_CWT_256 (5<<24) /* 256 PCI clock cycles */
156	# define UNIV_LMISC_CWT_512 (6<<24) /* 512 PCI clock cycles */
157
158	/* PCI Command Error Log Register */
159	#define UNIV_REGOFF_L_CMDERR 0x18c
160	# define UNIV_L_CMDERR_CMDERR(reg) (((reg)>>28)&0xf) /* extract PCI cmd error log */
161	# define UNIV_L_CMDERR_M_ERR (1<<27) /* multiple errors have occurred */
162	# define UNIV_L_CMDERR_L_STAT (1<<23) /* PCI error log status valid (write 1 to clear and enable logging) */
163
164	/* PCI Address Error Log */
165	#define UNIV_REGOFF_LAERR 0x190 /* PCI fault address (if L_CMDERR_L_STAT valid) */
166	/* DMA Xfer Control Register */
167	#define UNIV_REGOFF_DCTL 0x200
168	# define UNIV_DCTL_L2V (1<<31) /* PCI->VME if set */
169	# define UNIV_DCTL_VDW_MSK (3<<22) /* VME max. width mask 0x00c00000 */
170	# define UNIV_DCTL_VDW_8 (0<<22) /* VME max. width 8 */
171	# define UNIV_DCTL_VDW_16 (1<<22) /* VME max. width 16 */
172	# define UNIV_DCTL_VDW_32 (2<<22) /* VME max. width 32 */
173	# define UNIV_DCTL_VDW_64 (3<<22) /* VME max. width 64 */
174	# define UNIV_DCTL_VAS_MSK (7<<16) /* VME AS mask 0x00070000 */
175	# define UNIV_DCTL_VAS_A16 (0<<16) /* VME A16 */
176	# define UNIV_DCTL_VAS_A24 (1<<16) /* VME A24 */
177	# define UNIV_DCTL_VAS_A32 (2<<16) /* VME A32 */
178	# define UNIV_DCTL_PGM_MSK (3<<14) /* VME PGM/DATA mask 0x0000c000 */
179	# define UNIV_DCTL_PGM (1<<14) /* VME PGM(1)/DATA(0) */
180	# define UNIV_DCTL_SUPER_MSK (3<<12) /* VME SUPER/USR mask 0x00003000 */
181	# define UNIV_DCTL_SUPER (1<<12) /* VME SUPER(1)/USR(0) */
182	# define UNIV_DCTL_NO_VINC (1<<9) /* VME no VME address increment [Universe IIa/b ONLY */
183	# define UNIV_DCTL_VCT (1<<8) /* VME enable BLT */
184	# define UNIV_DCTL_LD64EN (1<<7) /* PCI 64 enable */
185
186	/* DMA Xfer byte count register (is updated by DMA) */
187	#define UNIV_REGOFF_DTBC 0x204
188	/* DMA Xfer local (PCI) address (direction is set in DCTL) */
189	#define UNIV_REGOFF_DLA 0x208
190	/* DMA Xfer VME address (direction is set in DCTL)
191	* NOTE: (UNIV_DVA) & ~7 == (UNIV_DLA) & ~7 MUST HOLD
192	*/
193	#define UNIV_REGOFF_DVA 0x210
194
195	/* DMA Xfer VME command packet pointer
196	* NOTE: The address stored here MUST be 32-byte aligned
197	*/
198	#define UNIV_REGOFF_DCPP 0x218
199	/* these bits are only used in linked lists */
200	# define UNIV_DCPP_IMG_NULL (1<<0) /* last packet in list */
201	# define UNIV_DCPP_IMG_PROCESSED (1<<1) /* packet processed */
202
203	/* DMA Xfer General Control/Status register */
204	#define UNIV_REGOFF_DGCS 0x220
205	# define UNIV_DGCS_GO (1<<31) /* start xfer */
206	# define UNIV_DGCS_STOP_REQ (1<<30) /* stop xfer (immediate abort) */
207	# define UNIV_DGCS_HALT_REQ (1<<29) /* halt xfer (abort after current packet) */
208	# define UNIV_DGCS_CHAIN (1<<27) /* enable linked list mode */
209	# define UNIV_DGCS_VON_MSK (7<<20) /* VON mask */
210	# define UNIV_DGCS_VON_DONE (0<<20) /* VON counter disabled (do until done) */
211	# define UNIV_DGCS_VON_256 (1<<20) /* VON yield bus after 256 bytes */
212	# define UNIV_DGCS_VON_512 (2<<20) /* VON yield bus after 512 bytes */
213	# define UNIV_DGCS_VON_1024 (3<<20) /* VON yield bus after 1024 bytes */
214	# define UNIV_DGCS_VON_2048 (4<<20) /* VON yield bus after 2048 bytes */
215	# define UNIV_DGCS_VON_4096 (5<<20) /* VON yield bus after 4096 bytes */
216	# define UNIV_DGCS_VON_8192 (6<<20) /* VON yield bus after 8192 bytes */
217	# define UNIV_DGCS_VON_16384 (7<<20) /* VON yield bus after 16384 bytes */
218	# define UNIV_DGCS_VOFF_MSK (15<<16) /* VOFF mask */
219	# define UNIV_DGCS_VOFF_0_US (0<<16) /* re-request VME master after 0 us */
220	# define UNIV_DGCS_VOFF_2_US (8<<16) /* re-request VME master after 2 us */
221	# define UNIV_DGCS_VOFF_4_US (9<<16) /* re-request VME master after 4 us */
222	# define UNIV_DGCS_VOFF_8_US (10<<16)/* re-request VME master after 8 us */
223	# define UNIV_DGCS_VOFF_16_US (1<<16) /* re-request VME master after 16 us */
224	# define UNIV_DGCS_VOFF_32_US (2<<16) /* re-request VME master after 32 us */
225	# define UNIV_DGCS_VOFF_64_US (3<<16) /* re-request VME master after 64 us */
226	# define UNIV_DGCS_VOFF_128_US (4<<16) /* re-request VME master after 128 us */
227	# define UNIV_DGCS_VOFF_256_US (5<<16) /* re-request VME master after 256 us */
228	# define UNIV_DGCS_VOFF_512_US (6<<16) /* re-request VME master after 512 us */
229	# define UNIV_DGCS_VOFF_1024_US (7<<16) /* re-request VME master after 1024 us */
230	/* Status Bits (write 1 to clear) */
231	# define UNIV_DGCS_ACT (1<<15) /* DMA active */
232	# define UNIV_DGCS_STOP (1<<14) /* DMA stopped */
233	# define UNIV_DGCS_HALT (1<<13) /* DMA halted */
234	# define UNIV_DGCS_DONE (1<<11) /* DMA done (OK) */
235	# define UNIV_DGCS_LERR (1<<10) /* PCI bus error */
236	# define UNIV_DGCS_VERR (1<<9) /* VME bus error */
237	# define UNIV_DGCS_P_ERR (1<<8) /* programming protocol error (e.g. PCI master disabled) */
238	# define UNIV_DGCS_STATUS_CLEAR\
239	(UNIV_DGCS_ACT\|UNIV_DGCS_STOP\|UNIV_DGCS_HALT\|\
240	UNIV_DGCS_DONE\|UNIV_DGCS_LERR\|UNIV_DGCS_VERR\|UNIV_DGCS_P_ERR)
241	# define UNIV_DGCS_P_ERR (1<<8) /* programming protocol error (e.g. PCI master disabled) */
242	/* Interrupt Mask Bits */
243	# define UNIV_DGCS_INT_STOP (1<<6) /* interrupt when stopped */
244	# define UNIV_DGCS_INT_HALT (1<<5) /* interrupt when halted */
245	# define UNIV_DGCS_INT_DONE (1<<3) /* interrupt when done */
246	# define UNIV_DGCS_INT_LERR (1<<2) /* interrupt on LERR */
247	# define UNIV_DGCS_INT_VERR (1<<1) /* interrupt on VERR */
248	# define UNIV_DGCS_INT_P_ERR (1<<0) /* interrupt on P_ERR */
249	# define UNIV_DGCS_INT_MSK (0x0000006f) /* interrupt mask */
250
251	/* DMA Linked List Update Enable Register */
252	#define UNIV_REGOFF_D_LLUE 0x224
253	# define UNIV_D_LLUE_UPDATE (1<<31)
254
255
256	/* PCI (local) interrupt enable register */
257	#define UNIV_REGOFF_LINT_EN 0x300
258	# define UNIV_LINT_EN_LM3 (1<<23) /* location monitor 3 mask */
259	# define UNIV_LINT_EN_LM2 (1<<22) /* location monitor 2 mask */
260	# define UNIV_LINT_EN_LM1 (1<<21) /* location monitor 1 mask */
261	# define UNIV_LINT_EN_LM0 (1<<20) /* location monitor 0 mask */
262	# define UNIV_LINT_EN_MBOX3 (1<<19) /* mailbox 3 mask */
263	# define UNIV_LINT_EN_MBOX2 (1<<18) /* mailbox 2 mask */
264	# define UNIV_LINT_EN_MBOX1 (1<<17) /* mailbox 1 mask */
265	# define UNIV_LINT_EN_MBOX0 (1<<16) /* mailbox 0 mask */
266	# define UNIV_LINT_EN_ACFAIL (1<<15) /* ACFAIL irq mask */
267	# define UNIV_LINT_EN_SYSFAIL (1<<14) /* SYSFAIL irq mask */
268	# define UNIV_LINT_EN_SW_INT (1<<13) /* PCI (local) software irq */
269	# define UNIV_LINT_EN_SW_IACK (1<<12) /* VME software IACK mask */
270	# define UNIV_LINT_EN_VERR (1<<10) /* PCI VERR irq mask */
271	# define UNIV_LINT_EN_LERR (1<<9) /* PCI LERR irq mask */
272	# define UNIV_LINT_EN_DMA (1<<8) /* PCI DMA irq mask */
273	# define UNIV_LINT_EN_VIRQ7 (1<<7) /* VIRQ7 mask (universe does IACK automatically) */
274	# define UNIV_LINT_EN_VIRQ6 (1<<6) /* VIRQ6 mask */
275	# define UNIV_LINT_EN_VIRQ5 (1<<5) /* VIRQ5 mask */
276	# define UNIV_LINT_EN_VIRQ4 (1<<4) /* VIRQ4 mask */
277	# define UNIV_LINT_EN_VIRQ3 (1<<3) /* VIRQ3 mask */
278	# define UNIV_LINT_EN_VIRQ2 (1<<2) /* VIRQ2 mask */
279	# define UNIV_LINT_EN_VIRQ1 (1<<1) /* VIRQ1 mask */
280	# define UNIV_LINT_EN_VOWN (1<<0) /* VOWN mask */
281
282	/* PCI (local) interrupt status register */
283	#define UNIV_REGOFF_LINT_STAT 0x304
284	# define UNIV_LINT_STAT_LM3 (1<<23) /* location monitor 3 status */
285	# define UNIV_LINT_STAT_LM2 (1<<22) /* location monitor 2 status */
286	# define UNIV_LINT_STAT_LM1 (1<<21) /* location monitor 1 status */
287	# define UNIV_LINT_STAT_LM0 (1<<20) /* location monitor 0 status */
288	# define UNIV_LINT_STAT_MBOX3 (1<<19) /* mailbox 3 status */
289	# define UNIV_LINT_STAT_MBOX2 (1<<18) /* mailbox 2 status */
290	# define UNIV_LINT_STAT_MBOX1 (1<<17) /* mailbox 1 status */
291	# define UNIV_LINT_STAT_MBOX0 (1<<16) /* mailbox 0 status */
292	# define UNIV_LINT_STAT_ACFAIL (1<<15) /* ACFAIL irq status */
293	# define UNIV_LINT_STAT_SYSFAIL (1<<14) /* SYSFAIL irq status */
294	# define UNIV_LINT_STAT_SW_INT (1<<13) /* PCI (local) software irq */
295	# define UNIV_LINT_STAT_SW_IACK (1<<12) /* VME software IACK status */
296	# define UNIV_LINT_STAT_VERR (1<<10) /* PCI VERR irq status */
297	# define UNIV_LINT_STAT_LERR (1<<9) /* PCI LERR irq status */
298	# define UNIV_LINT_STAT_DMA (1<<8) /* PCI DMA irq status */
299	# define UNIV_LINT_STAT_VIRQ7 (1<<7) /* VIRQ7 status */
300	# define UNIV_LINT_STAT_VIRQ6 (1<<6) /* VIRQ6 status */
301	# define UNIV_LINT_STAT_VIRQ5 (1<<5) /* VIRQ5 status */
302	# define UNIV_LINT_STAT_VIRQ4 (1<<4) /* VIRQ4 status */
303	# define UNIV_LINT_STAT_VIRQ3 (1<<3) /* VIRQ3 status */
304	# define UNIV_LINT_STAT_VIRQ2 (1<<2) /* VIRQ2 status */
305	# define UNIV_LINT_STAT_VIRQ1 (1<<1) /* VIRQ1 status */
306	# define UNIV_LINT_STAT_VOWN (1<<0) /* VOWN status */
307	# define UNIV_LINT_STAT_CLR (0xfff7ff)/* Clear all status bits */
308
309	/* PCI (local) interrupt map 0 register */
310	#define UNIV_REGOFF_LINT_MAP0 0x308 /* mapping of VME IRQ sources to PCI irqs */
311	# define UNIV_LINT_MAP0_VIRQ7(lint) (((lint)&0x7)<<(7*4))
312	# define UNIV_LINT_MAP0_VIRQ6(lint) (((lint)&0x7)<<(6*4))
313	# define UNIV_LINT_MAP0_VIRQ5(lint) (((lint)&0x7)<<(5*4))
314	# define UNIV_LINT_MAP0_VIRQ4(lint) (((lint)&0x7)<<(4*4))
315	# define UNIV_LINT_MAP0_VIRQ3(lint) (((lint)&0x7)<<(3*4))
316	# define UNIV_LINT_MAP0_VIRQ2(lint) (((lint)&0x7)<<(2*4))
317	# define UNIV_LINT_MAP0_VIRQ1(lint) (((lint)&0x7)<<(1*4))
318	# define UNIV_LINT_MAP0_VOWN(lint) (((lint)&0x7)<<(0*4))
319
320	#define UNIV_REGOFF_LINT_MAP1 0x30c /* mapping of internal / VME IRQ sources to PCI irqs */
321	# define UNIV_LINT_MAP1_ACFAIL(lint) (((lint)&0x7)<<(7*4))
322	# define UNIV_LINT_MAP1_SYSFAIL(lint) (((lint)&0x7)<<(6*4))
323	# define UNIV_LINT_MAP1_SW_INT(lint) (((lint)&0x7)<<(5*4))
324	# define UNIV_LINT_MAP1_SW_IACK(lint) (((lint)&0x7)<<(4*4))
325	# define UNIV_LINT_MAP1_VERR(lint) (((lint)&0x7)<<(2*4))
326	# define UNIV_LINT_MAP1_LERR(lint) (((lint)&0x7)<<(1*4))
327	# define UNIV_LINT_MAP1_DMA(lint) (((lint)&0x7)<<(0*4))
328
329	/* enabling of generation of VME bus IRQs, TODO */
330	#define UNIV_REGOFF_VINT_EN 0x310
331	# define UNIV_VINT_EN_DISABLE_ALL 0
332	# define UNIV_VINT_EN_SWINT (1<<12)
333	# define UNIV_VINT_EN_SWINT_LVL(l) (1<<(((l)&7)+24)) /* universe II only */
334
335
336	/* status of generation of VME bus IRQs */
337	#define UNIV_REGOFF_VINT_STAT 0x314
338	# define UNIV_VINT_STAT_LINT(lint) (1<<((lint)&7))
339	# define UNIV_VINT_STAT_LINT_MASK (0xff)
340	# define UNIV_VINT_STAT_CLR (0xfe0f17ff)
341	# define UNIV_VINT_STAT_SWINT(l) (1<<(((l)&7)+24))
342
343	#define UNIV_REGOFF_VINT_MAP0 0x318 /* VME destination of PCI IRQ source, TODO */
344
345	#define UNIV_REGOFF_VINT_MAP1 0x31c /* VME destination of PCI IRQ source, TODO */
346	# define UNIV_VINT_MAP1_SWINT(level) (((level)&0x7)<<16)
347
348	/* NOTE: The universe seems to always set LSB (which has a special purpose in
349	* the STATID register: enable raising a SW_INT on IACK) on the
350	* vector it puts out on the bus...
351	*/
352	#define UNIV_REGOFF_VINT_STATID 0x320 /* our status/id response to IACK, TODO */
353	# define UNIV_VINT_STATID(id) ((id)<<24)
354
355	#define UNIV_REGOFF_VIRQ1_STATID 0x324 /* status/id of VME IRQ level 1 */
356	#define UNIV_REGOFF_VIRQ2_STATID 0x328 /* status/id of VME IRQ level 2 */
357	#define UNIV_REGOFF_VIRQ3_STATID 0x32c /* status/id of VME IRQ level 3 */
358	#define UNIV_REGOFF_VIRQ4_STATID 0x330 /* status/id of VME IRQ level 4 */
359	#define UNIV_REGOFF_VIRQ5_STATID 0x334 /* status/id of VME IRQ level 5 */
360	#define UNIV_REGOFF_VIRQ6_STATID 0x338 /* status/id of VME IRQ level 6 */
361	#define UNIV_REGOFF_VIRQ7_STATID 0x33c /* status/id of VME IRQ level 7 */
362	# define UNIV_VIRQ_ERR (1<<8) /* set if universe encountered a bus error when doing IACK */
363	# define UNIV_VIRQ_STATID_MASK (0xff)
364
365	#define UNIV_REGOFF_LINT_MAP2 0x340 /* mapping of internal sources to PCI irqs */
366	# define UNIV_LINT_MAP2_LM3(lint) (((lint)&0x7)<<74) / location monitor 3 */
367	# define UNIV_LINT_MAP2_LM2(lint) (((lint)&0x7)<<64) / location monitor 2 */
368	# define UNIV_LINT_MAP2_LM1(lint) (((lint)&0x7)<<54) / location monitor 1 */
369	# define UNIV_LINT_MAP2_LM0(lint) (((lint)&0x7)<<44) / location monitor 0 */
370	# define UNIV_LINT_MAP2_MBOX3(lint) (((lint)&0x7)<<34) / mailbox 3 */
371	# define UNIV_LINT_MAP2_MBOX2(lint) (((lint)&0x7)<<24) / mailbox 2 */
372	# define UNIV_LINT_MAP2_MBOX1(lint) (((lint)&0x7)<<14) / mailbox 1 */
373	# define UNIV_LINT_MAP2_MBOX0(lint) (((lint)&0x7)<<04) / mailbox 0 */
374
375	#define UNIV_REGOFF_VINT_MAP2 0x344 /* mapping of internal sources to VME irqs */
376	# define UNIV_VINT_MAP2_MBOX3(vint) (((vint)&0x7)<<34) / mailbox 3 */
377	# define UNIV_VINT_MAP2_MBOX2(vint) (((vint)&0x7)<<24) / mailbox 2 */
378	# define UNIV_VINT_MAP2_MBOX1(vint) (((vint)&0x7)<<14) / mailbox 1 */
379	# define UNIV_VINT_MAP2_MBOX0(vint) (((vint)&0x7)<<04) / mailbox 0 */
380
381	#define UNIV_REGOFF_MBOX0 0x348 /* mailbox 0 */
382	#define UNIV_REGOFF_MBOX1 0x34c /* mailbox 1 */
383	#define UNIV_REGOFF_MBOX2 0x350 /* mailbox 2 */
384	#define UNIV_REGOFF_MBOX3 0x354 /* mailbox 3 */
385
386	#define UNIV_REGOFF_SEMA0 0x358 /* semaphore 0 */
387	#define UNIV_REGOFF_SEMA1 0x35c /* semaphore 0 */
388	/* TODO define semaphore register bits */
389
390	#define UNIV_REGOFF_MAST_CTL 0x400 /* master control register */
391	# define UNIV_MAST_CTL_MAXRTRY(val) (((val)&0xf)<<74) / max # of pci master retries */
392	# define UNIV_MAST_CTL_PWON(val) (((val)&0xf)<<64) / posted write xfer count */
393	# define UNIV_MAST_CTL_VRL(val) (((val)&0x3)<<22) /* VME bus request level */
394	# define UNIV_MAST_CTL_VRM (1<<21) /* bus request mode (demand = 0, fair = 1) */
395	# define UNIV_MAST_CTL_VREL (1<<20) /* bus release mode (when done = 0, on request = 1) */
396	# define UNIV_MAST_CTL_VOWN (1<<19) /* bus ownership (release = 0, acquire/hold = 1) */
397	# define UNIV_MAST_CTL_VOWN_ACK (1<<18) /* bus ownership (not owned = 0, acquired/held = 1) */
398	# define UNIV_MAST_CTL_PABS(val) (((val)&0x3)<<34) / PCI aligned burst size (32,64,128 byte / 0x3 is reserved) */
399	# define UNIV_MAST_CTL_BUS_NO(val) (((val)&0xff)<<04) / PCI bus number */
400
401	#define UNIV_REGOFF_MISC_CTL 0x404 /* misc control register */
402	# define UNIV_MISC_CTL_VBTO(val) (((val)&0x7)<<74) / VME bus timeout (0=disable, 162^(val-1) us) /
403	# define UNIV_MISC_CTL_VARB (1<<26) /* VME bus arbitration mode (0=round robin, 1= priority) */
404	# define UNIV_MISC_CTL_VARBTO(val) (((val)&0x3)<<64) / arbitration time out: disable, 16us, 256us, reserved */
405	# define UNIV_MISC_CTL_SW_LRST (1<<23) /* software PCI reset */
406	# define UNIV_MISC_CTL_SW_SYSRST (1<<22) /* software VME reset */
407	# define UNIV_MISC_CTL_BI (1<<20) /* BI mode */
408	# define UNIV_MISC_CTL_ENGBI (1<<19) /* enable global BI mode initiator */
409	# define UNIV_MISC_CTL_SYSCON (1<<17) /* (R/W) 1:universe is system controller */
410	# define UNIV_MISC_CTL_V64AUTO (1<<16) /* (R/W) 1:initiate VME64 auto id slave participation */
411
412	/* U2SPEC described in VGM manual */
413	/* NOTE: the Joerger vtr10012_8 needs the timing to be tweaked!!!! READt27 must be _no_delay_
414	*/
415	#define UNIV_REGOFF_U2SPEC 0x4fc
416	# define UNIV_U2SPEC_DTKFLTR (1<<12) /* DTAck filter: 0: slow, better filter; 1: fast, poorer filter */
417	# define UNIV_U2SPEC_MASt11 (1<<10) /* Master parameter t11 (DS hi time during BLT and MBLTs) */
418	# define UNIV_U2SPEC_READt27_DEFAULT (0<<8) /* VME master parameter t27: (latch data after DTAck + 25ns) */
419	# define UNIV_U2SPEC_READt27_FAST (1<<8) /* VME master parameter t27: (latch data faster than 25ns) */
420	# define UNIV_U2SPEC_READt27_NODELAY (2<<8) /* VME master parameter t27: (latch data without any delay) */
421	# define UNIV_U2SPEC_POSt28_FAST (1<<2) /* VME slave parameter t28: (faster time of DS to DTAck for posted write) */
422	# define UNIV_U2SPEC_PREt28_FAST (1<<0) /* VME slave parameter t28: (faster time of DS to DTAck for prefetch read) */
423
424	/* Location Monitor control register */
425	#define UNIV_REGOFF_LM_CTL 0xf64
426	# define UNIV_LM_CTL_EN (1<<31) /* image enable */
427	# define UNIV_LM_CTL_PGM (1<<23) /* program AM */
428	# define UNIV_LM_CTL_DATA (1<<22) /* data AM */
429	# define UNIV_LM_CTL_SUPER (1<<21) /* supervisor AM */
430	# define UNIV_LM_CTL_USER (1<<20) /* user AM */
431	# define UNIV_LM_CTL_VAS_A16 (0<<16) /* A16 */
432	# define UNIV_LM_CTL_VAS_A24 (1<<16) /* A16 */
433	# define UNIV_LM_CTL_VAS_A32 (2<<16) /* A16 */
434
435	/* Location Monitor base address */
436	#define UNIV_REGOFF_LM_BS 0xf68
437
438	/* VMEbus register access image control register */
439	#define UNIV_REGOFF_VRAI_CTL 0xf70
440	# define UNIV_VRAI_CTL_EN (1<<31) /* image enable */
441	# define UNIV_VRAI_CTL_PGM (1<<23) /* program AM */
442	# define UNIV_VRAI_CTL_DATA (1<<22) /* data AM */
443	# define UNIV_VRAI_CTL_SUPER (1<<21) /* supervisor AM */
444	# define UNIV_VRAI_CTL_USER (1<<20) /* user AM */
445	# define UNIV_VRAI_CTL_VAS_A16 (0<<16) /* A16 */
446	# define UNIV_VRAI_CTL_VAS_A24 (1<<16) /* A14 */
447	# define UNIV_VRAI_CTL_VAS_A32 (2<<16) /* A32 */
448	# define UNIV_VRAI_CTL_VAS_MSK (3<<16)
449
450	/* VMEbus register acces image base address register */
451	#define UNIV_REGOFF_VRAI_BS 0xf74
452
453	/* VMEbus CSR control register */
454	#define UNIV_REGOFF_VCSR_CTL 0xf80
455	# define UNIV_VCSR_CTL_EN (1<<31) /* image enable */
456	# define UNIV_VCSR_CTL_LAS_PCI_MEM (0<<0) /* pci mem space */
457	# define UNIV_VCSR_CTL_LAS_PCI_IO (1<<0) /* pci IO space */
458	# define UNIV_VCSR_CTL_LAS_PCI_CFG (2<<0) /* pci config space */
459
460	/* VMEbus CSR translation offset */
461	#define UNIV_REGOFF_VCSR_TO 0xf84
462
463	/* VMEbus AM code error log */
464	#define UNIV_REGOFF_V_AMERR 0xf88
465	# define UNIV_V_AMERR_AMERR(reg) (((reg)>>26)&0x3f) /* extract error log code */
466	# define UNIV_V_AMERR_IACK (1<<25) /* VMEbus IACK signal */
467	# define UNIV_V_AMERR_M_ERR (1<<24) /* multiple errors occurred */
468	# define UNIV_V_AMERR_V_STAT (1<<23) /* log status valid (write 1 to clear) */
469
470	/* VMEbus address error log */
471	#define UNIV_REGOFF_VAERR 0xf8c /* address of fault address (if MERR_V_STAT valid) */
472
473	/* VMEbus CSR bit clear register */
474	#define UNIV_REGOFF_VCSR_CLR 0xff4
475	# define UNIV_VCSR_CLR_RESET (1<<31) /* read/negate LRST (can only be written from VME bus */
476	# define UNIV_VCSR_CLR_SYSFAIL (1<<30) /* read/negate SYSFAIL */
477	# define UNIV_VCSR_CLR_FAIL (1<<29) /* read: board has failed */
478
479	/* VMEbus CSR bit set register */
480	#define UNIV_REGOFF_VCSR_SET (0xff8)
481	# define UNIV_VCSR_SET_RESET (1<<31) /* read/assert LRST (can only be written from VME bus */
482	# define UNIV_VCSR_SET_SYSFAIL (1<<30) /* read/assert SYSFAIL */
483	# define UNIV_VCSR_SET_FAIL (1<<29) /* read: board has failed */
484
485	/* VMEbus CSR base address register */
486	#define UNIV_REGOFF_VCSR_BS 0xffc
487	#define UNIV_VCSR_BS_MASK (0xf8000000)
488
489	/* offset of universe registers in VME-CSR slot */
490	#define UNIV_CSR_OFFSET 0x7f000
491
492	#ifdef __cplusplus
493	extern "C" {
494	#endif
495
496	/* base address and IRQ line of 1st universe bridge
497	* NOTE: vmeUniverseInit() must be called before
498	* these may be used.
499	*/
500	extern volatile LERegister *vmeUniverse0BaseAddr;
501	extern int vmeUniverse0PciIrqLine;
502
503
504	/* Initialize the driver */
505	int
506	vmeUniverseInit(void);
507
508	/* setup the universe chip, i.e. disable most of its
509	* mappings, reset interrupts etc.
510	*/
511	void
512	vmeUniverseReset(void);
513
514	/* avoid pulling stdio.h into this header.
515	* Applications that want a declaration of the
516	* following routines should
517	* #include <stdio.h>
518	* #define _VME_UNIVERSE_DECLARE_SHOW_ROUTINES
519	* #include <vmeUniverse.h>
520	*/
521	/* print the current configuration of all master ports to
522	* f (stderr if NULL)
523	*/
524	void
525	vmeUniverseMasterPortsShow(FILE *f);
526
527	/* print the current configuration of all slave ports to
528	* f (stderr if NULL)
529	*/
530	void
531	vmeUniverseSlavePortsShow(FILE *f);
532
533	/* disable all master or slave ports, respectively */
534	void
535	vmeUniverseDisableAllMasters(void);
536
537	void
538	vmeUniverseDisableAllSlaves(void);
539
540	/* configure a master port
541	*
542	* port: port number 0..3 (0..7 for a UniverseII)
543	*
544	* address_space: vxWorks compliant addressing mode identifier
545	* (see vme.h). The most important are:
546	* 0x0d - A32, Sup, Data
547	* 0x3d - A24, Sup, Data
548	* 0x2d - A16, Sup, Data
549	* additionally, the value 0 is accepted; it will
550	* disable this port.
551	* vme_address: address on the vme_bus of this port.
552	* local_address: address on the pci_bus of this port.
553	* length: size of this port.
554	*
555	* NOTE: the addresses and length parameters must be aligned on a
556	* 2^16 byte (0x10000) boundary, except for port 4 (only available
557	* on a UniverseII), where the alignment can be 4k (4096).
558	*
559	* RETURNS: 0 on success, -1 on failure. Error messages printed to stderr.
560	*/
561
562	int
563	vmeUniverseMasterPortCfg(
564	unsigned long port,
565	unsigned long address_space,
566	unsigned long vme_address,
567	unsigned long local_address,
568	unsigned long length);
569
570	/* translate an address through the bridge
571	*
572	* vmeUniverseXlateAddr(0,0,as,addr,&result)
573	* yields a VME a address that reflects
574	* a local memory location as seen from the VME bus through the universe
575	* VME slave.
576	*
577	* likewise does vmeUniverseXlateAddr(1,0,as,addr,&result)
578	* translate a VME bus addr (through the VME master) to the
579	* PCI side of the bridge.
580	*
581	* a valid address space modifier must be specified.
582	*
583	* The 'reverse' parameter may be used to find a reverse
584	* mapping, i.e. the pci address in a master window can be
585	* found if the respective vme address is known etc.
586	*
587	* RETURNS: translated address in pbusAdrs / plocalAdrs
588	*
589	* 0: success
590	* -1: address/modifier not found in any bridge port
591	* -2: invalid modifier
592	*/
593	int
594	vmeUniverseXlateAddr(
595	int master, /* look in the master windows */
596	int reverse, /* reverse mapping; for masters: map local to VME */
597	unsigned long as, /* address space */
598	unsigned long addr, /* address to look up */
599	unsigned long paOut/ where to put result */
600	);
601
602	/* configure a VME slave (PCI master) port */
603	int
604	vmeUniverseSlavePortCfg(
605	unsigned long port,
606	unsigned long address_space,
607	unsigned long vme_address,
608	unsigned long local_address,
609	unsigned long length);
610
611	/**** NOTE: USE OF vmeUniverseStartDMA IS DEPRECATED *******
612	**** USE API IN VMEDMA.h/vmeUniverseDMA.h INSTEAD *******/
613
614	/* start a (direct, not linked) DMA transfer
615	*
616	* NOTE: DCTL and DGCS must be set up
617	* prior to calling this routine
618	*/
619	int
620	vmeUniverseStartDMA(
621	unsigned long local_addr,
622	unsigned long vme_addr,
623	unsigned long count); /* DEPRECATED */
624
625	int
626	vmeUniverseStartDMAXX(
627	volatile LERegister *ubase,
628	unsigned long local_addr,
629	unsigned long vme_addr,
630	unsigned long count); /* DEPRECATED */
631
632
633	/* read a register in PCI memory space
634	* (offset being one of the declared constants)
635	*/
636	unsigned long
637	vmeUniverseReadReg(unsigned long offset);
638
639	/* write a register in PCI memory space */
640	void
641	vmeUniverseWriteReg(unsigned long value, unsigned long offset);
642
643	/* convert an array of unsigned long values to LE (as needed
644	* when the universe reads e.g. DMA descriptors from PCI)
645	*/
646	void
647	vmeUniverseCvtToLE(unsigned long *ptr, unsigned long num);
648
649	/* reset the VME bus */
650	void
651	vmeUniverseResetBus(void);
652
653	/* The ...XX routines take the universe base address as an additional
654	* argument - this allows for programming secondary devices.
655	*/
656
657	unsigned long
658	vmeUniverseReadRegXX(volatile LERegister *ubase, unsigned long offset);
659
660	void
661	vmeUniverseWriteRegXX(volatile LERegister *ubase, unsigned long value, unsigned long offset);
662
663	int
664	vmeUniverseXlateAddrXX(
665	volatile LERegister *ubase,
666	int master,
667	int reverse,
668	unsigned long as,
669	unsigned long addr,
670	unsigned long *paOut
671	);
672
673	int
674	vmeUniverseMasterPortCfgXX(
675	volatile LERegister *ubase,
676	unsigned long port,
677	unsigned long address_space,
678	unsigned long vme_address,
679	unsigned long local_address,
680	unsigned long length);
681
682	int
683	vmeUniverseSlavePortCfgXX(
684	volatile LERegister *ubase,
685	unsigned long port,
686	unsigned long address_space,
687	unsigned long vme_address,
688	unsigned long local_address,
689	unsigned long length);
690
691	void
692	vmeUniverseDisableAllMastersXX(volatile LERegister *ubase);
693
694	void
695	vmeUniverseDisableAllSlavesXX(volatile LERegister *ubase);
696
697	/* print the current configuration of all master ports to
698	* f (stderr if NULL)
699	*/
700	void
701	vmeUniverseMasterPortsShowXX(
702	volatile LERegister ubase,FILE f);
703
704	/* print the current configuration of all slave ports to
705	* f (stderr if NULL)
706	*/
707	void
708	vmeUniverseSlavePortsShowXX(
709	volatile LERegister ubase,FILE f);
710
711	/* Raise a VME Interrupt at 'level' and respond with 'vector' to a
712	* handler on the VME bus. (The handler could be a different board
713	* or the universe itself - [only works with universe II]).
714	*
715	* Note that you could install a interrupt handler at UNIV_VME_SW_IACK_INT_VEC
716	* to be notified of an IACK cycle having completed.
717	*
718	* This routine is mainly FOR TESTING.
719	*
720	* NOTES:
721	* - several registers are modified: the vector is written to VINT_STATID
722	* and (universe 1 chip only) the level is written to the SW_INT bits
723	* int VINT_MAP1
724	* - NO MUTUAL EXCLUSION PROTECTION (reads VINT_EN, modifies then writes back).
725	* If several users need access to VINT_EN and/or VINT_STATID (and VINT_MAP1
726	* on the universe 1) it is their responsibility to serialize access.
727	*
728	* Arguments:
729	* 'level': interrupt level, 1..7
730	* 'vector': vector number (0..254) that the universe puts on the bus in response to
731	* an IACK cycle. NOTE: the vector number must be even (hardware restriction
732	* of the universe -- it always clears the LSB when the interrupter is
733	* a software interrupt).
734	*
735	* RETURNS:
736	* 0: Success
737	* -1: Invalid argument (level not 1..7, vector odd or >= 256)
738	* -2: Interrupt 'level' already asserted (maybe nobody handles it).
739	* You can manually clear it be writing the respective bit in
740	* VINT_STAT. Make sure really nobody responds to avoid spurious
741	* interrupts (consult universe docs).
742	*/
743
744	int
745	vmeUniverseIntRaiseXX(volatile LERegister *base, int level, unsigned vector);
746
747	int
748	vmeUniverseIntRaise(int level, unsigned vector);
749
750	/* Map internal register block to VME.
751	*
752	* This routine is intended for BSP implementors. The registers can be
753	* made accessible from VME so that the interrupt handler can flush the
754	* bridge FIFO (see below). The preferred method is by accessing VME CSR,
755	* though, if these are mapped [and the BSP provides an outbound window].
756	* On the universe we can also disable posted writes in the 'ordinary'
757	* outbound windows.
758	*
759	* vme_base: VME address where the universe registers (4k) can be mapped.
760	* This VME address must fall into a range covered by
761	* any pre-configured outbound window.
762	* address_space: The desired VME address space.
763	* (all of SUP/USR/PGM/DATA are always accepted).
764	*
765	* See NOTES [vmeUniverseInstallIrqMgrAlt()] below for further information.
766	*
767	* RETURNS: 0 on success, nonzero on error. It is not possible (and results
768	* in a non-zero return code) to change the CRG VME address after
769	* initializing the interrupt manager as it uses the CRG.
770	*/
771	int
772	vmeUniverseMapCRGXX(volatile LERegister *base, unsigned long vme_base, unsigned long address_space);
773
774	int
775	vmeUniverseMapCRG(unsigned long vme_base, unsigned long address_space);
776
777
778	#ifdef __rtems__
779
780	/* VME Interrupt Handler functionality */
781
782	/* we dont use the current RTEMS/BSP interrupt API for the
783	* following reasons:
784	*
785	* - RTEMS/BSP API does not pass an argument to the ISR :-( :-(
786	* - no separate vector space for VME vectors. Some vectors would
787	* have to overlap with existing PCI/ISA vectors.
788	* - RTEMS/BSP API allocates a structure for every possible vector
789	* - the irq_on(), irq_off() functions add more bloat than helping.
790	* They are (currently) only used by the framework to disable
791	* interrupts at the device level before removing a handler
792	* and to enable interrupts after installing a handler.
793	* These operations may as well be done by the driver itself.
794	*
795	* Hence, we maintain our own (VME) handler table and hook our PCI
796	* handler into the standard RTEMS/BSP environment. Our handler then
797	* dispatches VME interrupts.
798	*/
799
800	typedef void (VmeUniverseISR) (void usrArg, unsigned long vector);
801
802	/* use these special vectors to connect a handler to the
803	* universe specific interrupts (such as "DMA done",
804	* VOWN, error irqs etc.)
805	* NOTE: The wrapper clears all status LINT bits (except
806	* for regular VME irqs). Also note that it is the user's
807	* responsibility to enable the necessary interrupts in
808	* LINT_EN
809	*
810	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
811	* DO NOT CHANGE THE ORDER OF THESE VECTORS - THE DRIVER
812	* DEPENDS ON IT
813	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
814	*
815	*/
816	#define UNIV_VOWN_INT_VEC 256
817	#define UNIV_DMA_INT_VEC 257
818	#define UNIV_LERR_INT_VEC 258
819	#define UNIV_VERR_INT_VEC 259
820	/* 260 is reserved */
821	#define UNIV_VME_SW_IACK_INT_VEC 261
822	#define UNIV_PCI_SW_INT_VEC 262
823	#define UNIV_SYSFAIL_INT_VEC 263
824	#define UNIV_ACFAIL_INT_VEC 264
825	#define UNIV_MBOX0_INT_VEC 265
826	#define UNIV_MBOX1_INT_VEC 266
827	#define UNIV_MBOX2_INT_VEC 267
828	#define UNIV_MBOX3_INT_VEC 268
829	#define UNIV_LM0_INT_VEC 269
830	#define UNIV_LM1_INT_VEC 270
831	#define UNIV_LM2_INT_VEC 271
832	#define UNIV_LM3_INT_VEC 272
833
834	#define UNIV_NUM_INT_VECS 273
835
836
837	/* install a handler for a VME vector
838	* RETURNS 0 on success, nonzero on failure.
839	*/
840	int
841	vmeUniverseInstallISR(unsigned long vector, VmeUniverseISR handler, void *usrArg);
842
843	/* remove a handler for a VME vector. The vector and usrArg parameters
844	* must match the respective parameters used when installing the handler.
845	* RETURNS 0 on success, nonzero on failure.
846	*/
847	int
848	vmeUniverseRemoveISR(unsigned long vector, VmeUniverseISR handler, void *usrArg);
849
850	/* query for the currently installed ISR and usr parameter at a given vector
851	* RETURNS: ISR or 0 (vector too big or no ISR installed)
852	*/
853	VmeUniverseISR
854	vmeUniverseISRGet(unsigned long vector, void **parg);
855
856	/* utility routines to enable/disable a VME IRQ level.
857	*
858	* To enable/disable the internal interrupt sources (special vectors above)
859	* pass a vector argument > 255.
860	*
861	* RETURNS 0 on success, nonzero on failure
862	*/
863	int
864	vmeUniverseIntEnable(unsigned int level);
865	int
866	vmeUniverseIntDisable(unsigned int level);
867
868	/* Check if an interrupt level or internal source is enabled:
869	*
870	* 'level': VME level 1..7 or internal special vector > 255
871	*
872	* RETURNS: value > 0 if interrupt is currently enabled,
873	* zero if interrupt is currently disabled,
874	* -1 on error (invalid argument).
875	*/
876	int
877	vmeUniverseIntIsEnabled(unsigned int level);
878
879
880	/* Change the routing of IRQ 'level' to 'pin'.
881	* If the BSP connects more than one of the eight
882	* physical interrupt lines from the universe to
883	* the board's PIC then you may change the physical
884	* line a given 'level' is using. By default,
885	* all 7 VME levels use the first wire (pin==0) and
886	* all internal sources use the (optional) second
887	* wire (pin==1).
888	* This feature is useful if you want to make use of
889	* different hardware priorities of the PIC. Let's
890	* say you want to give IRQ level 7 the highest priority.
891	* You could then give 'pin 0' a higher priority (at the
892	* PIC) and 'pin 1' a lower priority and issue.
893	*
894	* for ( i=1; i<7; i++ ) vmeUniverseIntRoute(i, 1);
895	*
896	* PARAMETERS:
897	* 'level' : VME interrupt level '1..7' or one of
898	* the internal sources. Pass the internal
899	* source's vector number (>=256).
900	* 'pin' : a value of 0 routes the requested IRQ to
901	* the first line registered with the manager
902	* (vmeIrqUnivOut parameter), a value of 1
903	* routes it to the alternate wire
904	* (specialIrqUnivOut)
905	* RETURNS: 0 on success, nonzero on error (invalid arguments)
906	*
907	* NOTES: - DONT change the universe 'map' registers
908	* directly. The driver caches routing internally.
909	* - support for the 'specialIrqUnivOut' wire is
910	* board dependent. If the board only provides
911	* a single physical wire from the universe to
912	* the PIC then the feature might not be available.
913	*/
914	int
915	vmeUniverseIntRoute(unsigned int level, unsigned int pin);
916
917	/* Loopback test of the VME interrupt subsystem.
918	* - installs ISRs on 'vector' and on UNIV_VME_SW_IACK_INT_VEC
919	* - asserts VME interrupt 'level'
920	* - waits for both interrupts: 'ordinary' VME interrupt of 'level' and
921	* IACK completion interrupt ('special' vector UNIV_VME_SW_IACK_INT_VEC).
922	*
923	* NOTES:
924	* - make sure no other handler responds to 'level'.
925	* - make sure no ISR is installed on both vectors yet.
926	* - ISRs installed by this routine are removed after completion.
927	* - no concurrent access protection of all involved resources
928	* (levels, vectors and registers [see vmeUniverseIntRaise()])
929	* is implemented.
930	* - this routine is intended for TESTING (when implementing new BSPs etc.).
931	* - one RTEMS message queue is temporarily used (created/deleted).
932	* - the universe 1 always yields a zero vector (VIRQx_STATID) in response
933	* to a self-generated VME interrupt. As a workaround, the routine
934	* only accepts a zero vector when running on a universe 1.
935	*
936	* RETURNS:
937	* 0: Success.
938	* -1: Invalid arguments.
939	* 1: Test failed (outstanding interrupts).
940	* rtems_status_code: Failed RTEMS directive.
941	*/
942	int
943	vmeUniverseIntLoopbackTst(int level, unsigned vector);
944
945
946	/* the universe interrupt handler is capable of routing all sorts of
947	* (VME) interrupts to 8 different lines (some of) which may be hooked up
948	* in a (board specific) way to a PIC.
949	*
950	* This driver only supports at most two lines. By default, it routes the
951	* 7 VME interrupts to the main line and optionally, it routes the 'special'
952	* interrupts generated by the universe itself (DMA done, VOWN etc.)
953	* to a second line. If no second line is available, all IRQs are routed
954	* to the main line.
955	*
956	* The routing of interrupts to the two lines can be modified (using
957	* the vmeUniverseIntRoute() call - see above - i.e., to make use of
958	* different hardware priorities of the two pins.
959	*
960	* Because the driver has no way to figure out which lines are actually
961	* wired to the PIC, this information has to be provided when installing
962	* the manager.
963	*
964	* Hence the manager sets up routing VME interrupts to 1 or 2 universe
965	* OUTPUTS. However, it must also be told to which PIC INPUTS they
966	* are wired.
967	* Optionally, the first PIC input line can be read from PCI config space
968	* but the second must be passed to this routine. Note that the info read
969	* from PCI config space is wrong for many boards!
970	*
971	* PARAMETERS:
972	* vmeIrqUnivOut: to which output pin (of the universe) should the 7
973	* VME irq levels be routed.
974	* vmeIrqPicLine: specifies to which PIC input the 'main' output is
975	* wired. If passed a value < 0, the driver reads this
976	* information from PCI config space ("IRQ line").
977	* specialIrqUnivOut: to which output pin (of the universe) should the
978	* internally irqs be routed. Use 'vmeIRQunivOut'
979	* if < 0.
980	* specialIrqPicLine: specifies to which PIC input the 'special' output
981	* pin is wired. The wiring of the 'vmeIRQunivOut' to
982	* the PIC is determined by reading PCI config space.
983	*
984	* RETURNS: 0 on success, -1 on failure.
985	*
986	*/
987
988	/* This routine is outside of the __INSIDE_RTEMS_BSP__ test for bwrds compatibility ONLY */
989	int
990	vmeUniverseInstallIrqMgr(int vmeIrqUnivOut,
991	int vmeIrqPicLine,
992	int specialIrqUnivOut,
993	int specialIrqPicLine);
994
995
996	#if defined(__INSIDE_RTEMS_BSP__)
997	#include <stdarg.h>
998
999	/* up to 4 universe outputs are now supported by this alternate
1000	* entry point.
1001	* Terminate the vararg list (uni_pin/pic_pin pairs) with a
1002	* '-1' uni_pin.
1003	* E.g., the old interface is now just a wrapper to
1004	* vmeUniverseInstallIrqMgrAlt(0, vmeUnivOut, vmePicLint, specUnivOut, specPicLine, -1);
1005	*
1006	* The 'IRQ_MGR_SHARED' flag uses the BSP_install_rtems_shared_irq_handler()
1007	* API. CAVEAT: shared interrupts need RTEMS workspace, i.e., the
1008	* VME interrupt manager can only be installed after workspace is initialized
1009	* if 'shared' is nonzero (i.e., not from bspstart()).
1010	*
1011	* If 'PW_WORKAROUND' flag is set then the interrupt manager will try to
1012	* find a way to access the control registers from VME so that the universe's
1013	* posted write FIFO can be flushed after the user ISR returns:
1014	*
1015	* The installation routine looks first for CSR registers in CSR space (this
1016	* requires:
1017	* - a VME64 crate with autoid or geographical addressing
1018	* - the firmware or BSP to figure out the slot number and program the CSR base
1019	* in the universe.
1020	* - the BSP to open an outbound window to CSR space.
1021	*
1022	* If CSR registers cannot be found then the installation routine looks for CRG registers:
1023	* - BSP must map CRG on VME
1024	* - CRG must be visible in outbound window
1025	* CAVEAT: multiple boards with same BSP on single backplane must not map their CRG
1026	* to the same address!
1027	*/
1028
1029	#define VMEUNIVERSE_IRQ_MGR_FLAG_SHARED 1 /* use shared interrupts */
1030	#define VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND 2 /* use shared interrupts */
1031
1032	int
1033	vmeUniverseInstallIrqMgrAlt(int flags, int uni_pin0, int pic_pin0, ...);
1034
1035	int
1036	vmeUniverseInstallIrqMgrVa(int flags, int uni_pin0, int pic_pin0, va_list ap);
1037
1038	#endif /* __INSIDE_RTEMS_BSP__ */
1039	#endif /* __rtems__ */
1040
1041	#ifdef __cplusplus
1042	}
1043	#endif
1044
1045	#endif

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