1 | /* |
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2 | * RTEMS support for MPC83xx |
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3 | * |
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4 | * This file declares the MPC83xx TSEC networking driver. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2007 embedded brains GmbH. All rights reserved. |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #ifndef LIBCPU_POWERPC_TSEC_H |
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16 | #define LIBCPU_POWERPC_TSEC_H |
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17 | |
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18 | #include <stdint.h> |
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19 | |
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20 | #include <bsp/irq.h> |
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21 | #include <bsp/tsec-config.h> |
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22 | |
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23 | #ifdef __cplusplus |
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24 | extern "C" { |
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25 | #endif /* __cplusplus */ |
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26 | |
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27 | /* |
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28 | * this enumeration defines the index |
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29 | * of a given rmon mib counter |
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30 | * in the tsec_rmon_mib array |
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31 | */ |
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32 | typedef enum { |
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33 | /* TSEC1 Transmit and Receive Counters */ |
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34 | TSEC_RMON_TR64, /* 0x2_4680 Transmit and receive 64-byte frame counter register R/W 0x0000_0000 15.5.3.7.1/15-60 */ |
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35 | TSEC_RMON_TR127, /* 0x2_4684 Transmit and receive 65- to 127-byte frame counter register R/W 0x0000_0000 15.5.3.7.2/15-61 */ |
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36 | TSEC_RMON_TR255, /* 0x2_4688 Transmit and receive 128- to 255-byte frame counter register R/W 0x0000_0000 15.5.3.7.3/15-61 */ |
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37 | TSEC_RMON_TR511, /* 0x2_468C Transmit and receive 256- to 511-byte frame counter register R/W 0x0000_0000 15.5.3.7.4/15-62 */ |
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38 | TSEC_RMON_TR1K, /* 0x2_4690 Transmit and receive 512- to 1023-byte frame counter register R/W 0x0000_0000 15.5.3.7.5/15-62 */ |
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39 | TSEC_RMON_TRMAX, /* 0x2_4694 Transmit and receive 1024- to 1518-byte frame counter register R/W 0x0000_0000 15.5.3.7.6/15-63 */ |
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40 | TSEC_RMON_TRMGV, /* 0x2_4698 Transmit and receive 1519- to 1522-byte good VLAN frame count register R/W 0x0000_0000 15.5.3.7.7/15-63 */ |
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41 | /* TSEC1 Receive Counters */ |
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42 | TSEC_RMON_RBYT, /* 0x2_469C Receive byte counter register R/W 0x0000_0000 15.5.3.7.8/15-64 */ |
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43 | TSEC_RMON_RPKT, /* 0x2_46A0 Receive packet counter register R/W 0x0000_0000 15.5.3.7.9/15-64 */ |
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44 | TSEC_RMON_RFCS, /* 0x2_46A4 Receive FCS error counter register R/W 0x0000_0000 15.5.3.7.10/15-65 */ |
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45 | TSEC_RMON_RMCA, /* 0x2_46A8 Receive multicast packet counter register R/W 0x0000_0000 15.5.3.7.11/15-65 */ |
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46 | TSEC_RMON_RBCA, /* 0x2_46AC Receive broadcast packet counter register R/W 0x0000_0000 15.5.3.7.12/15-66 */ |
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47 | TSEC_RMON_RXCF, /* 0x2_46B0 Receive control frame packet counter register R/W 0x0000_0000 15.5.3.7.13/15-66 */ |
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48 | TSEC_RMON_RXPF, /* 0x2_46B4 Receive PAUSE frame packet counter register R/W 0x0000_0000 15.5.3.7.14/15-67 */ |
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49 | TSEC_RMON_RXUO, /* 0x2_46B8 Receive unknown OP code counter register R/W 0x0000_0000 15.5.3.7.15/15-67 */ |
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50 | TSEC_RMON_RALN, /* 0x2_46BC Receive alignment error counter register R/W 0x0000_0000 15.5.3.7.16/15-68 */ |
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51 | TSEC_RMON_RFLR, /* 0x2_46C0 Receive frame length error counter register R/W 0x0000_0000 15.5.3.7.17/15-68 */ |
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52 | TSEC_RMON_RCDE, /* 0x2_46C4 Receive code error counter register R/W 0x0000_0000 15.5.3.7.18/15-69 */ |
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53 | TSEC_RMON_RCSE, /* 0x2_46C8 Receive carrier sense error counter register R/W 0x0000_0000 15.5.3.7.19/15-69 */ |
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54 | TSEC_RMON_RUND, /* 0x2_46CC Receive undersize packet counter register R/W 0x0000_0000 15.5.3.7.20/15-70 */ |
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55 | TSEC_RMON_ROVR, /* 0x2_46D0 Receive oversize packet counter register R/W 0x0000_0000 15.5.3.7.21/15-70 */ |
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56 | TSEC_RMON_RFRG, /* 0x2_46D4 Receive fragments counter register R/W 0x0000_0000 15.5.3.7.22/15-71 */ |
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57 | TSEC_RMON_RJBR, /* 0x2_46D8 Receive jabber counter register R/W 0x0000_0000 15.5.3.7.23/15-71 */ |
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58 | TSEC_RMON_RDRP, /* 0x2_46DC Receive drop register R/W 0x0000_0000 15.5.3.7.24/15-72 */ |
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59 | /* TSEC1 Transmit Counters */ |
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60 | TSEC_RMON_TBYT, /* 0x2_46E0 Transmit byte counter register R/W 0x0000_0000 15.5.3.7.25/15-72 */ |
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61 | TSEC_RMON_TPKT, /* 0x2_46E4 Transmit packet counter register R/W 0x0000_0000 15.5.3.7.26/15-73 */ |
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62 | TSEC_RMON_TMCA, /* 0x2_46E8 Transmit multicast packet counter register R/W 0x0000_0000 15.5.3.7.27/15-73 */ |
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63 | TSEC_RMON_TBCA, /* 0x2_46EC Transmit broadcast packet counter register R/W 0x0000_0000 15.5.3.7.28/15-74 */ |
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64 | TSEC_RMON_TXPF, /* 0x2_46F0 Transmit PAUSE control frame counter register R/W 0x0000_0000 15.5.3.7.29/15-74 */ |
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65 | TSEC_RMON_TDFR, /* 0x2_46F4 Transmit deferral packet counter register R/W 0x0000_0000 15.5.3.7.30/15-75 */ |
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66 | TSEC_RMON_TEDF, /* 0x2_46F8 Transmit excessive deferral packet counter register R/W 0x0000_0000 15.5.3.7.31/15-75 */ |
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67 | TSEC_RMON_TSCL, /* 0x2_46FC Transmit single collision packet counter register R/W 0x0000_0000 15.5.3.7.32/15-76 */ |
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68 | TSEC_RMON_TMCL, /* 0x2_4700 Transmit multiple collision packet counter register R/W 0x0000_0000 15.5.3.7.33/15-76 */ |
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69 | TSEC_RMON_TLCL, /* 0x2_4704 Transmit late collision packet counter register R/W 0x0000_0000 15.5.3.7.34/15-77 */ |
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70 | TSEC_RMON_TXCL, /* 0x2_4708 Transmit excessive collision packet counter register R/W 0x0000_0000 15.5.3.7.35/15-77 */ |
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71 | TSEC_RMON_TNCL, /* 0x2_470C Transmit total collision counter register R/W 0x0000_0000 15.5.3.7.36/15-78 */ |
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72 | TSEC_RESERVED1, /* 0x2_4710 Reserved, should be cleared R 0x0000_0000 */ |
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73 | TSEC_RMON_TDRP, /* 0x2_4714 Transmit drop frame counter register R/W 0x0000_0000 15.5.3.7.37/15-78 */ |
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74 | TSEC_RMON_TJBR, /* 0x2_4718 Transmit jabber frame counter register R/W 0x0000_0000 15.5.3.7.38/15-79 */ |
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75 | TSEC_RMON_TFCS, /* 0x2_471C Transmit FCS error counter register R/W 0x0000_0000 15.5.3.7.39/15-79 */ |
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76 | TSEC_RMON_TXCF, /* 0x2_4720 Transmit control frame counter register R/W 0x0000_0000 15.5.3.7.40/15-80 */ |
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77 | TSEC_RMON_TOVR, /* 0x2_4724 Transmit oversize frame counter register R/W 0x0000_0000 15.5.3.7.41/15-80 */ |
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78 | TSEC_RMON_TUND, /* 0x2_4728 Transmit undersize frame counter register R/W 0x0000_0000 15.5.3.7.42/15-81 */ |
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79 | TSEC_RMON_TFRG, /* 0x2_472C Transmit fragments frame counter register R/W 0x0000_0000 15.5.3.7.43/15-81 */ |
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80 | TSEC_RMON_CNT |
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81 | } tsec_rmon_idx; |
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82 | |
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83 | /* TSEC1/2 General Control and Status Registers */ |
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84 | typedef struct { |
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85 | uint8_t reserved0x2_4000[0x24010-0x24000]; /* 0x2_4000--0x2_400F Reserved, should be cleared */ |
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86 | uint32_t ievent; /* 0x2_4010 Interrupt event register R/W 0x0000_0000 15.5.3.1.1/15-19 */ |
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87 | uint32_t imask; /* 0x2_4014 Interrupt mask register R/W 0x0000_0000 15.5.3.1.2/15-22 */ |
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88 | uint32_t edis; /* 0x2_4018 Error disabled register R/W 0x0000_0000 15.5.3.1.3/15-24 */ |
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89 | uint8_t reserved0x2_401c[0x24020-0x2401c]; /* 0x2_401c--0x2_401f Reserved, should be cleared */ |
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90 | uint32_t ecntrl; /* 0x2_4020 Ethernet control register R/W 0x0000_0000 15.5.3.1.4/15-25 */ |
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91 | uint32_t minflr; /* 0x2_4024 Minimum frame length register R/W 0x0000_0040 15.5.3.1.5/15-26 */ |
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92 | uint32_t ptv; /* 0x2_4028 Pause time value register R/W 0x0000_0000 15.5.3.1.6/15-27 */ |
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93 | uint32_t dmactrl; /* 0x2_402C DMA control register R/W 0x0000_0000 15.5.3.1.7/15-28 */ |
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94 | uint32_t tbipa; /* 0x2_4030 TBI PHY address register R/W 0x0000_0000 15.5.3.1.8/15-29 */ |
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95 | uint8_t reserved0x2_4034[0x2408c-0x24034]; /* 0x2_4034--0x2_408b Reserved, should be cleared */ |
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96 | /* TSEC1 FIFO Control and Status Registers */ |
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97 | uint32_t fifo_tx_thr; /* 0x2_408C FIFO transmit threshold register R/W 0x0000_0100 15.5.3.2.1/15-30 */ |
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98 | uint8_t reserved0x2_4090[0x24094-0x24090]; /* 0x2_4090--0x2_4093 Reserved, should be cleared */ |
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99 | uint32_t fifo_tx_sp; /* 0x2_4094 FIFO transmit space available register R/W 0x0000_0010 15.5.3.2.2/15-31 */ |
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100 | uint32_t fifo_tx_starve; /* 0x2_4098 FIFO transmit starve register R/W 0x0000_0080 15.5.3.2.3/15-31 */ |
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101 | uint32_t fifo_tx_starve_shutoff; /* 0x2_409C FIFO transmit starve shutoff register R/W 0x0000_0100 15.5.3.2.4/15-32 */ |
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102 | uint8_t reserved0x2_40A0[0x24100-0x240A0]; /* 0x2_40A0--0x2_40ff Reserved, should be cleared */ |
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103 | /* TSEC1 Transmit Control and Status Registers */ |
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104 | uint32_t tctrl; /* 0x2_4100 Transmit control register R/W 0x0000_0000 15.5.3.3.1/15-33 */ |
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105 | uint32_t tstat; /* 0x2_4104 Transmit status register R/W 0x0000_0000 15.5.3.3.2/15-34 */ |
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106 | uint8_t reserved0x2_4108[0x24110-0x24108]; /* 0x2_4108 Reserved, should be cleared R 0x0000_0000 */ |
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107 | uint32_t txic; /* 0x2_4110 Transmit interrupt coalescing configuration register R/W 0x0000_0000 */ |
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108 | uint8_t reserved0x2_4114[0x24124-0x24114]; /* 0x2_4114--0x2_4120 Reserved, should be cleared */ |
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109 | uint32_t ctbptr; /* 0x2_4124 Current TxBD pointer register R 0x0000_0000 15.5.3.3.5/15-36 */ |
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110 | uint8_t reserved0x2_4128[0x24184-0x24128]; /* 0x2_4128--0x2_4180 Reserved, should be cleared */ |
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111 | uint32_t tbptr; /* 0x2_4184 TxBD pointer register R/W 0x0000_0000 15.5.3.3.6/15-36 */ |
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112 | uint8_t reserved0x2_4188[0x24204-0x24188]; /* 0x2_4188--0x2_4200 Reserved, should be cleared */ |
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113 | uint32_t tbase; /* 0x2_4204 TxBD base address register R/W 0x0000_0000 15.5.3.3.7/15-37 */ |
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114 | uint8_t reserved0x2_4208[0x242B0-0x24208]; /* 0x2_4208--0x2_42AC Reserved, should be cleared */ |
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115 | uint32_t ostbd; /* 0x2_42B0 Out-of-sequence TxBD register R/W 0x0800_0000 15.5.3.3.8/15-37 */ |
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116 | uint32_t ostbdp; /* 0x2_42B4 Out-of-sequence Tx data buffer pointer register R/W 0x0000_0000 15.5.3.3.9/15-39 */ |
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117 | uint8_t reserved0x2_42B8[0x24300-0x242B8]; /* 0x2_42B8--0x2_42FC Reserved, should be cleared */ |
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118 | /* TSEC1 Receive Control and Status Registers */ |
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119 | uint32_t rctrl; /* 0x2_4300 Receive control register R/W 0x0000_0000 15.5.3.4.1/15-40 */ |
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120 | uint32_t rstat; /* 0x2_4304 Receive status register R/W 0x0000_0000 15.5.3.4.2/15-41 */ |
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121 | uint8_t reserved0x2_4308[0x2430C-0x24308]; /* 0x2_4308 Reserved, should be cleared R 0x0000_0000 */ |
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122 | uint32_t rbdlen; /* 0x2_430C RxBD data length register R 0x0000_0000 15.5.3.4.3/15-41 */ |
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123 | uint32_t rxic; /* 0x2_4310 Receive interrupt coalescing configuration register R/W 0x0000_0000 15.5.3.4.4/15-42 */ |
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124 | uint8_t reserved0x2_4314[0x24324-0x24314]; /* 0x2_4314--0x2_4320 Reserved, should be cleared */ |
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125 | uint32_t crbptr; /* 0x2_4324 Current RxBD pointer register R 0x0000_0000 15.5.3.4.5/15-43 */ |
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126 | uint8_t reserved0x2_4328[0x24340-0x24328]; /* 0x2_4328--0x2_433C Reserved, should be cleared */ |
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127 | uint32_t mrblr; /* 0x2_4340 Maximum receive buffer length register R/W 0x0000_0000 15.5.3.4.6/15-43 */ |
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128 | uint8_t reserved0x2_4344[0x24384-0x24344]; /* 0x2_4344--0x2_4380 Reserved, should be cleared */ |
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129 | uint32_t rbptr; /* 0x2_4384 RxBD pointer register R/W 0x0000_0000 15.5.3.4.7/15-44 */ |
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130 | uint8_t reserved0x2_4388[0x24404-0x24388]; /* 0x2_4388--0x2_4400 Reserved, should be cleared */ |
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131 | uint32_t rbase; /* 0x2_4404 RxBD base address register R/W 0x0000_0000 15.5.3.4.8/15-44 */ |
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132 | uint8_t reserved0x2_4408[0x24500-0x24408]; /* 0x2_4408--0x2_44FC Reserved, should be cleared */ |
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133 | /* TSEC1 MAC Registers */ |
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134 | uint32_t maccfg1; /* 0x2_4500 MAC configuration register 1 R/W, R 0x0000_0000 15.5.3.6.1/15-48 */ |
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135 | uint32_t maccfg2; /* 0x2_4504 MAC configuration register 2 R/W 0x0000_7000 15.5.3.6.2/15-49 */ |
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136 | uint32_t ipgifg; /* 0x2_4508 Inter-packet gap/inter-frame gap register R/W 0x4060_5060 15.5.3.6.3/15-51 */ |
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137 | uint32_t hafdup; /* 0x2_450C Half-duplex register R/W 0x00A1_F037 15.5.3.6.4/15-52 */ |
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138 | uint32_t maxfrm; /* 0x2_4510 Maximum frame length register R/W 0x0000_0600 15.5.3.6.5/15-53 */ |
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139 | uint8_t reserved0x2_4514[0x24520-0x24514]; /* 0x2_4514--0x2_451C Reserved, should be cleared */ |
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140 | uint32_t miimcfg; /* 0x2_4520 MII management configuration register R/W 0x0000_0000 15.5.3.6.6/15-53 */ |
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141 | uint32_t miimcom; /* 0x2_4524 MII management command register R/W 0x0000_0000 15.5.3.6.7/15-54 */ |
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142 | uint32_t miimadd; /* 0x2_4528 MII management address register R/W 0x0000_0000 15.5.3.6.8/15-55 */ |
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143 | uint32_t miimcon; /* 0x2_452C MII management control register W 0x0000_0000 15.5.3.6.9/15-56 */ |
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144 | uint32_t miimstat; /* 0x2_4530 MII management status register R 0x0000_0000 15.5.3.6.10/15-56 */ |
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145 | uint32_t miimind; /* 0x2_4534 MII management indicator register R 0x0000_0000 15.5.3.6.11/15-57 */ |
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146 | uint8_t reserved0x2_4538[0x2453c-0x24538]; /* 0x2_4538 Reserved, should be cleared $ $ */ |
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147 | uint32_t ifstat; /* 0x2_453C Interface status register Special 0x0000_0001 15.5.3.6.12/15-58 */ |
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148 | uint32_t macstnaddr[2]; /* 0x2_4540 Station address register, part 1/2 R/W 0x0000_0000 15.5.3.6.13/15-58 */ |
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149 | uint8_t reserved0x2_4548[0x24680-0x24548]; /* 0x2_4548--0x2_467C Reserved, should be cleared */ |
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150 | |
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151 | /* TSEC1 RMON MIB Registers */ |
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152 | uint32_t rmon_mib[TSEC_RMON_CNT]; |
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153 | |
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154 | /* TSEC1 General Registers */ |
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155 | uint32_t car[2]; /* 0x2_4730 Carry register one/two register R 0x0000_0000 15.5.3.7.44/15-82 */ |
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156 | uint32_t cam[2]; /* 0x2_4738 Carry register one/two mask register R/W 0xFE01_FFFF 15.5.3.7.46/15-85 */ |
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157 | uint8_t reserved0x2_4740[0x24800-0x24740]; /* 0x2_4740--0x2_47FC Reserved, should be cleared */ |
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158 | |
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159 | /* TSEC1 Hash Function Registers */ |
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160 | uint32_t iaddr[8]; /* 0x2_4800 Individual address register 0-7 R/W 0x0000_0000 15.5.3.8.1/15-87 */ |
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161 | uint8_t reserved0x2_4820[0x24880-0x24820]; /* 0x2_4820--0x2_487C Reserved, should be cleared */ |
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162 | uint32_t gaddr[8]; /* 0x2_4880 Group address register 0-7 R/W 0x0000_0000 15.5.3.8.2/15-88 */ |
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163 | uint8_t reserved0x2_48A0[0x24B00-0x248A0]; /* 0x2_48A0--0x2_4AFF Reserved, should be cleared */ |
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164 | |
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165 | /* TSEC1 Attribute Registers */ |
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166 | uint8_t reserved0x2_4B00[0x24BF8-0x24B00]; /* 0x2_4B00--0x2_4BF4 Reserved, should be cleared */ |
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167 | uint32_t attr; /* 0x2_4BF8 Attribute register R 0x0000_0000 */ |
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168 | uint32_t attreli; /* 0x2_4BFC Attribute extract length and extract index register R/W 0x0000_0000 */ |
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169 | uint8_t reserved0x2_4C00[0x25000-0x24C00]; /* 0x2_4C00--0x2_4FFF Reserved, should be cleared */ |
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170 | } tsec_registers; |
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171 | |
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172 | /* |
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173 | * TSEC IEVENT/IMASK bit definitions |
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174 | */ |
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175 | #define TSEC_IEVENT_BABR (1<<(31- 0)) |
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176 | #define TSEC_IEVENT_RXC (1<<(31- 1)) |
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177 | #define TSEC_IEVENT_BSY (1<<(31- 2)) |
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178 | #define TSEC_IEVENT_EBERR (1<<(31- 3)) |
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179 | #define TSEC_IEVENT_MSRO (1<<(31- 5)) |
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180 | #define TSEC_IEVENT_GTSC (1<<(31- 6)) |
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181 | #define TSEC_IEVENT_BABT (1<<(31- 7)) |
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182 | #define TSEC_IEVENT_TXC (1<<(31- 8)) |
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183 | #define TSEC_IEVENT_TXE (1<<(31- 9)) |
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184 | #define TSEC_IEVENT_TXB (1<<(31-10)) |
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185 | #define TSEC_IEVENT_TXF (1<<(31-11)) |
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186 | #define TSEC_IEVENT_LC (1<<(31-13)) |
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187 | #define TSEC_IEVENT_CRL_XDA (1<<(31-14)) |
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188 | #define TSEC_IEVENT_XFUN (1<<(31-15)) |
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189 | #define TSEC_IEVENT_RXB (1<<(31-16)) |
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190 | #define TSEC_IEVENT_MMRD (1<<(31-21)) |
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191 | #define TSEC_IEVENT_MMWR (1<<(31-22)) |
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192 | #define TSEC_IEVENT_GRSC (1<<(31-23)) |
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193 | #define TSEC_IEVENT_RXF (1<<(31-24)) |
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194 | |
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195 | /* |
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196 | * TSEC DMACTRL bit definitions |
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197 | */ |
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198 | #define TSEC_DMACTL_TDSEN (1<<(31-24)) |
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199 | #define TSEC_DMACTL_TBDSEN (1<<(31-25)) |
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200 | #define TSEC_DMACTL_GRS (1<<(31-27)) |
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201 | #define TSEC_DMACTL_GTS (1<<(31-28)) |
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202 | #define TSEC_DMACTL_WWR (1<<(31-30)) |
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203 | #define TSEC_DMACTL_WOP (1<<(31-31)) |
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204 | |
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205 | /* |
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206 | * TSEC TSTAT bit definitions |
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207 | */ |
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208 | #define TSEC_TSTAT_THLT (1<<(31-0)) |
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209 | |
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210 | /* |
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211 | * TSEC RSTAT bit definitions |
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212 | */ |
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213 | #define TSEC_RSTAT_QHLT (1<<(31-8)) |
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214 | /* |
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215 | * TSEC ECNTRL bit positions |
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216 | */ |
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217 | #define TSEC_ECNTRL_CLRCNT (1 << (31-17)) /* Clear stat counters */ |
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218 | #define TSEC_ECNTRL_AUTOZ (1 << (31-18)) /* auto-zero read counters */ |
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219 | #define TSEC_ECNTRL_STEN (1 << (31-19)) /* enable statistics */ |
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220 | #define TSEC_ECNTRL_TBIM (1 << (31-26)) /* ten-bit-interface */ |
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221 | #define TSEC_ECNTRL_RPM (1 << (31-27)) /* reduced signal mode */ |
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222 | #define TSEC_ECNTRL_R100M (1 << (31-28)) /* RGMII100 mode */ |
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223 | /* |
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224 | * TSEC EDIS bit positions |
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225 | */ |
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226 | #define TSEC_EDIS_BSYDIS (1 << (31- 2)) /* Busy disable */ |
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227 | #define TSEC_EDIS_EBERRDIS (1 << (31- 3)) /* bus error disable */ |
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228 | #define TSEC_EDIS_TXEDIS (1 << (31- 9)) /* Tx error disable */ |
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229 | #define TSEC_EDIS_LCDIS (1 << (31-13)) /* Late collision disable */ |
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230 | #define TSEC_EDIS_CRLXDADIS (1 << (31-14)) /* Collision Retry disable */ |
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231 | #define TSEC_EDIS_FUNDIS (1 << (31-15)) /* Tx FIFO underrun disable*/ |
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232 | |
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233 | /* |
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234 | * TSEC RCTRL bit positions |
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235 | */ |
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236 | #define TSEC_RCTRL_BC_REJ (1 << (31-27)) /* Broadcast Reject */ |
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237 | #define TSEC_RCTRL_PROM (1 << (31-28)) /* Promiscuous */ |
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238 | #define TSEC_RCTRL_RSF (1 << (31-29)) /* Receive short frames */ |
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239 | |
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240 | /* |
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241 | * TSEC TXIC bit positions |
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242 | */ |
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243 | #define TSEC_TXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ |
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244 | #define TSEC_TXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ |
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245 | #define TSEC_TXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ |
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246 | |
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247 | /* |
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248 | * TSEC RXIC bit positions |
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249 | */ |
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250 | #define TSEC_RXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ |
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251 | #define TSEC_RXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ |
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252 | #define TSEC_RXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ |
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253 | |
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254 | /* |
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255 | * TSEC MACCFG1 bit positions |
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256 | */ |
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257 | #define TSEC_MACCFG1_SOFTRST (1 << (31- 0)) /* Soft Reset */ |
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258 | #define TSEC_MACCFG1_RES_RXMC (1 << (31-12)) /* Reset Rx MAC block */ |
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259 | #define TSEC_MACCFG1_RES_TXMC (1 << (31-13)) /* Reset Tx MAC block */ |
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260 | #define TSEC_MACCFG1_RES_RXFUN (1 << (31-14)) /* Reset Rx function blk*/ |
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261 | #define TSEC_MACCFG1_RES_TXFUN (1 << (31-15)) /* Reset Tx function blk*/ |
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262 | #define TSEC_MACCFG1_LOOPBACK (1 << (31-23)) /* Loopback mode */ |
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263 | #define TSEC_MACCFG1_RX_FLOW (1 << (31-26)) /* Receive Flow Ctrl */ |
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264 | #define TSEC_MACCFG1_TX_FLOW (1 << (31-27)) /* Transmit Flow Ctrl */ |
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265 | #define TSEC_MACCFG1_SYNVRXEN (1 << (31-28)) /* Sync Receive Enable */ |
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266 | #define TSEC_MACCFG1_RXEN (1 << (31-29)) /* Receive Enable */ |
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267 | #define TSEC_MACCFG1_SYNVTXEN (1 << (31-30)) /* Sync Transmit Enable */ |
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268 | #define TSEC_MACCFG1_TXEN (1 << (31-31)) /* Transmit Enable */ |
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269 | |
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270 | /* |
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271 | * TSEC MACCFG2 bit positions |
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272 | */ |
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273 | #define TSEC_MACCFG2_PRELEN(n) (((n)&0x0f) << (31-19)) /* Preamble len*/ |
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274 | |
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275 | #define TSEC_MACCFG2_IFMODE_MSK (3 << (31-23)) /* mode mask */ |
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276 | #define TSEC_MACCFG2_IFMODE_NIB (1 << (31-23)) /* nibble mode */ |
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277 | #define TSEC_MACCFG2_IFMODE_BYT (2 << (31-23)) /* byte mode */ |
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278 | |
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279 | #define TSEC_MACCFG2_HUGE_FRAME (1 << (31-26)) /* Huge Frame */ |
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280 | #define TSEC_MACCFG2_LENGTH_CHK (1 << (31-27)) /* Length Check */ |
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281 | #define TSEC_MACCFG2_PAD_CRC (1 << (31-29)) /* MAC adds PAD/CRC */ |
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282 | #define TSEC_MACCFG2_CRC_EN (1 << (31-30)) /* CRC enable */ |
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283 | #define TSEC_MACCFG2_FULLDUPLEX (1 << (31-31)) /* Full Duplex Mode */ |
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284 | |
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285 | /* |
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286 | * TSEC MIIMADD bit positions |
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287 | */ |
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288 | #define TSEC_MIIMADD_PHY(n) (((n) & 0x3f)<<(31- 23)) /* PHY addr */ |
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289 | #define TSEC_MIIMADD_REGADDR(n) (((n) & 0x3f)<<(31- 31)) /* PHY addr */ |
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290 | |
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291 | /* |
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292 | * TSEC MIIMCOM bit positions |
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293 | */ |
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294 | #define TSEC_MIIMCOM_SCAN (1 << (31-30)) /* Scan command */ |
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295 | #define TSEC_MIIMCOM_READ (1 << (31-31)) /* Read command */ |
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296 | |
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297 | /* |
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298 | * TSEC MIIMIND bit positions |
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299 | */ |
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300 | #define TSEC_MIIMIND_NVAL (1 << (31-29)) /* not valid */ |
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301 | #define TSEC_MIIMIND_SCAN (1 << (31-30)) /* Scan in progress */ |
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302 | #define TSEC_MIIMIND_BUSY (1 << (31-31)) /* Acc. in progress */ |
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303 | |
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304 | /* |
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305 | * TSEC ATTR bit positions |
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306 | */ |
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307 | #define TSEC_ATTR_RDSEN (1 << (31-24)) /* read data snoop */ |
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308 | #define TSEC_ATTR_RBDSEN (1 << (31-25)) /* read BD snoop */ |
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309 | |
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310 | typedef struct { |
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311 | volatile uint16_t status; |
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312 | volatile uint16_t length; |
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313 | volatile void *buffer; |
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314 | } PQBufferDescriptor_t; |
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315 | |
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316 | /* |
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317 | * Bits in receive buffer descriptor status word |
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318 | */ |
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319 | #define BD_EMPTY (1<<15) |
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320 | #define BD_RO1 (1<<14) |
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321 | #define BD_WRAP (1<<13) |
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322 | #define BD_INTERRUPT (1<<12) |
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323 | #define BD_LAST (1<<11) |
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324 | #define BD_CONTROL_CHAR (1<<11) |
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325 | #define BD_FIRST_IN_FRAME (1<<10) |
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326 | #define BD_MISS (1<<8) |
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327 | #define BD_BROADCAST (1<<7) |
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328 | #define BD_MULTICAST (1<<6) |
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329 | #define BD_LONG (1<<5) |
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330 | #define BD_NONALIGNED (1<<4) |
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331 | #define BD_SHORT (1<<3) |
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332 | #define BD_CRC_ERROR (1<<2) |
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333 | #define BD_OVERRUN (1<<1) |
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334 | #define BD_COLLISION (1<<0) |
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335 | |
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336 | /* |
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337 | * Bits in transmit buffer descriptor status word |
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338 | * Many bits have the same meaning as those in receiver buffer descriptors. |
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339 | */ |
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340 | #define BD_READY (1<<15) |
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341 | #define BD_PAD_CRC (1<<14) |
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342 | /* WRAP/Interrupt as in Rx BDs */ |
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343 | #define BD_TX_CRC (1<<10) |
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344 | #define BD_DEFER (1<<9) |
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345 | #define BD_TO1 (1<<8) |
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346 | #define BD_HFE_ (1<<7) |
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347 | #define BD_LATE_COLLISION (1<<7) |
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348 | #define BD_RETRY_LIMIT (1<<6) |
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349 | #define BD_RETRY_COUNT(x) (((x)&0x3C)>>2) |
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350 | #define BD_UNDERRUN (1<<1) |
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351 | #define BD_TXTRUNC (1<<0) |
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352 | |
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353 | struct rtems_bsdnet_ifconfig; |
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354 | |
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355 | typedef struct { |
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356 | int unit_number; |
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357 | char *unit_name; |
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358 | volatile tsec_registers *reg_ptr; |
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359 | volatile tsec_registers *mdio_ptr; |
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360 | rtems_irq_number irq_num_tx; |
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361 | rtems_irq_number irq_num_rx; |
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362 | rtems_irq_number irq_num_err; |
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363 | int phy_default; |
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364 | } tsec_config; |
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365 | |
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366 | int tsec_driver_attach_detach( |
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367 | struct rtems_bsdnet_ifconfig *config, |
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368 | int attaching |
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369 | ); |
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370 | |
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371 | #ifdef __cplusplus |
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372 | } |
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373 | #endif /* __cplusplus */ |
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374 | |
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375 | #endif /* LIBCPU_POWERPC_TSEC_H */ |
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