[502609c8] | 1 | /* |
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| 2 | |
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| 3 | Low-level interface to the PPC405 MMU |
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| 4 | |
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| 5 | M.Hamel ADInstruments 2008 |
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| 6 | |
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| 7 | */ |
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| 8 | |
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| 9 | #include <rtems/asm.h> |
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| 10 | |
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| 11 | /* Useful MMU SPR values */ |
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| 12 | |
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| 13 | #define SPR_ZPR 0x3B0 |
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| 14 | #define SPR_PID 0x3B1 |
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| 15 | |
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| 16 | .text |
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| 17 | |
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| 18 | /* void MMU_ClearTLBs(); */ |
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| 19 | PUBLIC_VAR(MMU_ClearTLBs) |
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| 20 | SYM (MMU_ClearTLBs): |
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| 21 | tlbia |
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| 22 | isync |
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| 23 | lis r3,0x5555 // *** Gratuitous fiddle of ZPR to 0101010101 to take it out of |
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| 24 | mtspr SPR_ZPR,r3 // the picture |
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| 25 | blr |
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| 26 | |
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| 27 | /* void MMU_SetTLBEntry(UInt8 index, UInt32 tagword, UInt32 dataword, UInt8 SPR_PID) */ |
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| 28 | PUBLIC_VAR(MMU_SetTLBEntry) |
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| 29 | SYM (MMU_SetTLBEntry): |
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| 30 | mfspr r7,SPR_PID // Save the current SPR_PID |
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| 31 | mtspr SPR_PID,r6 // Write to SPR_PID |
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| 32 | tlbwehi r4,r3 // Write hiword |
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| 33 | mtspr SPR_PID,r7 // Restore the SPR_PID |
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| 34 | tlbwelo r5,r3 // Write loword |
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| 35 | isync |
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| 36 | blr |
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| 37 | |
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| 38 | /* void MMU_GetTLBEntry(UInt8 index, UInt32& tagword, UInt32& dataword, UInt8& SPR_PID) */ |
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| 39 | PUBLIC_VAR(MMU_GetTLBEntry) |
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| 40 | SYM (MMU_GetTLBEntry): |
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| 41 | mfspr r7,SPR_PID // Save the current SPR_PID |
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| 42 | tlbrehi r8,r3 // Read hiword & SPR_PID |
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| 43 | mfspr r9,SPR_PID // Copy the SPR_PID |
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| 44 | mtspr SPR_PID,r7 // Restore original SPR_PID so we can proceed |
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| 45 | stw r8,0(r4) // Write to r4 pointer |
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| 46 | stb r9,0(r6) // Write to r6 pointer |
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| 47 | tlbrelo r8,r3 // Read loword |
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| 48 | stw r8,0(r5) // Write to r5 pointer |
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| 49 | blr |
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| 50 | |
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| 51 | /* SInt16 MMU_FindTLBEntry(UInt32 address) */ |
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| 52 | /* Returns index of covering TLB entry (0..63), or -1 if there isn't one */ |
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| 53 | PUBLIC_VAR(MMU_FindTLBEntry) |
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| 54 | SYM (MMU_FindTLBEntry): |
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| 55 | tlbsx. r3,0,r3 |
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| 56 | beqlr |
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| 57 | li r3,0xFFFFFFFF |
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| 58 | blr |
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| 59 | |
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| 60 | /* bool mmu_enable_code(bool enable); */ |
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| 61 | PUBLIC_VAR(mmu_enable_code) |
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| 62 | SYM (mmu_enable_code): |
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| 63 | li r5,0x20 // IR bit |
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| 64 | b msrbits |
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| 65 | |
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| 66 | /* bool mmu_enable_data(bool enable); */ |
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| 67 | PUBLIC_VAR(mmu_enable_data) |
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| 68 | SYM (mmu_enable_data): |
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| 69 | li r5,0x10 // DR bit |
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| 70 | msrbits: cmpwi r3,0 // Common code: parameter 0? |
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| 71 | mfmsr r4 // r4 = MSR state |
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| 72 | beq clrBit |
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| 73 | or r6,r4,r5 // If 1, r6 = MSR with bit set |
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| 74 | b setmsr |
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| 75 | clrBit: andc r6,r4,r5 // If 0 r6 = MSR with bit clear |
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| 76 | setmsr: mtmsr r6 // Write new MSR |
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| 77 | and. r3,r4,r5 // Result = old MSR bit |
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| 78 | beqlr // If zero return zero |
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| 79 | li r3,0xFF // If nonzero return byte -1 |
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| 80 | blr |
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| 81 | |
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| 82 | |
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| 83 | |
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