[f57aa10] | 1 | /* |
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| 2 | * This routine does the bulk of the system initialization. |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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[c4515a1] | 6 | * Author: Thomas Doerfler <td@imd.m.isar.de> |
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[3c6fe2e] | 7 | * IMD Ingenieurbuero fuer Microcomputertechnik |
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| 8 | * |
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| 9 | * COPYRIGHT (c) 1998 by IMD |
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| 10 | * |
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| 11 | * Changes from IMD are covered by the original distributions terms. |
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| 12 | * This file has been derived from the papyrus BSP: |
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| 13 | * |
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[c4515a1] | 14 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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[3c6fe2e] | 15 | * |
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| 16 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 17 | * |
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| 18 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 19 | * without any express or implied warranty: |
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| 20 | * permission to use, copy, modify, and distribute this file |
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| 21 | * for any purpose is hereby granted without fee, provided that |
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| 22 | * the above copyright notice and this notice appears in all |
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| 23 | * copies, and that the name of i-cubed limited not be used in |
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| 24 | * advertising or publicity pertaining to distribution of the |
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| 25 | * software without specific, written prior permission. |
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| 26 | * i-cubed limited makes no representations about the suitability |
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| 27 | * of this software for any purpose. |
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| 28 | * |
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| 29 | * Modifications for spooling console driver and control of memory layout |
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| 30 | * with linker command file by |
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| 31 | * Thomas Doerfler <td@imd.m.isar.de> |
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| 32 | * for these modifications: |
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| 33 | * COPYRIGHT (c) 1997 by IMD, Puchheim, Germany. |
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| 34 | * |
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| 35 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 36 | * without any express or implied warranty: |
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| 37 | * permission to use, copy, modify, and distribute this file |
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| 38 | * for any purpose is hereby granted without fee, provided that |
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| 39 | * the above copyright notice and this notice appears in all |
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| 40 | * copies. IMD makes no representations about the suitability |
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| 41 | * of this software for any purpose. |
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| 42 | * |
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| 43 | * Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/bspstart.c: |
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| 44 | * |
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| 45 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 46 | * On-Line Applications Research Corporation (OAR). |
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| 47 | * |
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| 48 | * Modifications for PPC405GP by Dennis Ehlin |
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| 49 | * |
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| 50 | * Further modified for the PPC405EX Haleakala board by |
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| 51 | * Michael Hamel ADInstruments Ltd May 2008 |
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| 52 | */ |
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| 53 | #include <string.h> |
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| 54 | #include <fcntl.h> |
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| 55 | |
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[1c77a36] | 56 | #include <rtems/bspIo.h> |
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[24bf11e] | 57 | #include <rtems/counter.h> |
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| 58 | |
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[3c6fe2e] | 59 | #include <bsp.h> |
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[f57aa10] | 60 | #include <bsp/bootcard.h> |
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[3c6fe2e] | 61 | #include <bsp/uart.h> |
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| 62 | #include <bsp/irq.h> |
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[2d2de4eb] | 63 | #include <libcpu/powerpc-utility.h> |
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| 64 | #include <bsp/vectors.h> |
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[3c6fe2e] | 65 | #include <ppc4xx/ppc405gp.h> |
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| 66 | #include <ppc4xx/ppc405ex.h> |
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| 67 | |
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| 68 | #include <stdio.h> |
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| 69 | |
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[39a9f8e] | 70 | LINKER_SYMBOL(intrStack_start); |
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| 71 | LINKER_SYMBOL(intrStack_size); |
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[3c6fe2e] | 72 | /* |
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| 73 | * Driver configuration parameters |
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| 74 | */ |
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| 75 | |
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| 76 | /* Expected by clock.c */ |
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[c4515a1] | 77 | uint32_t bsp_clicks_per_usec; |
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[3c6fe2e] | 78 | |
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| 79 | /*-------------------- Haleakala-specific UART setup -------------------------*/ |
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| 80 | |
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| 81 | static void |
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| 82 | EarlyUARTInit(int baudRate) |
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| 83 | { |
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[ec11156e] | 84 | volatile uint8_t* up = (uint8_t*)(BSP_UART_IOBASE_COM1); |
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[c4515a1] | 85 | int divider = BSP_UART_BAUD_BASE / baudRate; |
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| 86 | up[LCR] = DLAB; /* Access DLM/DLL */ |
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| 87 | up[DLL] = divider & 0x0FF; |
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| 88 | up[DLM] = divider >> 8; |
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| 89 | up[LCR] = CHR_8_BITS; |
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| 90 | up[MCR] = DTR | RTS; |
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| 91 | up[FCR] = FIFO_EN | XMIT_RESET | RCV_RESET; |
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| 92 | up[THR] = '+'; |
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[3c6fe2e] | 93 | } |
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| 94 | |
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| 95 | |
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| 96 | static void |
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[378bea5] | 97 | InitUARTClock(void) |
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[3c6fe2e] | 98 | { |
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[c4515a1] | 99 | uint32_t reg; |
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| 100 | mfsdr(SDR0_UART0,reg); |
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| 101 | reg &= ~0x008000FF; |
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| 102 | reg |= 0x00800001; /* Ext clock, div 1 */ |
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| 103 | mtsdr(SDR0_UART0,reg); |
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[3c6fe2e] | 104 | } |
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| 105 | |
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[59888da] | 106 | static void GPIO_AlternateSelect(int bitnum, int source) |
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[3c6fe2e] | 107 | /* PPC405EX: select a GPIO function for the specified pin */ |
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| 108 | { |
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[c4515a1] | 109 | int shift; |
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| 110 | unsigned long value, mask; |
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| 111 | GPIORegisters* gpioPtr = (GPIORegisters*)(GPIOAddress); |
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| 112 | |
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| 113 | shift = (31 - bitnum) & 0xF; |
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| 114 | value = (source & 3) << (shift*2); |
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| 115 | mask = 3 << (shift*2); |
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| 116 | if (bitnum <= 15) { |
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| 117 | gpioPtr->OSRL = (gpioPtr->OSRL & ~mask) | value; |
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| 118 | gpioPtr->TSRL = (gpioPtr->TSRL & ~mask) | value; |
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| 119 | } else { |
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| 120 | gpioPtr->OSRH = (gpioPtr->OSRH & ~mask) | value; |
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| 121 | gpioPtr->TSRH = (gpioPtr->TSRH & ~mask) | value; |
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| 122 | } |
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[3c6fe2e] | 123 | } |
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| 124 | |
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[59888da] | 125 | static void Init_FPGA(void) |
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[3c6fe2e] | 126 | { |
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[c4515a1] | 127 | /* Have to write to the FPGA to enable the UART drivers */ |
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| 128 | /* Have to enable CS2 as an output in GPIO to get the FPGA working */ |
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| 129 | mtebc(EBC0_B2CR,0xF0018000); /* Set up CS2 at 0xF0000000 */ |
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| 130 | mtebc(EBC0_B2AP,0x9400C800); |
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| 131 | GPIO_AlternateSelect(9,1); /* GPIO9 = PerCS2 */ |
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| 132 | { |
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| 133 | unsigned long *fpgaPtr = (unsigned long*)(0xF0000000); |
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| 134 | unsigned long n; |
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| 135 | n = *(fpgaPtr); |
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| 136 | n &= ~0x00100; /* User LEDs on */ |
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| 137 | n |= 0x30000; /* UART 0 and 1 transcievers on! */ |
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| 138 | *fpgaPtr = n; |
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| 139 | } |
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[3c6fe2e] | 140 | } |
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| 141 | |
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| 142 | /*===================================================================*/ |
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| 143 | |
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| 144 | static void |
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| 145 | DirectUARTWrite(const char c) |
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| 146 | { |
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[ec11156e] | 147 | volatile uint8_t* up = (uint8_t*)(BSP_UART_IOBASE_COM1); |
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[c4515a1] | 148 | while ((up[LSR] & THRE) == 0) { ; } |
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| 149 | up[THR] = c; |
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[3c6fe2e] | 150 | } |
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| 151 | |
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| 152 | /* We will provide our own printk output function as it may get used early */ |
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[a90576b6] | 153 | BSP_output_char_function_type BSP_output_char = DirectUARTWrite; |
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| 154 | BSP_polling_getchar_function_type BSP_poll_char = NULL; |
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[3c6fe2e] | 155 | |
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| 156 | /*===================================================================*/ |
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| 157 | |
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| 158 | void bsp_start( void ) |
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| 159 | { |
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[c4515a1] | 160 | /* Get the UART clock initialized first in case we call printk */ |
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| 161 | |
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| 162 | InitUARTClock(); |
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| 163 | Init_FPGA(); |
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| 164 | EarlyUARTInit(115200); |
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| 165 | |
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| 166 | /* |
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[ac7af4a] | 167 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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| 168 | * function store the result in global variables |
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[c4515a1] | 169 | * so that it can be used later... |
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| 170 | */ |
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[59888da] | 171 | get_ppc_cpu_type(); |
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| 172 | get_ppc_cpu_revision(); |
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[c4515a1] | 173 | |
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| 174 | /* |
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| 175 | * initialize the device driver parameters |
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| 176 | */ |
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| 177 | |
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| 178 | /* Set globals visible to clock.c */ |
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| 179 | /* timebase register ticks/microsecond = CPU Clk in MHz */ |
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| 180 | bsp_clicks_per_usec = 400; |
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[24bf11e] | 181 | rtems_counter_initialize_converter(bsp_clicks_per_usec * 1000000); |
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[c4515a1] | 182 | |
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| 183 | /* |
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[ac7af4a] | 184 | * Initialize default raw exception handlers. |
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[c4515a1] | 185 | */ |
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[b1e8a58] | 186 | ppc_exc_initialize( |
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[2d2de4eb] | 187 | (uintptr_t) intrStack_start, |
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| 188 | (uintptr_t) intrStack_size |
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| 189 | ); |
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[c4515a1] | 190 | |
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| 191 | /* |
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| 192 | * Install our own set of exception vectors |
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| 193 | */ |
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| 194 | BSP_rtems_irq_mng_init(0); |
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[3c6fe2e] | 195 | } |
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