[f610e83f] | 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic MPC83xx BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Partially based on the code references which are named below. | |
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| 5 | | Adaptions, modifications, enhancements and any recent parts of | |
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| 6 | | the code are: | |
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| 7 | | Copyright (c) 2005 | |
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| 8 | | Embedded Brains GmbH | |
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| 9 | | Obere Lagerstr. 30 | |
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| 10 | | D-82178 Puchheim | |
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| 11 | | Germany | |
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| 12 | | rtems@embedded-brains.de | |
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| 13 | +-----------------------------------------------------------------+ |
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| 14 | | The license and distribution terms for this file may be | |
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| 15 | | found in the file LICENSE in this distribution or at | |
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| 16 | | | |
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[c499856] | 17 | | http://www.rtems.org/license/LICENSE. | |
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[f610e83f] | 18 | | | |
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| 19 | +-----------------------------------------------------------------+ |
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| 20 | | this file contains the code to initialize the cpu | |
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| 21 | \*===============================================================*/ |
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[dfef80e8] | 22 | |
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| 23 | |
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[f610e83f] | 24 | /***********************************************************************/ |
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| 25 | /* */ |
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| 26 | /* Module: cpuinit.c */ |
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| 27 | /* Date: 07/17/2003 */ |
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| 28 | /* Purpose: RTEMS MPC5x00 C level startup code */ |
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| 29 | /* */ |
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| 30 | /*---------------------------------------------------------------------*/ |
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| 31 | /* */ |
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| 32 | /* Description: This file contains additional functions for */ |
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| 33 | /* initializing the MPC5x00 CPU */ |
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| 34 | /* */ |
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| 35 | /*---------------------------------------------------------------------*/ |
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| 36 | /* */ |
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| 37 | /* Code */ |
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| 38 | /* References: MPC8260ads additional CPU initialization */ |
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| 39 | /* Module: cpuinit.c */ |
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| 40 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
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| 41 | /* Version 1.1 */ |
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| 42 | /* Date: 10/22/2002 */ |
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| 43 | /* */ |
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| 44 | /* Author(s) / Copyright(s): */ |
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| 45 | /* */ |
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| 46 | /* Written by Jay Monkman (jmonkman@frasca.com) */ |
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| 47 | /* */ |
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| 48 | /*---------------------------------------------------------------------*/ |
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| 49 | /* */ |
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| 50 | /* Partially based on the code references which are named above. */ |
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| 51 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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| 52 | /* the code are under the right of */ |
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| 53 | /* */ |
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| 54 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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| 55 | /* Copyright(C) 2003 */ |
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| 56 | /* */ |
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| 57 | /*---------------------------------------------------------------------*/ |
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| 58 | /* */ |
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| 59 | /* IPR Engineering makes no representation or warranties with */ |
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| 60 | /* respect to the performance of this computer program, and */ |
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| 61 | /* specifically disclaims any responsibility for any damages, */ |
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| 62 | /* special or consequential, connected with the use of this program. */ |
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| 63 | /* */ |
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| 64 | /*---------------------------------------------------------------------*/ |
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| 65 | /* */ |
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| 66 | /* Version history: 1.0 */ |
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| 67 | /* */ |
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| 68 | /***********************************************************************/ |
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| 69 | |
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[d79a27be] | 70 | #include <stdbool.h> |
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| 71 | #include <string.h> |
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[f610e83f] | 72 | |
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[d79a27be] | 73 | #include <libcpu/powerpc-utility.h> |
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[f610e83f] | 74 | #include <libcpu/mmu.h> |
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| 75 | |
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[d79a27be] | 76 | #include <mpc83xx/mpc83xx.h> |
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| 77 | |
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| 78 | #include <bsp.h> |
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[ce0922e] | 79 | #include <bsp/u-boot.h> |
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[d79a27be] | 80 | |
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| 81 | #define SET_DBAT( n, uv, lv) \ |
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| 82 | do { \ |
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| 83 | PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##L, lv); \ |
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| 84 | PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##U, uv); \ |
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| 85 | } while (0) |
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| 86 | |
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| 87 | #define SET_IBAT( n, uv, lv) \ |
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| 88 | do { \ |
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| 89 | PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##L, lv); \ |
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| 90 | PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##U, uv); \ |
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| 91 | } while (0) |
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| 92 | |
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| 93 | static void calc_dbat_regvals( |
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| 94 | BAT *bat_ptr, |
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| 95 | uint32_t base_addr, |
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| 96 | uint32_t size, |
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| 97 | bool flg_w, |
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| 98 | bool flg_i, |
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| 99 | bool flg_m, |
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| 100 | bool flg_g, |
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| 101 | uint32_t flg_bpp |
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| 102 | ) |
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[f610e83f] | 103 | { |
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[d79a27be] | 104 | uint32_t block_mask = 0xffffffff; |
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| 105 | uint32_t end_addr = base_addr + size - 1; |
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[f610e83f] | 106 | |
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[d79a27be] | 107 | /* Determine block mask, that overlaps the whole block */ |
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[f610e83f] | 108 | while ((end_addr & block_mask) != (base_addr & block_mask)) { |
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| 109 | block_mask <<= 1; |
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| 110 | } |
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[ac7af4a] | 111 | |
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| 112 | bat_ptr->batu.bepi = base_addr >> (32 - 15); |
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[d79a27be] | 113 | bat_ptr->batu.bl = ~(block_mask >> (28 - 11)); |
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| 114 | bat_ptr->batu.vs = 1; |
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| 115 | bat_ptr->batu.vp = 1; |
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[ac7af4a] | 116 | |
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| 117 | bat_ptr->batl.brpn = base_addr >> (32 - 15); |
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| 118 | bat_ptr->batl.w = flg_w; |
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| 119 | bat_ptr->batl.i = flg_i; |
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| 120 | bat_ptr->batl.m = flg_m; |
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| 121 | bat_ptr->batl.g = flg_g; |
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| 122 | bat_ptr->batl.pp = flg_bpp; |
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[f610e83f] | 123 | } |
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| 124 | |
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[d79a27be] | 125 | static void clear_mmu_regs( void) |
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[f610e83f] | 126 | { |
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| 127 | uint32_t i; |
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[d79a27be] | 128 | |
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| 129 | /* Clear segment registers */ |
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[f610e83f] | 130 | for (i = 0;i < 16;i++) { |
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[0d01467b] | 131 | __asm__ volatile( "mtsrin %0, %1\n" : : "r" (i * 0x1000), "r" (i << (31 - 3))); |
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[f610e83f] | 132 | } |
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[ac7af4a] | 133 | |
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[d79a27be] | 134 | /* Clear TLBs */ |
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[f610e83f] | 135 | for (i = 0;i < 32;i++) { |
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[0d01467b] | 136 | __asm__ volatile( "tlbie %0\n" : : "r" (i << (31 - 19))); |
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[f610e83f] | 137 | } |
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| 138 | } |
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| 139 | |
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[d79a27be] | 140 | void cpu_init( void) |
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[f610e83f] | 141 | { |
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[d79a27be] | 142 | BAT dbat, ibat; |
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| 143 | uint32_t msr; |
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[bfde536e] | 144 | uint32_t hid0; |
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[f610e83f] | 145 | |
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[d79a27be] | 146 | /* Clear MMU and segment registers */ |
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[f610e83f] | 147 | clear_mmu_regs(); |
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[d79a27be] | 148 | |
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| 149 | /* Clear caches */ |
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[bfde536e] | 150 | hid0 = PPC_SPECIAL_PURPOSE_REGISTER(HID0); |
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| 151 | if ((hid0 & (HID0_ICE | HID0_DCE)) == 0) { |
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| 152 | hid0 &= ~(HID0_ILOCK | HID0_DLOCK | HID0_ICE | HID0_DCE); |
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| 153 | PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0); |
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| 154 | hid0 |= HID0_ICFI | HID0_DCI; |
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| 155 | PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0); |
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| 156 | hid0 &= ~(HID0_ICFI | HID0_DCI); |
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| 157 | PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0); |
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| 158 | } |
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[ac7af4a] | 159 | |
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[f610e83f] | 160 | /* |
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[d79a27be] | 161 | * Set up IBAT registers in MMU |
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[f610e83f] | 162 | */ |
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| 163 | |
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[d79a27be] | 164 | memset(&ibat, 0, sizeof( ibat)); |
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| 165 | SET_IBAT( 2, ibat.batu, ibat.batl); |
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| 166 | SET_IBAT( 3, ibat.batu, ibat.batl); |
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| 167 | SET_IBAT( 4, ibat.batu, ibat.batl); |
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| 168 | SET_IBAT( 5, ibat.batu, ibat.batl); |
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| 169 | SET_IBAT( 6, ibat.batu, ibat.batl); |
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| 170 | SET_IBAT( 7, ibat.batu, ibat.batl); |
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| 171 | |
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| 172 | calc_dbat_regvals( |
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| 173 | &ibat, |
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| 174 | #ifdef HAS_UBOOT |
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[f044f9c] | 175 | bsp_uboot_board_info.bi_memstart, |
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| 176 | bsp_uboot_board_info.bi_memsize, |
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[d79a27be] | 177 | #else /* HAS_UBOOT */ |
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| 178 | (uint32_t) bsp_ram_start, |
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| 179 | (uint32_t) bsp_ram_size, |
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| 180 | #endif /* HAS_UBOOT */ |
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| 181 | false, |
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| 182 | false, |
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| 183 | false, |
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| 184 | false, |
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| 185 | BPP_RX |
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| 186 | ); |
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| 187 | SET_IBAT( 0, ibat.batu, ibat.batl); |
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[f610e83f] | 188 | |
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[d79a27be] | 189 | calc_dbat_regvals( |
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| 190 | &ibat, |
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| 191 | #ifdef HAS_UBOOT |
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[f044f9c] | 192 | bsp_uboot_board_info.bi_flashstart, |
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| 193 | bsp_uboot_board_info.bi_flashsize, |
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[d79a27be] | 194 | #else /* HAS_UBOOT */ |
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| 195 | (uint32_t) bsp_rom_start, |
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| 196 | (uint32_t) bsp_rom_size, |
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| 197 | #endif /* HAS_UBOOT */ |
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| 198 | false, |
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| 199 | false, |
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| 200 | false, |
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| 201 | false, |
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| 202 | BPP_RX |
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| 203 | ); |
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| 204 | SET_IBAT( 1, ibat.batu, ibat.batl); |
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[574fb67] | 205 | |
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[d79a27be] | 206 | /* |
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| 207 | * Set up DBAT registers in MMU |
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| 208 | */ |
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[f610e83f] | 209 | |
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[d79a27be] | 210 | memset(&dbat, 0, sizeof( dbat)); |
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| 211 | SET_DBAT( 3, dbat.batu, dbat.batl); |
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| 212 | SET_DBAT( 4, dbat.batu, dbat.batl); |
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| 213 | SET_DBAT( 5, dbat.batu, dbat.batl); |
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| 214 | SET_DBAT( 6, dbat.batu, dbat.batl); |
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| 215 | SET_DBAT( 7, dbat.batu, dbat.batl); |
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[574fb67] | 216 | |
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[d79a27be] | 217 | calc_dbat_regvals( |
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| 218 | &dbat, |
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| 219 | #ifdef HAS_UBOOT |
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[f044f9c] | 220 | bsp_uboot_board_info.bi_memstart, |
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| 221 | bsp_uboot_board_info.bi_memsize, |
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[d79a27be] | 222 | #else /* HAS_UBOOT */ |
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| 223 | (uint32_t) bsp_ram_start, |
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| 224 | (uint32_t) bsp_ram_size, |
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| 225 | #endif /* HAS_UBOOT */ |
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| 226 | false, |
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| 227 | false, |
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| 228 | false, |
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| 229 | false, |
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| 230 | BPP_RW |
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| 231 | ); |
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| 232 | SET_DBAT( 0, dbat.batu, dbat.batl); |
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[f610e83f] | 233 | |
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[d79a27be] | 234 | calc_dbat_regvals( |
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| 235 | &dbat, |
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| 236 | #ifdef HAS_UBOOT |
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[f044f9c] | 237 | bsp_uboot_board_info.bi_flashstart, |
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| 238 | bsp_uboot_board_info.bi_flashsize, |
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[d79a27be] | 239 | #else /* HAS_UBOOT */ |
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| 240 | (uint32_t) bsp_rom_start, |
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| 241 | (uint32_t) bsp_rom_size, |
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| 242 | #endif /* HAS_UBOOT */ |
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[907b07d9] | 243 | #ifdef MPC83XX_HAS_NAND_LP_FLASH_ON_CS0 |
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| 244 | false, |
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| 245 | true, |
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| 246 | false, |
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| 247 | true, |
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| 248 | BPP_RW |
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| 249 | #else |
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| 250 | true, |
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| 251 | false, |
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| 252 | false, |
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| 253 | false, |
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| 254 | BPP_RX |
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| 255 | #endif |
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[d79a27be] | 256 | ); |
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| 257 | SET_DBAT( 1, dbat.batu, dbat.batl); |
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[574fb67] | 258 | |
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[d79a27be] | 259 | calc_dbat_regvals( |
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| 260 | &dbat, |
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| 261 | #ifdef HAS_UBOOT |
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[f044f9c] | 262 | bsp_uboot_board_info.bi_immrbar, |
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[d79a27be] | 263 | #else /* HAS_UBOOT */ |
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| 264 | (uint32_t) IMMRBAR, |
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| 265 | #endif /* HAS_UBOOT */ |
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[a3db5ff4] | 266 | #if MPC83XX_CHIP_TYPE / 10 == 830 |
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| 267 | 2 * 1024 * 1024, |
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| 268 | #else |
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| 269 | 1024 * 1024, |
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| 270 | #endif |
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[d79a27be] | 271 | false, |
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| 272 | true, |
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| 273 | false, |
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| 274 | true, |
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| 275 | BPP_RW |
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| 276 | ); |
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| 277 | SET_DBAT( 2, dbat.batu, dbat.batl); |
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[f610e83f] | 278 | |
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[7a752161] | 279 | #if defined(MPC83XX_BOARD_HSC_CM01) |
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[4b23c94] | 280 | calc_dbat_regvals( |
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| 281 | &dbat, |
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| 282 | FPGA_START, |
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| 283 | FPGA_SIZE, |
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| 284 | true, |
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| 285 | true, |
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| 286 | true, |
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| 287 | false, |
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| 288 | BPP_RW |
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| 289 | ); |
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| 290 | SET_DBAT(3,dbat.batu,dbat.batl); |
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| 291 | #endif |
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| 292 | |
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[7a752161] | 293 | #ifdef MPC83XX_BOARD_MPC8313ERDB |
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[541c9e84] | 294 | /* Enhanced Local Bus Controller (eLBC) */ |
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[d79a27be] | 295 | calc_dbat_regvals( |
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| 296 | &dbat, |
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| 297 | 0xfa000000, |
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| 298 | 128 * 1024, |
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| 299 | false, |
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| 300 | true, |
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| 301 | false, |
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| 302 | true, |
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| 303 | BPP_RW |
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| 304 | ); |
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[541c9e84] | 305 | SET_DBAT( 3, dbat.batu, dbat.batl); |
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[7a752161] | 306 | #endif /* MPC83XX_BOARD_MPC8313ERDB */ |
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[541c9e84] | 307 | |
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[d79a27be] | 308 | /* Read MSR */ |
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| 309 | msr = ppc_machine_state_register(); |
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[f610e83f] | 310 | |
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[d79a27be] | 311 | /* Enable data and instruction MMU in MSR */ |
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| 312 | msr |= MSR_DR | MSR_IR; |
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[f610e83f] | 313 | |
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[d79a27be] | 314 | /* Enable FPU in MSR */ |
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| 315 | msr |= MSR_FP; |
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| 316 | |
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| 317 | /* Update MSR */ |
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| 318 | ppc_set_machine_state_register( msr); |
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[f610e83f] | 319 | |
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| 320 | /* |
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[ac7af4a] | 321 | * In HID0: |
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[d79a27be] | 322 | * - Enable dynamic power management |
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| 323 | * - Enable machine check interrupts |
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[f610e83f] | 324 | */ |
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[d79a27be] | 325 | PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_EMCP | HID0_DPM); |
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| 326 | |
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| 327 | /* Enable timebase clock */ |
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[f610e83f] | 328 | mpc83xx.syscon.spcr |= M83xx_SYSCON_SPCR_TBEN; |
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| 329 | } |
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